JPS6242394B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a protection device for integrated circuits.

Many types of electrical equipment include integrated circuit devices that are susceptible to damage from high voltage transients.

For example, in television receivers having integrated circuits for video and audio signal processing, the anode of the picture tube for displaying images is typically biased to a high potential, for example 2500V. The high voltage transient is caused by the arc discharge that occurs when the high voltage anode of the picture tube is rapidly discharged. Even when the television receiver is in normal operating conditions, a discharge occurs between the picture tube anode and one or more of the other low potential electrodes. In either case, the picture tube discharge produces high voltage transients at the integrated circuit terminals, often with positive and negative peaks of 100 volts or more, lasting one to several microseconds.

Another source of high voltage transients in television receivers is electrostatic discharge. The accumulated static charge is discharged by the user's control of the television receiver, thereby creating high voltage transients that can damage the television receiver's integrated circuits.

The invention is implemented in a semiconductor protection circuit for an integrated circuit that includes a pair of transistors of complementary conductivity types and a resistance element (linear or nonlinear) integral with the semiconductor structure. The pair of complementary conductivity transistors and the resistive element are arranged to form a two-terminal device capable of conducting a high current when the potential difference between the two terminals exceeds a predetermined threshold. One terminal of the protection circuit is connected to a circuit terminal of the circuit to be protected, and the other terminal is connected to an operating power source.

When the potential at the circuit terminals of the circuit to be protected increases above the operating power supply potential by a value equal to a predetermined threshold, the protection circuit becomes conductive and protects the integrated circuit from damage.

As shown in FIG. 1, a semiconductor circuit is fabricated on a substrate 10 of P-type silicon material. First, an N _- type epitaxial layer 12 is provided on a substrate 10 , a P type region 14 is formed therein, and a P type region 14 is formed between the N - type layer 12 and the N _- type epitaxial layer 12 .
Forms a PN junction. Further, another P type region 16 is formed within the N _- type epitaxial layer 12 to form a PN junction with the epitaxial layer 12. Further, an N ₊ type region 18 is formed within the P type region 16 to form a PN junction with the P type region 16. Another N ₊ type region 20 is formed within the N _- type epitaxial layer 12 . A buried N ₊ type pocket 11 is provided below P type regions 14 and 16.

For example _, 2
An insulating layer 22 of silicon oxide is provided, and regions 14,1
Insulating layer 22 above 8 and 20 is provided with openings for making electrical contact in each region thereof. Insulating layer 2
A conductive layer 26 of aluminum, for example, is provided on 2 to bring regions 18 and 20 into contact. Conductive layer 26 is further connected to terminal 30 for receiving a positive operating voltage V ₊ . A conductive layer 24, for example aluminum, is extended through the opening in the insulating layer 22 into contact with the region 14. A bonding pad 28 is connected to this region 14 via a conductive layer 24.
is further connected to an input or output terminal of a utilization circuit (not shown) located somewhere on the integrated circuit. P ₊ type region 32 extends from the surface of epitaxial layer 12 to substrate 10 and
The protection circuit is insulated from other circuits on the board 12 by surrounding it.

FIG. 2 is a circuit diagram of the structure of FIG. 1 in which the resistance element is linear. The protection circuit consists of an NPN transistor Q1, a PNP transistor Q2, and a linear resistance element shown as resistor R. Emitter electrode 118, base electrode 116, and collector electrode 112 of transistor Q1 correspond to regions 18, 16, and 12 of FIG. 1, respectively, and emitter electrode 114, base electrode 112, and collector electrode 116 of transistor Q2 correspond to regions 18, 16, and 12 of FIG. Corresponds to areas 14, 12 and 16. The resistor R designated 120 is Q2
base electrode 112 and emitter electrode 118 of Q1
and corresponds to the region of N _- type epitaxial layer 12 between P region 16 and N ₊ region 20 in FIG. The conductor 126 between the emitter electrode of transistor Q1 and resistor R corresponds to conductive layer 26 of FIG.

The value of the resistor R depends on the resistivity of the N _- type epitaxial layer 12 and the size and shape of the N _- type epitaxial layer between the P type region 16 and the N ₊ type region 20 (first
Figure). For example, the resistance of resistor R increases as N ₊ type region 20 is separated from P type region 16, and buried N ₊ type region 11 significantly reduces the resistance value of N _- type epitaxial layer 12. Therefore, the buried N ₊ type region 11 is similar to the P type regions 14 and 16.
Directly below the P type region 16 and N ₊ type region 20
It does not extend below the portion of the N _- type epitaxial layer 12 between.

In FIG. 2, transistors Q1 and Q2 are connected to form a silicon controlled rectifier (SCR). That is, the base electrode of Q1 is connected to the collector electrode of Q2, the base electrode of Q2 is connected to the collector electrode of Q1, and the resistor R is connected in parallel with the conductive path between the collector and emitter of the transistor Q1.

FIG. 3 shows a semiconductor circuit formed on a substrate 10 of typically P-type silicon material with a buried region 11 of N ₊ type. An N _- type epitaxial layer 12 is provided on a substrate 10, and a P type region 14 is formed within the N _- type epitaxial layer 12 to form a PN junction therebetween. There is further another P type region 16 within the N _- type epitaxial layer 12.
is formed to form a PN junction therebetween, and an N ₊ region 18 is formed within the P type region 16 to form a PN junction with the P type region 16. The combination of regions 12, 16 and 18 represent the collector-base and emitter, respectively, of transistor Q1. In this example, N _-
A P-type region 38 is formed within the type epitaxial layer 12, and an N ₊ region 20 is formed within the P-type region 38. Regions 20, 38 and P-type region 38
An N ₊ type region 36 formed in N _- type epitaxial layer 12 adjacent to represents the emitter-base and collector of transistor Q3. A buried N ₊ type pocket 11 is provided below the P type regions 14, 16 and 38.

An insulating layer 22 of silicon dioxide, for example, is provided on the surface of the N _- type epitaxial layer 12 .
The insulating layer 22 over the regions 14, 18, 36, 38 and 20 is provided with openings for making electrical contacts to those regions, e.g. a conductive contact 26 of aluminum passes through the insulating layer 22 to the regions. 1
8, and a conductive contact 34, for example aluminum, is ohmically contacted to regions 36 and 38, shorting the base and collector regions of Q3 to form a diode. The conductive contact 26 is further connected by a conductor 42 to a terminal 30 of the positive operating power supply V ₊ . Also, a conductive layer 24 of, for example, aluminum passes through the opening in the insulating layer 22 and contacts the region 14, and a bond pad 28 is connected to the region 14 via the conductive layer 24, and the bond pad 28 is further connected to the integrated circuit. It is connected to an input or output terminal of a utilization circuit (not shown) provided somewhere. A P ₊ type insulating region 32 extends from the surface of epitaxial layer 12 to substrate 10 and simultaneously surrounds epitaxial layer 12 to isolate its protection circuitry from other circuitry on substrate 12. It should be noted that when insulating region 32 is formed, P ₊ type region 40 is also formed in region 14. This additional region 40 improves emitter injection efficiency and reduces the contact or conduction resistance of Q2.

FIG. 4 is a circuit diagram of the structure of FIG. 3 in which the resistive element is a nonlinear resistive element in the form of a diode. The protection circuit is NPN transistor Q1, PNP transistor Q2 and diode connected
It includes a nonlinear resistance element formed by an NPN transistor Q3. The emitter electrode 118, base electrode 116 and collector electrode 112 of transistor Q1 are located in regions 18 and 16, respectively, of FIG.
and 12, emitter electrode 114 base electrode 112 and collector electrode 116 of transistor Q2 correspond to regions 14, 12 and 16 in FIG. 3, respectively. diode connected Q
3 is connected between the base electrode of Q2 and the operating power supply 30. The base region 138 and collector region 136 of Q3 are shorted together by contact 34 (FIG. 3) to form a diode and the emitter region 1
20 (region 20 in FIG. 3) is connected to operating power source 30 by conductor 144 (conductor 44 in FIG. 3). To complete this device, the emitter 120 of Q3 and the emitter 118 of Q3 are connected by a conductor 126 (via the contact portion 26 and the conductor 42 in FIG. 3).
It is connected to a power source 30.

The resistance value of resistor R (FIG. 1) depends only on the resistivity of N-type epitaxial layer 12 and the size and shape of the N-type epitaxial layer disposed between P-type region 16 and N ₊ type region 20. It will be decided. For example, resistor R
The resistance value can be increased by separating the N ₊ type region 20 from the P type region 16. As in the case of the circuit shown in Figure 2, Q2 is triggered to cause regenerative operation,
Base current is required to latch the structure of transistors Q1 and Q2. In the circuit diagram of Figure 4, when Q3 (nonlinear resistance element) is forward biased, there is an additional voltage drop of approximately 0.6 volts that must be overcome before triggering occurs; The reverse bias breakdown voltage inherent in this diode is approximately 7 volts due to the deep diffusion region 40 in contact with the N ₊ type pocket 11.
Because it is added along with the reverse bias breakdown voltage of volts,
A total reverse bias breakdown voltage of about 15 volts, which is necessary to operate the power supply at about 12 volts, was obtained.

Similar to FIG. 2, transistors Q1 and Q of FIG.
2 and are connected to form a silicon controlled rectifier (SCR). That is, the base electrode of Q1 is connected to the collector electrode of Q2, and the base electrode of Q2 is connected to the collector electrode of Q1.
Diode-connected Q3 is connected in parallel with the conductive path between the collector and emitter of transistor Q1.

The protection circuit thus obtained is such that the resistive element (linear resistor R in Figure 2 or diode-connected transistor in Figure 4) conducts when the voltage across the terminals exceeds a predetermined threshold. It differs from a normal SCR device in that it is changed to a two-terminal device. Furthermore, unlike conventional SCRs, the present invention does not require a resistor between the base and emitter electrodes of transistors Q1 or Q2.

The protection circuit of both embodiments (FIGS. 2 and 4) is connected to terminal 30 via conductor 126 and receives a positive operating potential V ₊ . This protection circuit is also Q2
The emitter electrode is connected to a bonding pad 28 which is connected to the utilized circuit to be protected.

In operation, the signal at junction pad 28 typically fluctuates at a potential below V ₊ . The potential of the bonding pad 28 is
As long as V ₊ is below, the base-emitter junction of transistor Q2 is reverse biased and transistors Q1 and Q2 are non-conducting.

The high voltage transient that occurs at junction pad 28 causes its potential to be a positive voltage greater than V ₊ . When the potential difference between the junction pad and the power supply terminal 30 exceeds the combined forward bias base-emitter voltage (V _BE ) of transistors Q2 and Q3, transistor Q
2 begins to flow collector current. transistor Q
The current flowing through the collector electrode of transistor Q1 provides base current to the transistor Q1, making it conductive. This current passing through the collector electrode of transistor Q1 provides base current to transistor Q2, thereby driving transistor Q2 and transistor Q1 into a highly conductive state. When the current supplied from junction pad 28 to power supply terminal 30 falls below the minimum sustaining current due to high voltage fluctuations, transistor Q2 is cut off, cutting off the base current to transistor Q1, and the protection circuit becomes non-conducting. . In this manner, the energy of the high voltage fluctuations that produce a positive voltage at junction pad 28 is released to power supply terminal 30 by conduction of transistors Q1 and Q2, protecting the utilized circuitry from damage.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of an embodiment of a semiconductor structure implementing a protection circuit according to the present invention, FIG. 2 is a circuit diagram of an embodiment of the semiconductor protection circuit of FIG. 1, and FIG. FIG. 4 is a sectional view of another embodiment of the implemented semiconductor structure, and FIG. 4 is a circuit diagram of the embodiment of the semiconductor protection circuit of FIG. Q1, 12, 16, 18... first transistor, Q2, 12, 14, 16... second transistor, 112, 116... transistor connection means, 30... power supply terminal, 26, 126... power supply terminal Connection means, 28...Signal terminal, 24...Signal terminal connection means, R...Resistance element.

Claims (1)

[Claims] 1 first and second transistors of mutually opposite conductivity types formed in a substrate of a semiconductor material and each having emitter, base, and collector electrodes; and a base electrode of the first transistor connected to the second transistor. and means for connecting the base electrode of the second transistor to the collector electrode of the first transistor, and means for connecting the first and second transistors as an SCR-type device. ,
a power supply terminal connected to an operating potential source, a means for connecting the power supply terminal to the emitter electrode of the first transistor, a signal terminal connected to a circuit to be used, and a means for connecting the emitter electrode of the second transistor to the signal and a resistor connected between the base electrode of the second transistor and the power supply terminal.