JPS6242533A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the generation of cracks in a cover film and the generation of short circuits among wires and a chip, and to improve the reliability of a semiconductor device by forming an insulating film without coating the periphery of the semiconductor chip, to which an integrated circuit is shaped, with a bonding pad. CONSTITUTION:Polyimide is coated without coating bonding pads 15 for chips along scribing lines 17 for a wafer 11 before the wafer 11 for a semiconductor device is diced into separate chip, and polyimide films 16 are shaped as insulating films. Polyimide except predetermined sections is removed by using a mask for a pattern, and the polyimide films 16 are left around the chips 14 after dicing. When the LSI chips are scaled up and pins are increased, the generation of cracks in cover films and short circuits among wires 24 and among the wires 24 and the chips 14 are prevented, and the semiconductor device is handled easily, thus improving reliability.

Description

[Detailed description of the invention] [Summary] Polyimide coating around semiconductor chip (coating 1!J)
The stress on the chip surface is reduced by applying
Prevent wire short circuits.

C. Industrial Application Field] The present invention relates to a semiconductor device. More specifically, by coating the periphery of a semiconductor chip (hereinafter simply referred to as a chip) with polyimide, the occurrence of cranking of the cover film is reduced, and wire The present invention relates to a chip structure that prevents short circuits between each other and between wires and chip edges.

[Conventional technology]

In the manufacture of semiconductor devices, for example, silicon wafers (
A large number of identical integrated circuits (ICs) are formed in a matrix on a wafer (hereinafter simply referred to as a wafer), a cover film (protective film) of, for example, phosphorus silicate glass (PSG) is applied to the entire surface of the wafer, and then each wafer is Each IC is cut into chips (dicing), and the chips are sealed in, for example, a package to complete one semiconductor device. The cutting of the wafer described above is carried out by pasting the wafer 11 on a tape 12 (for example, a vinyl chloride sheet) as shown in the cross-sectional view of FIG. The chips are then split and then expanded into individual chips 14 as shown in FIG. Chip 14 is collet 2
1 to another location, such as on the package 22 partially shown in the cross-sectional view of FIG. and 23 by bonding (wire bonding).

[Problem that the invention seeks to solve]

The recent trend in semiconductors is to miniaturize patterns for the purpose of higher integration, while chips are becoming larger in order to incorporate as many ICs as possible into one chip, resulting in smaller knobs and sealing plastic. PS due to the difference in thermal expansion coefficient of
G-crank occurs.

Second, as chips become larger, the number of pins (outer leads of the pan cage) tends to increase.

This means that the number of wires connecting pads increases.For example, when a chip is encapsulated with resin, the wires are long and rounded. They can move relative to each other and cause shorts between the wires. In order to prevent this, if the wires are connected (strung) low as shown in FIG. 8, there is a problem that the wires and the edges of the chip come into contact and short circuit occurs.

Furthermore, conventionally, wafers were cut by half-canting as shown in FIGS. 5 and 6, but in this case, stress was concentrated in the notch 14a created when the chip was broken. There was a problem that the cutout portion 14a peeled off. In order to avoid this, recently, as shown in FIG. 7, the cuts have been made to completely cut the wafer (full cut) and also cut into the tape 12. In this case, the tape cannot be spread out, so the conventional collet 21 cannot be used to move the chip 14, so a technique that uses a type of collet 21a that contacts the surface of the chip 14 and brings the chip into close contact with the collet by vacuum suction has been developed. It has been adopted. In that case, when the collet 21a comes down and comes into contact with the chip 14, there is a problem that the surface of the chip 14 is damaged by the collet.

The present invention was created in view of the above points. An object of the present invention is to provide a chip in which damage to the chip during handling due to short circuiting and full-cut dicing can be prevented.

[Means for solving problems]

1 and 2 are a plan view and a perspective view of an embodiment of the present invention, and 3.
FIG. 4 is a sectional view showing an example of application of the present invention.

In FIG. 1, an insulating film, such as a polyimide film 16, is formed around a chip 14 so as not to cover bonding pads 15 provided on the chip.

[Effect]

Since the polyimide film is formed around the chip 14, the force applied in the lateral direction of the chip is partially absorbed by the polyimide film, so the force applied to the cover film is alleviated, and the collet is The chip surface is protected because it contacts only the polyimide film, and even if the wire is stretched low, the wire only contacts the polyimide film, even if the wire is stretched low to prevent short circuits between wires. This prevents short circuits with the edges of the chip.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

Referring to FIG. 1, in the present invention, prior to dicing the wafer into individual chips, the bonding pads 15 of the chips are cut along the scribe lines 17 of the wafer 11.
An insulating film, ie, a polyimide film 16, is formed by coating an insulating material such as polyimide without covering the substrate. To do this, the entire surface of the wafer may be coated with polyimide, and then the polyimide other than the portions shown in the figure may be removed using a mask with the pattern shown in FIG. It is important that a polyimide film 16 exists around the periphery as shown in FIG.

When a polyimide film is provided around the chip, when a collet is used to move the chip 14 after dicing, a vacuum suction type collet 21a shown in FIG.
4, the surface of the collet is covered with polyimide film 1.
Since the tip contacts only the tip 6 and does not come into contact with the surface of the tip 14, damage to the tip is prevented. Furthermore, even if the collet 21a contacts the polyimide film 16 with a strong force, the polyimide film acts as a cushion and relieves the stress, thereby preventing damage to the chip 14.

Bonding pad 15 of the chip as shown in FIG.
When connecting the pad 23 of the pancage with the wire 24, the wire 24 contacts the polyimide film 16 before contacting the edge of the chip, and since the polyimide film is made of an insulating material, there is no short circuit. There is no risk of short circuit between the wire 24 and the chip 14. This allows the wires to be stretched low and prevents short circuits between the wires 24, making it suitable for the recent increase in the number of bins.

Furthermore, referring to FIGS. 3 and 4, even if a lateral force F is applied to the chip 14, it is resisted by the polyimide film 16, so that the force applied to the chip itself is alleviated.

(Effects of the Invention) As described above, according to the present invention, even if the LSI chip becomes larger and has more pins, it is possible to avoid the occurrence of cracks in the cover film, which were previously experienced, and short circuits between wires or between wires and chips. , damage to the chip during chip handling with a collet under full-cut conditions is prevented or alleviated, which is highly effective in improving the reliability of semiconductor devices.

[Brief explanation of drawings]

Fig. 1 is a plan view of an embodiment of the present invention, Fig. 2 is a perspective view of an embodiment of the invention, Fig. 3 is a sectional view of an applied example of the present invention, Fig. 4 is a sectional view of an applied example of the present invention, and Fig. 5 is a sectional view of an applied example of the present invention. 6 is a sectional view of a conventional example, FIG. 7 is a sectional view showing a full cut of wafer dicing, and FIG. 8 is a sectional view of a conventional example. 1 to 7, 11 is a wafer, 12 is a tape, 13 is a groove, 13a is a crack line, 14 is a chip, 15 is a bonding pad, 16 is a polyimide film, 17 is a scribe line, and 21 is a scribe line. 21a is a vacuum suction type collet, 22 is a package, 23 is a pad of the package, and 24 is a wire. Ntobo Nmi Akatsubi 'Ntoba Chiiyoko'l Jhio Il
l:nΔ Fig. 1 The present invention's atonement envoy Izeng Fig. 12 El Fig. 3

Claims (1)

[Claims] In a semiconductor chip (12) on which an integrated circuit is formed to be cut from a wafer (11), an insulating film ( 16) A semiconductor device comprising: