JPS6243337B2 - - Google Patents
Info
- Publication number
- JPS6243337B2 JPS6243337B2 JP54131876A JP13187679A JPS6243337B2 JP S6243337 B2 JPS6243337 B2 JP S6243337B2 JP 54131876 A JP54131876 A JP 54131876A JP 13187679 A JP13187679 A JP 13187679A JP S6243337 B2 JPS6243337 B2 JP S6243337B2
- Authority
- JP
- Japan
- Prior art keywords
- brazing material
- plate
- bonded
- conductive plate
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/20—Conductive package substrates serving as an interconnection, e.g. metal plates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07511—Treating the bonding area before connecting, e.g. by applying flux or cleaning
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5434—Dispositions of bond wires the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/934—Cross-sectional shape, i.e. in side view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は、電子部品より具体的には半導体装置
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates more specifically to semiconductor devices than electronic components.
半導体装置において、ステム（又はフランジ）
基板上に取付けられる中間絶縁ポストは、一般に
第１図に示すように平らな絶縁板１とその上に
Ag（銀）ロウ２を介して接続される表面が平ら
なCu（銅）等の導電板３からなり、その上面が
Al（アルミニウム）線（ワイヤ）４を超音波ワ
イヤボンデイングする領域になつている。この導
電板のAg（銀）ロウ付時にロウ材の量の変動等
により同図のように導電板表面にロウ材が流れ出
してAl（アルミニウム）線の超音波ワイヤボン
デイングが不可能になつたり、いつたんボンデイ
ングされたAl線が剥れたりして、半導体製品の
不良品の発生の原因となつている。これが対策と
して、ステム上で絶縁ポストを外観検査し、導電
板上にロウ材のもり上りがあつたものは不良品と
みなし、又、超音波ボンデイングはポスト上の平
坦面部を選んで行なうようにしているが作業能率
上問題があつた。 In semiconductor devices, stem (or flange)
The intermediate insulating post installed on the board generally consists of a flat insulating plate 1 and a
It consists of a conductive plate 3 made of Cu (copper) etc. with a flat surface connected via Ag (silver) wax 2, and its upper surface
This is an area where an Al (aluminum) wire 4 is subjected to ultrasonic wire bonding. When the conductive plate is brazed with Ag (silver), due to fluctuations in the amount of brazing metal, the brazing metal flows out onto the surface of the conductive plate as shown in the figure, making ultrasonic wire bonding of Al (aluminum) wires impossible. Bonded Al wires can easily peel off, causing defective semiconductor products. As a countermeasure, the insulating post should be visually inspected on the stem, and if there is brazing material rising onto the conductive plate, it should be considered a defective product, and ultrasonic bonding should be performed by selecting a flat surface on the post. However, there were problems with work efficiency.
本発明の目的は支持板に対してロウ材を介して
導電板が取り付けられた新規な電子部品を提供す
ることにある。 An object of the present invention is to provide a novel electronic component in which a conductive plate is attached to a support plate via a brazing material.
上記目的を達成するための本発明の基本構成
は、支持板に対して導電板がロウ材を介して取り
付けられてなる電子部品であつて、その導電板の
ロウ材が接着されている面の周縁部は鈍角又はア
ール状に形成されていることを特徴とするもので
ある。 The basic structure of the present invention for achieving the above object is an electronic component in which a conductive plate is attached to a support plate via a brazing material, and the surface of the conductive plate to which the brazing material is bonded is The peripheral edge portion is characterized by being formed into an obtuse angle or a rounded shape.
第２図は本発明による基本的構造を示すもので
５は金属ステム（フランジ）基板、１は絶縁板、
例えばセラミツク板の上下面にMo（モリブデ
ン）等のメタライズ膜を施し、下面とステムとの
間にAgロウ６、半田を介在させてステムの上に
取付けてある。３はCu等の導電板で下面と絶縁
板１との間をAgロウ２を介在させて取付けてあ
り、上面はAlワイヤをボンデイングするための
平坦面を形成し、絶縁板との接面となる下面の縁
部７を鈍角に又はアール状に形成してある。 Fig. 2 shows the basic structure according to the present invention, in which 5 is a metal stem (flange) substrate, 1 is an insulating plate,
For example, a metallized film of Mo (molybdenum) or the like is applied to the top and bottom surfaces of a ceramic plate, and the plate is attached to the top of the stem with Ag wax 6 and solder interposed between the bottom surface and the stem. 3 is a conductive plate made of Cu, etc., which is attached with an Ag wax 2 interposed between the lower surface and the insulating plate 1, and the upper surface forms a flat surface for bonding the Al wire, and the contact surface with the insulating plate. The edge 7 of the lower surface is formed into an obtuse angle or a rounded shape.
このような本発明の構造によれば下記理由で前
記発明の目的が達成できる。 According to such a structure of the present invention, the above object of the invention can be achieved for the following reasons.
一般にある温度での溶融状のロウ材が導電体面
に付着する場合ロウ材の導体面となす角はロウ材
の導体面への附着力（ぬれ性）とロウ材自体の表
面張力とのバランスにより決まる。従来構造の場
合、第３図に示すようにロウ材の導体面となす角
θが一定であれば、破線で示す位置でのθ′＝θ
であるためロウ材は上方へ移動し易く、このため
導電体上面までロウ材でぬれるようになる。これ
に対して、第４図に示すように導電体の下面の周
縁が鈍角（直角−α）ないしアール状に形成して
ある場合、最初ロウ材のなす角がθでバランスし
ていても、導体の側面ではθ−αとなり、バラン
スがくずれ、それ以上ロウ材が上へ進行しない。
このことから、導電体下面の周縁の角をとつたり
アールを形成することで導電体上面へのロウ材の
もり上りがなく、ロウ材の全くない平坦面でワイ
ヤボンデイングができるようになつた。実験によ
れば導電体下面の加工をしない従来の場合、ロウ
材のもり上りが50％にも及んだが、本発明によ
り、例えば0.2〜0.4mm厚のCu板で0.1mmのアール
又は角を落としAgロウを使用した場合、ロウの
もり上りを全くなくすことができた。 Generally, when molten brazing material adheres to a conductor surface at a certain temperature, the angle that the brazing material forms with the conductor surface depends on the balance between the adhesion force (wettability) of the brazing material to the conductor surface and the surface tension of the brazing material itself. It's decided. In the case of the conventional structure, if the angle θ between the brazing material and the conductor surface is constant as shown in Figure 3, θ' = θ at the position shown by the broken line.
Therefore, the brazing material can easily move upward, and the top surface of the conductor can be wetted with the brazing material. On the other hand, if the periphery of the lower surface of the conductor is formed at an obtuse angle (right angle -α) or a rounded shape as shown in FIG. 4, even if the angle formed by the brazing material is initially balanced at θ, At the side of the conductor, the angle becomes θ-α, the balance is lost, and the brazing metal no longer moves upward.
From this, by rounding or forming a radius around the periphery of the lower surface of the conductor, the solder metal does not rise to the upper surface of the conductor, and wire bonding can now be performed on a flat surface with no solder metal at all. . According to experiments, in the conventional case where the bottom surface of the conductor is not processed, the brazing material rises up to 50%, but with the present invention, for example, a 0.1 mm radius or corner can be formed on a 0.2 to 0.4 mm thick Cu plate. When using dropped Ag wax, it was possible to completely eliminate wax build-up.
第５図は本発明をエミツタベース上方取出し電
極タイプのトランジスタに適用した例を示す。同
図において５はフランジ、１は絶縁板、８は導電
板たるリード、９はSi半導体ペレツトでペレツト
のベースエミツタ電極と両リードとの間をワイヤ
４でボンデイングしてある。上記リード８はその
下面接面を第５Ａ図に示すように角を落として
Agロウ２によりセラミツク絶縁板１に接続して
あり、ロウ材がボンデイング領域に流れないよう
になつている。 FIG. 5 shows an example in which the present invention is applied to an emitter base upward lead electrode type transistor. In the figure, 5 is a flange, 1 is an insulating plate, 8 is a lead which is a conductive plate, 9 is a Si semiconductor pellet, and a wire 4 is used to bond between the base emitter electrode of the pellet and both leads. The lead 8 has its bottom surface rounded off as shown in Figure 5A.
It is connected to the ceramic insulating plate 1 by Ag solder 2 to prevent the solder material from flowing into the bonding area.
第６図は本発明をエミツタ接地形トランジスタ
に適用した例を示す。同図において、５はフラン
ジ、１は絶縁板、１０は導電板たるMo板でその
上にSiペレツト９とAlクラツド板１１が設けら
れ、Siペレツトのエミツタ電極はワイヤ４Ｅを介
してステムに接地され、ベース電極はワイヤ４Ｂ
を介してステム上の一方の外部リード１２に接続
され、コレクタと導通するAlクラツド板１１に
Alワイヤがボンデイングされて他方の外部リー
ドに接続される。第６Ａ図に示すようにMo板の
下面周縁の角部が落されAgロウ材を介して絶縁
板１に接続され、ロウ材はボンデイング領域に流
れることを防止してある。 FIG. 6 shows an example in which the present invention is applied to a grounded emitter transistor. In the figure, 5 is a flange, 1 is an insulating plate, 10 is a Mo plate which is a conductive plate, and a Si pellet 9 and an Al clad plate 11 are provided thereon, and the emitter electrode of the Si pellet is grounded to the stem via a wire 4E. and the base electrode is wire 4B
is connected to one external lead 12 on the stem through the Al clad plate 11 which is electrically connected to the collector.
An Al wire is bonded and connected to the other external lead. As shown in FIG. 6A, the corners of the lower periphery of the Mo plate are dropped and connected to the insulating plate 1 via Ag brazing material to prevent the brazing material from flowing into the bonding area.
以上実施例で述べた本発明によれば導電板の下
面周縁の角部を落とし又はアールをつけることに
よつて導電板上面へのロウ材の流れを防止するこ
とにより部品検査を簡略化し作業性が向上すると
ともに、製品の信頼性を高めた。 According to the present invention described in the above embodiments, the corners of the lower surface of the conductive plate are rounded or rounded to prevent the brazing material from flowing to the upper surface of the conductive plate, thereby simplifying component inspection and improving workability. As well as improving product reliability.
本発明は前記実施例に限定されず、これ以外の
実施形態もあり得る。 The present invention is not limited to the above embodiments, and other embodiments are possible.
第１図は従来の絶縁ポストの例を示す断面図、
第２図は本発明の基本的構造を示す断面図、第３
図及び第４図は導電板へのロウ材の付着形態を示
す原理図で第３図は従来の場合、第４図は本発明
の場合をそれぞれ示す。第５図及び第６図は本発
明の実施例を示す平面図、第５Ａ図、第６Ａ図は
第５図、第６図の各Ａ―Ａ視断面図である。
１…絶縁板、２…ロウ材、３…導電板、４…ワ
イヤ、５…ステム、６…ロウ材、７…導電板下面
周縁部、８…リード、９…Siペレツト、１０…
Mo板、１１…Alクラツド板、１２…リード。
Figure 1 is a sectional view showing an example of a conventional insulating post.
Fig. 2 is a sectional view showing the basic structure of the present invention;
3 and 4 are principle diagrams showing the form of adhesion of the brazing material to the conductive plate. FIG. 3 shows the conventional case, and FIG. 4 shows the case of the present invention. 5 and 6 are plan views showing an embodiment of the present invention, and FIGS. 5A and 6A are sectional views taken along the line AA in FIGS. 5 and 6. DESCRIPTION OF SYMBOLS 1... Insulating plate, 2... Brazing material, 3... Conductive plate, 4... Wire, 5... Stem, 6... Brazing material, 7... Bottom periphery of electrically conductive plate, 8... Lead, 9... Si pellet, 10...
Mo plate, 11... Al clad plate, 12... Lead.
Claims (1)
がロウ材を介して取付けられてなる電子部品であ
つて、その導電性リードのロウ材が接着されてい
る面の周縁部は外側に突出するアール状の面取り
され、そのアール状の面取り部分にロウ材が接着
され、その導電性リードのロウ材接着面とは反対
側の面に対してはワイヤがボンデイングされてな
ることを特徴とする電子部品。1 An electronic component in which a plate-shaped conductive lead is attached to one main surface of a support plate via a brazing material, and the peripheral edge of the surface of the conductive lead to which the brazing material is bonded is on the outside. The conductive lead is chamfered in a protruding radius, brazing metal is bonded to the chamfered radius, and a wire is bonded to the surface of the conductive lead opposite to the surface to which the brazing metal is bonded. and electronic components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13187679A JPS5656661A (en) | 1979-10-15 | 1979-10-15 | Insulation post in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13187679A JPS5656661A (en) | 1979-10-15 | 1979-10-15 | Insulation post in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5656661A JPS5656661A (en) | 1981-05-18 |
| JPS6243337B2 true JPS6243337B2 (en) | 1987-09-12 |
Family
ID=15068199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13187679A Granted JPS5656661A (en) | 1979-10-15 | 1979-10-15 | Insulation post in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5656661A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5077102B2 (en) * | 2008-06-30 | 2012-11-21 | 三菱マテリアル株式会社 | Power module substrate and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54111467U (en) * | 1978-01-25 | 1979-08-06 |
-
1979
- 1979-10-15 JP JP13187679A patent/JPS5656661A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5656661A (en) | 1981-05-18 |
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