JPS6243546B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to electronic devices, particularly to reference voltage generators and their applications, as well as insulated gate field effect transistors.

In various semiconductor electronic circuits, in order to generate a reference voltage, it is essential to use a physical quantity having the dimension of voltage. Until now, the physical quantities have mainly been the forward voltage drop V _F of a PN junction diode, the reverse breakdown voltage (Zena voltage) V _z , and the insulated gate field effect transistor (often represented by IGFET and MOSFET). Threshold voltage V _th etc. are used.

These physical quantities do not indicate absolute voltage values, and the voltage values are subject to fluctuations depending on various factors. Therefore, in order to utilize these physical quantities as a reference voltage generating device for various electronic circuits, it is necessary to pay attention to the fluctuation factors of the obtained voltage value and the permissible fluctuation range.

First, regarding the temperature characteristics of these physical quantities, V _F and V _th mentioned above usually have a temperature dependence of about 2 to 3 mV/°C, and the temperature change in the reference voltage that accompanies this temperature change varies depending on the application. In some cases, the size is such that we have no choice but to give up on practical use.

Next, regarding manufacturing variations in these physical quantities, the threshold voltage V _th of the MOSFET has a variation of about ±0.2V, and this variation is larger than the temperature change.

In addition, the Zener voltage V _z has a low voltage limit of about 3V, which is inappropriate as a reference voltage for use in the low voltage range of about 1 to 3V. In order to use it as a voltage, it is necessary to flow a current of several mA to several tens of mA, which is also inappropriate in terms of reducing power consumption.

As is clear from the above explanation, conventional reference voltage generators using V _th , V _F , and V _z are not necessarily suitable for all uses, considering temperature characteristics, manufacturing variations, power consumption, voltage levels, etc. However, in many cases, practical application and mass production had to be abandoned for applications that required extremely strict characteristics.

From the above studies, the present inventors learned that there are physical limits to the improvement of conventional reference voltage generators, and decided to research and develop a reference voltage generator with new ideas and ideas. .

An object of the present invention is to provide a reference voltage generation circuit based on a completely new concept not seen in the past, and to facilitate the design and mass production of electronic circuits.

Another object of the present invention is to provide a reference voltage generator with small temperature changes.

Another object of the present invention is to provide a reference voltage generator in which fluctuations in voltage values obtained are small relative to fluctuations in manufacturing conditions, for example, manufacturing variations (deviations) between lots are small.

Another object of the present invention is to provide an integrated circuit reference voltage generating device that can reduce manufacturing variations to such an extent that post-manufacturing adjustments are not required.

Another object of the present invention is to provide an integrated electronic circuit device including a reference voltage generating device that can be manufactured with a large margin of tolerance to target specifications.

Another object of the present invention is to provide an integrated electronic circuit device including a reference voltage generator with high manufacturing yield.

Another object of the present invention is to provide a reference voltage generator suitable for IGFET integrated circuits.

Still another object of the present invention is to provide a reference voltage generator and a voltage comparator that consume less power.

Another object of the present invention is to provide a reference voltage generator capable of obtaining a low voltage (1.1 V or less) with excellent accuracy.

Another object of the invention is a relatively low voltage (approximately 1 to
3V) power source, such as a 1.5V silver oxide battery or a 1.3V mercury battery.

Another object of the present invention is to provide a reference voltage generator suitable for semiconductor integrated circuits.

Another object of the present invention is to form a P-type Si gate.
A reference voltage generation device that prevents acceptor impurities such as B, Al, and Ga from being doped into the channel portion through the gate oxide film and changing the threshold voltage of an IGFET that uses this as a gate electrode. An object of the present invention is to provide a method for manufacturing a device.

FIG. 1d shows the structure of IGFETAs B, C, and D having threshold voltage differences based on the Fermi level difference of the gate electrodes constituting the reference voltage generating device of the present invention. A is a P-channel MOSFET with P-type Si11 as the gate electrode, and B is a P-channel MOSFET with P-type Si11 at both ends of the gate.
It is a P-channel MOSFET with a gate electrode made of Si11 and an N-type Si8 in the center. C is N type
It is an N-channel MOSFET with Si8 as the gate electrode, and D is N-type Si8 at both ends of the gate and P in the center.
A reference voltage generator is constructed using a voltage based on the difference in threshold voltage between A and B, or C and D, which are N-channel MOSFETs having Si11 type gate electrodes.

Figure 1 a to d are the above IGFETA, B, C, D.
This figure shows a method of manufacturing a MOS integrated circuit including.

(a) After forming a low concentration P-type layer 2 on an N-type Si substrate 1 and forming a thick oxide film 3 for device isolation, a gate oxide film 4 is formed in the opening of the oxide film 3, and an intrinsic semiconductor is formed. After depositing a certain polysilicon film 5,
Processed using photoetching technology.

(b) By partially forming a vapor phase grown oxide film 6 and selectively diffusing N-type impurities such as phosphorus using this as a mask, the N-type region 7 and N-type polysilicon that will become the source and drain of the N-channel MOSFET are formed. Form layer 8.

(c) A P-channel MOSFET is formed by partially forming a vapor-grown oxide film 9 and using this as a mask to ion-implant P-type impurities such as boron.
The P-type region 10 and P
A mold polysilicon layer 11 is formed. In the case of boron, the oxide film 9 is approximately 3000 Å thick, the acceleration energy is 30 to 50 KeV, and the implantation amount is 2×10 ¹⁵ to 1×
10 ¹⁶ /cm ² is appropriate. The implanted ions can be activated by heat treatment at 900°C for 10 minutes to 1000°C for 30 minutes.

Here, the N-type impurity diffusion in the process shown in (b) is shown in (c).
It may be performed after the step shown in (b), and in this case, it is better to implant the N-type impurity shown in (b) by implanting ions such as phosphorus. Here, in the case of phosphorus,
The oxide film 6 is about 3000 Å and the acceleration energy is 60~
100 KeV and an implantation amount of 2×10 ¹⁵ to 1×10 ¹⁶ /cm ² are appropriate. Heat treatment at 900°C for 10 minutes to 1000°C for 30 minutes is appropriate for activation of the implanted ions. In this way, by doping the P-type impurity by ion implantation, and therefore reducing the heat treatment required after the P-type impurity is doped, it is possible to prevent the P-type impurity from being doped into the channel portion. can.

(d) After depositing the vapor-grown phosphorus glass film 12, a contact hole is formed and an Al electrode 13 is formed to complete the process.

Next, a circuit for extracting the difference in V _th of the MOS transistors will be explained.

FIG. 2 shows a circuit that generates a voltage corresponding to the threshold voltage of a MOS transistor. T ₁ , T ₂
constitutes a so-called MOS diode whose drain and gate are commonly connected.

I ₀ is a constant current source, T ₁ and T ₂ are mutual conductances β that are approximately equal to different threshold voltages V _th1 and V _th2
MOSFET with each drain voltage
If V ₁ and V ₂ , then I ₀ = 1/2β (V ₁ −V _th1 ) ² = 1/2β (V ₂ −V _th2 ) ² ...(1) Therefore, V ₁ = V _th1 +√2 ₀ ...(2) V ₂ =V _th2 +√2 ₀ ...(3) If the difference in drain voltage is taken, the difference in threshold voltage can be extracted.

As a constant current source, a sufficiently large resistor may be used, and as long as it has the same characteristics, a diffused resistor,
Polycrystalline Si resistors, resistors made by ion implantation, and resistors made from MOS transistors can be used.

If the N ⁺ gate MOS and P ⁺ gate MOS described earlier are used as T ₁ and T ₂ in this circuit, the fermi quasi of the N-type semiconductor and the P-type semiconductor can be The difference in position (E _fo −E _fp ) can be extracted.

FIGS. 3 and 4 are examples of circuits in which FETs having different threshold voltages are connected in series in an AOS diode format to extract the difference in threshold voltage.
T ₁ is the threshold voltage V _th1 , T ₂ is the threshold voltage V _th2
Suppose you have

Under the condition that the resistance P ₁ is sufficiently large compared to the impedance of T ₁ and the resistance R ₂ is sufficiently large compared to the impedance of T ₂ , V ₁ −V ₂ ≒V _th1 …(4) V ₁ ≒V _th2 …( 5) Therefore, V ₂ ≒V _th1 −V _th2 (6).

In FIG. 5a, a voltage corresponding to the threshold voltage is applied to both terminals of the capacitor, and the voltage held in the capacitor is extracted as a differential voltage. FIG. 5b shows the operation timing. Clock pulse φ ₁ turns on T ₅ and T ₆ and sets the capacitance to C _1.
The difference voltage between the threshold voltages V _th1 and V _th2 of T ₁ and T ₂ is charged.

After _φ1 is cut off, clock _φ2 turns on _T3 and connects the node of _C1 . At this time, since the difference voltage between the threshold voltages is held in _C1 , that voltage is output to the node as is. When used in a voltage detection circuit as described later, the voltage at the node at this time can be used as it is as a reference voltage. However, in order to be able to use it in a more general form, the transmission gates T ₆ and T 7 are turned on by the clock φ ₃ during the time when the clock φ ₂ is on, and the transmission gates T 6 and T ₇ are easily turned on to C ₂ . If the potential is taken in and received by a so-called voltage follower that fully returns the output to the negative phase input (-) of the operational amplifier 5, the output will meet the thresholds of T ₁ and T ₂ with a sufficiently low internal impedance. The difference between the value voltages is obtained as a reference voltage.

FIG. 6 shows a reference voltage generating device that similarly utilizes capacitance _C2 . _T8 is turned on by clock _φ1 . At this time, _T9 is off due to clock _φ2 . The potential of the node is less than the potential of the node
The threshold voltage of T ₁ is lowered by V _th1 , and the potential of the node is lower than the potential of the node by the threshold voltage of T ₂ V _th
2 , and the difference voltage between the two is charged across the capacitor C. Next, turn off _T8 with _φ1 ,
When _T9 is turned on by _φ2 , a voltage difference between the threshold voltages is obtained at the node.

FIG. 7 shows an operational amplifier used in the circuit of FIG. T ₁ and T ₂ are a differential pair constituting a differential amplifier circuit, and T ₅ and T ₆ are active loads thereof. _T7 constitutes a constant current circuit together with the bias circuit formed by _T3 and _T4 . T ₈ and T ₇ are
This is a level conversion/output buffer circuit that uses _T7 as a constant current source load. The figure shows an example of a C-MOS circuit configuration, but single channel MOS
But it goes without saying that it can be configured.

[Brief explanation of the drawing]

Figures 1a to d have gate electrodes with different Fermi levels constituting the reference voltage generator of the present invention.
Cross-sectional diagrams showing the IGFET manufacturing method, Figures 2 and 3
4, 5a, 6 and 7 are reference voltage generation circuit diagrams according to the present invention, and FIG. 5b is a signal waveform time chart in the circuit of FIG. 5a. 1... N-type silicon base film, 2... P-type layer, 3...
... Oxide film, 4 ... Gate oxide film, 5 ... Intrinsic semiconductor polysilicon layer, 6 ... Oxide film, 7 ... N-type region, 8 ... N-type polysilicon layer, 9 ... Oxide film,
10...P type region, 11...P type polysilicon layer, 12...phosphorus glass film, 13...Al electrode.

Claims (1)

[Claims] 1 P channel with P type Si as gate electrode
The first MOSFET is a MOSFET, and the second MOSFET is a P-channel MOSFET with a gate electrode in which both ends of the gate are P-type Si and the center is N-type Si.
MOSFET, a third MOSFET that is an N-channel MOSFET with N-type Si as a gate electrode, and a fourth MOSFET that is an N-channel MOSFET with a gate electrode that has N-type Si at both ends and P-type Si in the center.
MOSFETs are on the same semiconductor substrate, and the first
MOSFET and 2nd MOSFET or 3rd MOSFET
A reference voltage generating device characterized in that a voltage based on a difference in threshold voltage between a MOSFET and a fourth MOSFET is extracted as a reference voltage.