JPS6243550B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to an improved method of manufacturing a semiconductor memory device.

The present applicant previously proposed a new nonvolatile semiconductor memory device in the specification of Patent Application No. 9911 of 1972 (filing date: January 31, 1972). The proposed nonvolatile semiconductor memory device includes source/drain regions having a conductivity type opposite to that of the substrate, which are provided at intervals near the surface of the semiconductor substrate, and a first gate edge on the surface of the substrate between the two regions. a floating gate electrode made of a first conductive layer thereon, a second gate insulating film thereon, and a control gate electrode made of a second conductive layer further thereon; It is characterized in that the drain region, the free gate electrode, and the control gate electrode are all formed in self-alignment. In such devices, due to the introduction of self-alignment technology, the floating gate electrode and control gate electrode have almost the same planar shape along the source-drain direction, compared to previous devices that did not use self-alignment technology. This brings about the great advantage that the device size can be reduced without any loss of maximum effect in terms of characteristics. However, in the device of the above-mentioned application, there is no difference in device dimensions in directions other than the source-drain direction, especially in the direction perpendicular to the source-drain direction, and there is room for further improvement in this respect.

Therefore, the purpose of the present invention is to further increase the integration of the device not only in comparison with the prior art but also in comparison with the above-mentioned application which has been improved upon, and to improve various aspects such as manufacturing yield and reliability. An object of the present invention is to provide a manufacturing method for stably and easily realizing a semiconductor memory device having particularly favorable properties and advantages.

The method for manufacturing a semiconductor device of the present invention includes a step of forming a first insulating film, such as a first gate insulating film, on the main surface of a semiconductor substrate, and a step of forming a first conductive layer, such as a polycrystalline silicon film, thereon. A process of forming an oxidation-resistant insulating film on this, a process of partially removing this oxidation-resistant insulating film, and a process of forming a thick field oxide film by thermal oxidation using the remaining part as a mask. It is characterized by including.

Furthermore, the present invention removes the remaining oxidation-resistant mask film, and then deposits a second conductive layer on the covered first conductive layer.
a process of forming an insulating film, a process of forming a second conductive layer thereon, a process of partially removing this second conductive layer, and a process of forming an insulating film covered by the remaining second conductive layer. selectively removing portions of the first conductive layer that are not present.

Furthermore, the method for fabricating a semiconductor memory device of the present invention includes the step of partially removing the oxidation-resistant insulating film in the above description and then selectively removing the first conductive layer using this as a mask. It is characterized by containing.

Furthermore, the manufacturing method of the present invention includes the following steps in the above description:
The present invention is characterized in that it includes a step of adding an impurity near the surface of each of the first and second conductive layers whose shapes have been determined to have a conductivity type opposite to that of the substrate in a self-aligned manner.

Furthermore, the manufacturing method of the present invention includes the step of doping a highly concentrated impurity of the same type as the substrate near the surface of the substrate in a self-aligned manner with the first and second conductive layers whose shapes have been determined in the above description. There is.

According to such a method of manufacturing a semiconductor device of the present invention, the first conductive layer functioning as a so-called floating gate electrode of a memory transistor generally called a stacked gate type is replaced with the second conductive layer functioning as a control gate electrode. Not only can the shape be determined in a self-aligned manner with respect to the thick field oxide film, but also the shape can be determined in a self-aligned manner with respect to the thick field oxide film. As a memory device, the device size can be reduced to the maximum extent possible. This is especially important when applying this memory device to a PROM with a large storage capacity.
(Programmable Read Only Memory), etc.
In the implementation of (integrated circuit) memories, various advantages such as high integration, high manufacturing yields, high reliability, etc. are achieved due to the reduction in 1-bit cell and therefore chip area.

Next, in order to make the features of the present invention easier to understand, several embodiments will be described in detail with reference to the drawings.

(Example 1): FIG. 1 is a plan view of a semiconductor memory device manufactured by an example of the method for manufacturing a semiconductor device of the present invention, and FIGS. 2A to 2L are cross sections a-a' in FIG. FIGS. 3A to 3C are cross-sectional model views at various manufacturing steps taken along the bb section of FIG. 1; Also, Figure 4 A, B, C and D
2 is a plan view showing various manufacturing steps in FIG. 1. FIG. Identical parts of the apparatus in these figures are designated by the same numerals. First, a first gate SiO ₂ film 3 with a thickness of about 1000 Å is grown by a thermal oxidation method on the main surface 2 having a surface index (100) of a P-type Si semiconductor substrate 1 with a specific resistance of about 50 Ω-cm. , on top of this
A polycrystalline Si film 4 with a thickness of about 2000 Å is formed using a SiH ₄ +H ₂ based thermal decomposition method, and then a Si ₃ N ₄ film 5 with a thickness of about 1000 Å is formed on this film using a SiH ₄ +NH ₃ based vapor phase growth method. (Figure 2A). Next, standard photo engraving (PR),
Parts of the films 3, 4, and 5 were selectively removed using the technique (FIG. 2B, FIG. 3A, and FIG. 4A). Then about
A thick field SiO ₂ film 6 of approximately 1 μm was selectively grown using the oxidation-resistant Si ₃ N ₄ film 5 as a mask by thermal oxidation in a steam atmosphere at 1000°C (Fig. 2C, 3). Figure B). Next, after removing the remaining film 5, the polycrystalline Si film 4 is thermally oxidized in an H ₂ - O ₂ atmosphere at approximately 900°C to a thickness of approximately
A second gate SiO ₂ film 7 of 1000 Å is grown on the film 4 (FIG. 2D, FIG. 3C). Next, SiH ₄ +N ₂
A polycrystalline Si film 8 with a thickness of about 5000 Å was grown by thermal decomposition of the system (Fig. 2E, Fig. 3D). Using standard PR technology, the polycrystalline Si film 8 was patterned to form the control gate electrode 8 (FIGS. 2F and 3).
Figure E, Figure 4B). Next, the shape of the polycrystalline Si
SiO ₂ film 7 in the part not covered by film 8, polycrystalline Si
The film 4 and the SiO ₂ film 3 are sequentially selectively removed to determine the shape of the floating gate electrode 4, and the substrate surface 2 is removed.
(Fig. 2G) and exposed to POCl ₃ at about 900℃.
Using phosphorus as a source, phosphorus was added to the substrate from the exposed substrate surface to form self-aligned N ⁺ type source regions 9 and drain regions 10 in both polycrystalline Si films 4 and 8 (FIG. 2H). Next, by heat treatment in a H ₂ - O ₂ atmosphere at approximately 900°C, the N ⁺ regions 9 and 10 are indented, and the thermal oxide film 11 covering the substrate surface 2 and the exposed surfaces of the control gate electrode 8 and floating gate electrode 4 is formed. (FIG. 2I, FIG. 3F), and apertures are formed in the oxide film 11 by standard PR techniques to form a source contact hole 12, a drain contact hole 13, and a control gate contact hole 14 (a second Figure J, Figure 3 G, Figure 4 C). Furthermore, an Al coating 15 with a thickness of about 1 μm is formed on the entire surface by vacuum evaporation (Fig. 2 K).
Figure 3H). Finally, the Al deposited film 15 is patterned using standard PR technology to form the source extraction electrode 16, drain extraction electrode 17, and control gate extraction electrode 18 to complete the device (Fig. 2L, Fig. 3). I, Figure 4 D). In this memory device, for example, by adding an appropriate amount of boron to the channel region in advance by ion implantation,
The initial threshold voltage seen from the control gate lead-out electrode 18 at the manufacturing stage was set to about 2V. With this device, for example, when 25V is applied to the control gate extraction electrode 18 and 15V is applied to the drain extraction electrode 17 with the source extraction electrode 16 grounded, electrons accelerated by the electric field in the channel and become hot form a so-called channel. In the injection mode, the floating gate electrode 4 is injected and the threshold voltage is shifted to about 10V, thus writing is performed. In this memory device, erasure is
Either optical or electrical methods are possible. Optical erasing is achieved by exciting the injected electrons in the floating gate electrode by irradiating the memory device with ultraviolet rays with a wavelength of λ = 2536 A, for example.
This is done by releasing it to the substrate and returning the threshold voltage to its initial value. Electrical erasing is accomplished by applying a positive voltage to the control gate extraction electrode 18, for example, and injecting electrons into the floating gate electrode 4 into the second gate.
By drawing out the electric field in the SiO ₂ film 7 to the control gate electrode 8 by Fowler-Nordheim tunneling, or by drawing it out to the control gate electrode 2
0 to ground or negative potential, source extraction electrode 16
A high positive voltage is applied to the source region 9 and the substrate 1.
The N--P junction between the two electrodes is broken down, and only holes among the hot electron-hole pairs generated at this time are selectively injected into the floating gate electrode 4 depending on the direction of the electric field existing in the first gate SiO ₂ film 3. ,
This is done by returning the threshold voltage to its initial value by canceling out the negative charge of the electrons that have already been injected. According to the manufacturing method of the semiconductor memory device of this example, the floating gate electrode 4 is self-aligned with the control gate electrode 8 along the channel direction, and with the thick field SiO ₂ film portion along the direction perpendicular thereto. The shape is determined by
Its dimensions are kept to the minimum required, so that the floating gate electrode is no longer a limiting factor in device size and maximum integration is achieved.

(Embodiment 2): FIG. 5 is a process sectional model diagram showing another embodiment of the present invention, and corresponds to the steps G to H in FIG. 2. In this figure, a floating gate electrode 4 and a control gate electrode 8 are shaped in a mutually self-aligned manner.
P-type regions 19 and 20 are formed in both regions by boron ion implantation in a self-aligned manner, and source and drain N ⁺ regions 9 and 10 are also formed in the regions 19 and 10, respectively.
20 in a self-aligned manner. The memory device of this example is dimensionally the same as that of Example 1, but by using a high resistivity, for example π type, for the base 1, the effective channel length between the source and drain is almost P type. It is determined only by the positional directions of the regions 19, 20 and the source and drain regions 9, 10, and therefore, it is relatively easy to realize a short channel device, and various improvements in characteristics can be achieved.

It should be noted that the several embodiments described above are merely for illustration, and it is clear from the above description that the present invention is not limited thereto. For example, it is possible to change the material, dimensions, and manufacturing method of each part of the device, and it is also possible to change the conductivity type and type of impurity.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a semiconductor memory device manufactured according to an embodiment of the present invention. Figures 2A to 2L are cross-sectional model views taken along the cutting line a-a' of Figure 1 and viewed in the direction of the arrow, showing one embodiment of the present invention in the order of manufacturing steps. It is something. 3A to 3I are cross-sectional model views of FIG. 1 taken along cutting line b-b' and viewed in the direction of the arrow; FIGS. 2B, C, D, E, and F, I,
The figures are shown corresponding to the manufacturing process of J, K and L. Figure 4A, Figure 4B, Figure 4C and Figure 4D correspond to the manufacturing process of Figure 2B, Figure 2F, Figure 2J and Figure 2L, respectively. FIG. FIG. 5 is a cross-sectional model diagram showing one step in another embodiment of the present invention. In the figure, 1...P-type Si semiconductor substrate, 6
... Main surface of 1, 3, 7... Gate SiO ₂ film, 4
...Floating gate electrode, 5...Si ₃ N ₄ film, 6... Field SiO ₂ film, 8... Control gate electrode, 9,
10... Source, drain N ⁺ region, 11...
SiO ₂ film, 12, 13, 14... Source, drain, control gate contact hole, 15... Al vapor deposited film, 17, 18, 19... Source, drain, control gate extraction Al electrode, 20, 21... P It is a type area.

Claims (1)

[Claims] 1. A step of forming a first silicon oxide film on the main surface of a semiconductor substrate, a step of forming a first polycrystalline silicon layer on the first silicon oxide film, and a step of forming a first polycrystalline silicon layer on the first silicon oxide film. A step of forming an oxidation-resistant insulating film on the polycrystalline silicon layer of forming a thick field oxide film by thermal oxidation using the remaining portion of the oxidation-resistant insulating film as a mask; and leaving the remaining portion of the oxidation-resistant insulating film as a mask. Then there is the second
a step of forming a silicon oxide film by thermal oxidation, a step of forming a second polycrystalline silicon layer on the second silicon oxide film and the field oxide film, and a step of forming the second polycrystalline silicon layer. forming a shape of a control gate electrode that partially remains and extends from above the field oxide film to above the first polycrystalline silicon layer; and using the control gate electrode as a mask, forming the second silicon oxide layer. a step of sequentially removing the film and the first polycrystalline silicon layer to form a floating gate electrode made of the first polycrystalline silicon layer; and a step of removing the semiconductor substrate using the control gate electrode and the field oxide film as a mask. forming source and drain regions in self-alignment with the control gate electrode and the floating gate electrode by introducing impurities into the control gate electrode and the channel region located on the field oxide film of the control gate electrode; A method of manufacturing a semiconductor device, comprising: connecting an aluminum control lead electrode to a portion near the floating gate electrode. 2. A method for manufacturing a semiconductor device according to claim 1, characterized in that a region having the same conductivity type as the semiconductor substrate and having a higher concentration than the semiconductor substrate is formed in a self-aligned manner with the control gate electrode and the floating gate electrode. .