JPS6244408B2 - - Google Patents
Info
- Publication number
- JPS6244408B2 JPS6244408B2 JP57174852A JP17485282A JPS6244408B2 JP S6244408 B2 JPS6244408 B2 JP S6244408B2 JP 57174852 A JP57174852 A JP 57174852A JP 17485282 A JP17485282 A JP 17485282A JP S6244408 B2 JPS6244408 B2 JP S6244408B2
- Authority
- JP
- Japan
- Prior art keywords
- push pin
- package
- heat dissipation
- heat
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C70/00—Shaping composites, i.e. plastics material comprising reinforcements, fillers or preformed parts, e.g. inserts
- B29C70/68—Shaping composites, i.e. plastics material comprising reinforcements, fillers or preformed parts, e.g. inserts by incorporating or moulding on preformed parts, e.g. inserts or layers, e.g. foam blocks
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C33/00—Moulds or cores; Details thereof or accessories therefor
- B29C33/12—Moulds or cores; Details thereof or accessories therefor with incorporated means for positioning inserts, e.g. labels
- B29C33/14—Moulds or cores; Details thereof or accessories therefor with incorporated means for positioning inserts, e.g. labels against the mould wall
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
- H10W74/016—Manufacture or treatment using moulds
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29L—INDEXING SCHEME ASSOCIATED WITH SUBCLASS B29C, RELATING TO PARTICULAR ARTICLES
- B29L2031/00—Other particular articles
- B29L2031/34—Electrical apparatus, e.g. sparking plugs or parts thereof
- B29L2031/3406—Components, e.g. resistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
【発明の詳細な説明】 この発明は半導体装置の製造方法に関する。[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor device.
半導体装置たとえば樹脂モールドしたパワート
ランジスタでは半導体チツプ(以下単にチツプと
言う。)をのせたリードフレームを樹脂モールド
によるパツケージの表面に露呈させ、チツプから
の熱をこの露呈したリードフレーム(これを放熱
部と呼ぶ。)から放散するようにしている。この
ような構成の半導体装置は従来では第1図に示す
ように製造していた。同図において1,2は対を
なすモールド用の金型(ここでは仮りに1を下金
型2を上金型と呼ぶことにする。)、3はチツプ、
4はチツプ3がダイボンデイングされてある放熱
部4Aと一体のリード、5はリード、6はチツプ
3とリード5とを接続する金線のようなワイヤで
ある。 For example, in a semiconductor device such as a resin-molded power transistor, a lead frame on which a semiconductor chip (hereinafter simply referred to as a chip) is placed is exposed on the surface of a resin-molded package, and heat from the chip is transferred to the exposed lead frame (which is used as a heat dissipation section). ). A semiconductor device having such a structure has conventionally been manufactured as shown in FIG. In the figure, 1 and 2 are a pair of molding dies (here, 1 is called the lower mold 2 and the upper mold is called the upper mold), 3 is a chip,
Reference numeral 4 designates a lead integrated with the heat dissipation portion 4A to which the chip 3 is die-bonded, 5 a lead, and 6 a wire such as a gold wire that connects the chip 3 and the lead 5.
トランジスタの製作に際しては、チツプ3を表
面にとりけた放熱部4Aを下金型1の底面1Aに
のせ、この下金型1に上金型2を重ねる。この重
ね合わせ部から各リード4,5を外部に導出す
る。そして両金型1,2間の空腔部にモールド用
の樹脂を注入する。ところでこのような製作過程
において、注入された樹脂が底面1Aと放熱部4
Aとの間の隙間に流れこむようなことがあると、
完成されたあと、放熱部4Aの周囲にバリが生ず
るようになり、放熱効果が損なわれるし、商品価
値が下がる。そのためこのように放熱部4Aの周
囲にバリができたときはそのバリをその都度剥離
するようにしているが、このような工程が加わる
ことはその作業性を著るしく損なう結果となる。 When manufacturing a transistor, a heat dissipating section 4A with a chip 3 disposed on its surface is placed on the bottom surface 1A of a lower mold 1, and an upper mold 2 is placed on the lower mold 1. Each lead 4, 5 is led out from this overlapping portion. Then, molding resin is injected into the cavity between the two molds 1 and 2. By the way, in such a manufacturing process, the injected resin covers the bottom surface 1A and the heat dissipation part 4.
If something flows into the gap between A and A,
After completion, burrs begin to form around the heat dissipation part 4A, impairing the heat dissipation effect and lowering the product value. Therefore, when burrs are formed around the heat dissipating section 4A, the burrs are peeled off each time, but the addition of such a step significantly impairs the workability.
このように放熱部4Aの周囲にバリが生ずるの
を防ぐために、放熱部4Aの表面を押圧して底面
1Aに押しつけて、放熱部4Aと底面1Aとの間
に隙間が生じないようにすればよい。そこで上金
型2を貫通する押しピン8を用意する。9は押し
ピン8を押付ける押付板、10はスペーサであ
る。このように押しピン8によつて放熱部4Aを
その表面から押えつければ、放熱部4Aと底面1
Aとの間の隙間の発生は阻止できるようになる。 In order to prevent burrs from forming around the heat dissipating section 4A, press the surface of the heat dissipating section 4A against the bottom surface 1A so that no gap is created between the heat dissipating section 4A and the bottom surface 1A. good. Therefore, a push pin 8 that penetrates the upper mold 2 is prepared. 9 is a pressing plate for pressing the push pin 8, and 10 is a spacer. By pressing the heat radiating part 4A from the surface with the push pin 8 in this way, the heat radiating part 4A and the bottom surface 1
This makes it possible to prevent a gap from forming between A and A.
しかし第1図に示すように先端面を平担とした
押しピン8を使用したとすると、次のような問題
が生ずる。その第1は放熱部4Aの厚みにバラツ
キがある場合である。たとえば放熱部4Aとして
厚み1.5mmとした場合、その許容誤差は±0.05mm
とされている。そこで押しピン8として厚み1.5
mmの放熱部4Aを押さえこむに必要な長さに設定
したとすると、たとえば放熱部4Aが(1.5−
0.05=1.45mm)の厚みであつたとすれば、押しピ
ン8の先端面と放熱部4Aとの間に0.05mmの隙間
が生ずるようになり、押しピン8による放熱部4
Aの押さえが不可能となる。 However, if a push pin 8 with a flat tip end surface as shown in FIG. 1 is used, the following problem will occur. The first case is when there is variation in the thickness of the heat dissipation section 4A. For example, if the thickness of heat dissipation part 4A is 1.5 mm, the tolerance is ±0.05 mm.
It is said that Therefore, as push pin 8, the thickness is 1.5 mm.
If we set the length necessary to hold down the heat dissipation part 4A of mm, for example, the heat dissipation part 4A is (1.5-
0.05=1.45 mm), a gap of 0.05 mm will be created between the tip end surface of the push pin 8 and the heat dissipation part 4A, and the heat dissipation part 4 by the push pin 8 will
It becomes impossible to hold A.
逆に放熱部4Aが(1.5+0.05=1.55mm)の厚み
であつたとすると、押しピン8が放熱部4Aを押
さえこんだとき下金型1と上金型2との衝合面に
0.05mmの隙間が生ずるようになり、この隙間の存
在により、モールド後の製品の周壁にバリが生ず
るようになる。したがつてこのときはこのバリを
除去する工程が必要となつてくる。 Conversely, if the heat radiation part 4A has a thickness of (1.5 + 0.05 = 1.55 mm), when the push pin 8 presses down the heat radiation part 4A, the abutment surface between the lower mold 1 and the upper mold 2
A gap of 0.05mm is created, and the existence of this gap causes burrs to form on the peripheral wall of the product after molding. Therefore, in this case, a step to remove this burr becomes necessary.
第2の問題は耐湿性の低下である。上記のよう
に押しピン8を設置して樹脂モールドするので、
モールド後の製品には押しピン8の跡である孔が
形成されることになる。そしてこの孔の底面に放
熱部4Aの表面が露呈している。上記のように押
しピン8として先端面を平坦としたものを使用し
ていれば、放熱部4Aの露呈面積は押しピン8の
先端面と同程度の面積となる。そのためこの孔に
湿気がたまつたとすると、その湿気と触れる面積
は広くなり、それだけ湿気により損なわれる恐れ
がでてくる。しかもこのように多量の湿気が触れ
るとすると、ここから、放熱部4Aとモールド樹
脂との境面を通つて内部に湿気が侵入しやすくな
る。このような湿気が侵入すればチツプ3,ワイ
ヤ6等が損なわれるようになることは明らかであ
る。 The second problem is a decrease in moisture resistance. Since the push pin 8 is installed and resin molded as described above,
A hole, which is the mark of the push pin 8, will be formed in the product after molding. The surface of the heat dissipation section 4A is exposed at the bottom of this hole. If the push pin 8 has a flat end surface as described above, the exposed area of the heat dissipation portion 4A will be approximately the same as the end surface of the push pin 8. Therefore, if moisture accumulates in these holes, the surface area that comes into contact with the moisture increases, and the risk of damage increases. Moreover, if such a large amount of moisture comes into contact with the heat dissipating portion 4A, the moisture easily enters the interior through the interface between the heat dissipating portion 4A and the molded resin. It is clear that if such moisture enters, the chip 3, wire 6, etc. will be damaged.
この発明は放熱部の周囲,製品の周壁にバリが
できないように半導体装置を製造することを目的
とする。 An object of the present invention is to manufacture a semiconductor device so that burrs are not formed around a heat dissipation part or on the peripheral wall of the product.
又この発明は耐湿性が損なわれないように半導
体装置を製造することを目的とする。 Another object of the present invention is to manufacture a semiconductor device so that moisture resistance is not impaired.
この発明は放熱部4Aを押さえこむ押しピン8
として第2図に示すように先端部8Aをすい
(錐)状としたことを特徴とする。押しピン8と
して丸棒状のものを使用したときは先端部8Aを
円すい状とすればよいし、又角棒状のものを使用
したときは角すい状とすればよい。そして押しピ
ン8によつて放熱部4Aを金型の内面に押しつけ
た状態でパツケージ用の樹脂を注型する。 This invention has a push pin 8 that presses down the heat dissipation part 4A.
As shown in FIG. 2, the tip 8A is shaped like a cone. When a round bar-shaped push pin 8 is used, the tip 8A may be conical, and when a square bar-shaped push pin 8 is used, it may be pyramid-shaped. Then, resin for the package is poured into the mold with the heat dissipating portion 4A pressed against the inner surface of the mold by the push pins 8.
第2図の構成において押しピン8として許容誤
差の最小値分だけ薄い厚み(1.45mm)の放熱部4
Aを押さえこむに足る長さに設定しておいたとす
る。今放熱部4Aが基準厚(1.5mm)又はこれよ
り許容誤差の最大値分だけ厚み(1.55mm)であつ
たとき押しピン8はその先端部がすい状とされて
いるため、その先端部が放熱部4Aの表面にくい
こむようになる。このときのくいこみ深さは0.05
〜0.1mm程度である。そしてこのくいこみによつ
て放熱部4Aは押しピン8によつて充分押さえこ
まれるようになる。したがつて上下両金型1,2
の衝合面に隙間が生ずる恐れはなくなる。放熱部
4Aが許容誤差の最小値分だけ薄いときはこの程
度の厚みの放熱部4Aを押さえこむのに足る長さ
に押しピン8が設定されてあるから、その押さえ
こみは充分である。このようにして放熱部4Aと
してその厚みにバラツキがあつても、放熱部4A
の押しピン8による押さえこみは確実である。そ
して放熱部4Aの周囲或いは製品の周壁にバリが
生ずるようなことはこれをもつて防止することが
できるようになる。 In the configuration shown in Figure 2, the heat dissipation part 4 is thinner (1.45 mm) by the minimum allowable error as the push pin 8.
Let's assume that the length is set to be enough to hold down A. Now, when the heat dissipation part 4A is the standard thickness (1.5 mm) or thicker than this by the maximum allowable value (1.55 mm), the tip of the push pin 8 is cone-shaped. It becomes embedded in the surface of the heat dissipation section 4A. The bite depth at this time is 0.05
~0.1mm. Due to this biting, the heat radiating portion 4A is sufficiently pressed down by the push pin 8. Therefore, both upper and lower molds 1 and 2
There is no possibility that a gap will form on the abutting surfaces. When the heat dissipation section 4A is thin by the minimum allowable error, the push pin 8 is set to a length sufficient to press down the heat dissipation section 4A having such a thickness, so that the push pin 8 is sufficient to hold down the heat dissipation section 4A. In this way, even if there is variation in the thickness of the heat dissipating part 4A, the heat dissipating part 4A
The pressing by the push pin 8 is reliable. This makes it possible to prevent burrs from forming around the heat radiating section 4A or on the peripheral wall of the product.
一方、モールド後において、樹脂モールドによ
るパツケージ12には押しピン8の跡に孔13が
形成されることになる(第4図以降参照。)。しか
しこの孔13の下端面は、押しピン8の先端部と
同形のすい状となる。そのため押しピン8として
先端面を平坦としたものを使用したときのように
その先端面と同面積分だけ放熱部4Aが露呈する
ことはなく、その露呈部分は点又は僅少な面積分
である。これによつて孔13に湿気が入つたとし
ても、湿気に接する放熱部4Aの面積は極く僅か
である。そのためパツケージ12内に孔13から
湿気が侵入するのが充分阻止されるようになる。 On the other hand, after molding, a hole 13 is formed in the resin-molded package 12 at the mark of the push pin 8 (see FIGS. 4 and subsequent figures). However, the lower end surface of this hole 13 has a cone shape that is the same shape as the tip of the push pin 8. Therefore, unlike when a push pin 8 with a flat tip surface is used, the heat dissipating portion 4A is not exposed by the same area as the tip surface, but the exposed portion is a point or a small area. As a result, even if moisture enters the hole 13, the area of the heat radiating portion 4A that is in contact with the moisture is extremely small. Therefore, moisture is sufficiently prevented from entering the package 12 through the holes 13.
第2図に示すように押しピン8を第1図と同じ
く押付板9で押しつけるようにした場合は、第1
図の場合よりも押しピン8の寸法を高精度とする
必要はなくなるが、しかしなお或る程度の寸法精
度が要求される。これを更に解決したのが第3図
である。この構成は押しピン8をバネ14を介し
て押付板9で押さえこむようにしてある。このよ
うに押しピン8を弾力的に押さえておくと、放熱
部4Aの厚みのバラツキに応じて押しピン8は弾
力に抗して上昇し、或いは弾力で下降するように
なり、常に放熱部4Aを弾力的に押さえこむよう
になる。したがつて押しピン8の長さを高精度と
する必要はなくなる。なお放熱部4Aを上金型2
の面に配置し、下方から押しピン8によつて押し
つけるようにしてもよい。 As shown in Fig. 2, when the push pin 8 is pressed by the pressing plate 9 as in Fig. 1, the first
Although it is no longer necessary to make the dimensions of the push pin 8 more precise than in the case shown in the figure, a certain degree of dimensional precision is still required. Figure 3 shows a further solution to this problem. In this configuration, the push pin 8 is pressed down by a push plate 9 via a spring 14. If the push pin 8 is held elastically in this way, the push pin 8 will rise against the elasticity or fall due to the elasticity depending on the variation in the thickness of the heat radiating part 4A, so that the heat radiating part 4A is always pressed down. It begins to hold down elastically. Therefore, it is no longer necessary to make the length of the push pin 8 highly accurate. Note that the heat dissipation part 4A is placed in the upper mold 2.
It may be placed on the surface and pressed from below by the push pin 8.
第4図乃至第6図はこの発明によつて製作され
た半導体装置たとえばパワートランジスタの横断
面図、平断面図及び底面図である。なお図中15
は必要によりパツケージ12を貫通するように形
成された貫通孔で、これはトランジスタを配線基
板等に設置するときの取付ネジの挿入に使用す
る。 4 to 6 are a cross-sectional view, a plan cross-sectional view, and a bottom view of a semiconductor device, such as a power transistor, manufactured according to the present invention. Note that 15 in the figure
A through hole is formed to pass through the package 12 as necessary, and is used for inserting a mounting screw when installing the transistor on a wiring board or the like.
以上詳述したようにこの発明によれば、製品の
周壁,放熱板の周囲等にバリが生ずることのない
ように製造することができ、又得られた製品の耐
湿性を向上させることができる効果を奏する。 As detailed above, according to the present invention, it is possible to manufacture a product without causing burrs on the peripheral wall or around the heat sink, and it is also possible to improve the moisture resistance of the obtained product. be effective.
第1図は従来法の説明のための断面図、第2図
はこの発明による製造方法を説明するための断面
図、第3図はこの発明の他の製造方法を説明する
ための断面図、第4図はこの発明による製造方法
により製造されたトランジスタの横断面図、第5
図は同平断面図、第6図は同底面図である。
1,2……金型、3……半導体チツプ、4……
リード、4A……放熱部、8……押しピン、8A
……先端部、12……パツケージ、14……バ
ネ。
FIG. 1 is a sectional view for explaining the conventional method, FIG. 2 is a sectional view for explaining the manufacturing method according to the present invention, and FIG. 3 is a sectional view for explaining another manufacturing method of the present invention. FIG. 4 is a cross-sectional view of a transistor manufactured by the manufacturing method according to the present invention;
The figure is a sectional plan view of the same, and FIG. 6 is a bottom view of the same. 1, 2... Mold, 3... Semiconductor chip, 4...
Lead, 4A...Heat radiation part, 8...Push pin, 8A
...Tip, 12...Package, 14...Spring.
Claims (1)
記パツケージの表面に放熱部を露呈せしめてなる
半導体装置の製造方法において、先端をすい状と
した押しピンによつて前記放熱部をモールド用の
金型の内面に押しつけた状態で前記パツケージ用
のモールド樹脂を注型することを特徴とする半導
体装置の製造方法。 2 モールド樹脂からなるパツケージを備え、前
記パツケージの表面に放熱部を露呈せしめてなる
半導体装置の製造方法において、先端をすい状と
した押しピンによつて前記放熱部をモールド用の
金型の内面に弾力的に押しつけた状態で前記パツ
ケージ用のモールド樹脂を注型することを特徴と
する半導体装置の製造方法。[Scope of Claims] 1. A method for manufacturing a semiconductor device comprising a package made of molded resin and a heat dissipation section exposed on the surface of the package, wherein the heat dissipation section is molded with a push pin having a cone-shaped tip. 1. A method of manufacturing a semiconductor device, characterized in that the molding resin for the package is cast while being pressed against the inner surface of a mold for the package. 2. In a method for manufacturing a semiconductor device comprising a package made of a molded resin and a heat dissipating section exposed on the surface of the package, the heat dissipating section is attached to the inner surface of a molding die using a push pin with a cone-shaped tip. A method of manufacturing a semiconductor device, characterized in that the molding resin for the package is cast while being elastically pressed against the package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57174852A JPS5963735A (en) | 1982-10-05 | 1982-10-05 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57174852A JPS5963735A (en) | 1982-10-05 | 1982-10-05 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5963735A JPS5963735A (en) | 1984-04-11 |
| JPS6244408B2 true JPS6244408B2 (en) | 1987-09-21 |
Family
ID=15985772
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57174852A Granted JPS5963735A (en) | 1982-10-05 | 1982-10-05 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5963735A (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02306639A (en) * | 1989-05-22 | 1990-12-20 | Toshiba Corp | Resin encapsulating method for semiconductor device |
| JP2708084B2 (en) * | 1992-03-23 | 1998-02-04 | ワイケイケイ株式会社 | Method of attaching hook-and-loop fastener to seat cushion material and foam molding die |
| DE19642088A1 (en) * | 1996-10-12 | 1998-04-16 | Bosch Gmbh Robert | Manufacturing a micro:textured component |
| JP4519424B2 (en) | 2003-06-26 | 2010-08-04 | ルネサスエレクトロニクス株式会社 | Resin mold type semiconductor device |
| DE102007020618B8 (en) * | 2007-04-30 | 2009-03-12 | Danfoss Silicon Power Gmbh | Method for producing a solid power module and transistor module made therewith |
| CN102468190A (en) * | 2010-11-12 | 2012-05-23 | 三星半导体(中国)研究开发有限公司 | A packaging mold and semiconductor packaging process using the mold |
| DE102012222679A1 (en) * | 2012-12-10 | 2014-06-12 | Robert Bosch Gmbh | Method for producing a switching module and an associated grid module and an associated grid module and corresponding electronic module |
| US9269597B2 (en) * | 2013-01-23 | 2016-02-23 | Microchip Technology Incorporated | Open cavity plastic package |
| EP2927954B1 (en) | 2014-04-02 | 2021-06-09 | Brusa Elektronik AG | Fastening system for a power module |
| JP6228904B2 (en) * | 2014-10-16 | 2017-11-08 | 新電元工業株式会社 | Semiconductor device manufacturing method, semiconductor device, mold and lead frame |
| JP6319399B2 (en) * | 2016-10-28 | 2018-05-09 | 株式会社デンソー | Insert mold |
| DE102020104220A1 (en) | 2020-02-18 | 2021-08-19 | Infineon Technologies Ag | Transistor outline package and transistor outline package arrangement |
| CN115023056A (en) * | 2022-05-30 | 2022-09-06 | 青岛歌尔微电子研究院有限公司 | Selective packaging method for packaged products |
| CN117584359A (en) * | 2023-10-20 | 2024-02-23 | 敦南微电子(无锡)有限公司 | Plastic sealing mold and sealing method, pressing device and device for semiconductor devices |
-
1982
- 1982-10-05 JP JP57174852A patent/JPS5963735A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5963735A (en) | 1984-04-11 |
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