JPS6244427B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit in which a MOS transistor and a MOS diode type capacitor are arranged in parallel, and is particularly suitable for a memory element.

A MOS diode consisting of a metal layer (conductor layer), an oxide layer (insulator), and a semiconductor substrate is used as a capacitor, and it can be easily formed on the same substrate as a MOS transistor, making it an important element in integrated circuits. It is well known that it is becoming popular. Also, in such an integrated circuit,
It is well known that for electrical isolation of MOS transistors, an impurity layer in which a high concentration of impurity is implanted is provided in a semiconductor substrate. In order to miniaturize such integrated circuits in which MOS transistors, isolation layers, and MOS capacitors are densely arranged on the same substrate, various measures such as improving mask precision have been taken, but recently, miniaturization It appears that the government has reached its limit. As a solution to this problem, it has been proposed, for example, to use a two-story structure for transistors and capacitors in memory elements (Japanese Patent Application No. 127781-1981). Although this configuration is extremely effective in terms of reducing the area of the substrate, it complicates the manufacturing process and is therefore problematic in terms of reducing manufacturing costs.

Therefore, an object of the present invention is to improve the degree of integration of a semiconductor integrated circuit in which a MOS transistor and a MOS diode type capacitor are arranged side by side.

In order to improve the degree of integration of the above-mentioned integrated circuit, the present invention reduces the occupied area by sharing the separation layer and the semiconductor side electrode of the MOS diode type capacitor.

According to the present invention, a MOS transistor and a MOS diode type capacitor are arranged side by side on the same semiconductor substrate, and one conductor layer electrode of the capacitor that is not connected to the MOS transistor is formed on the surface of the semiconductor substrate. and in which the other conductor layer electrode connected to the MOS transistor is provided above the one conductor layer electrode via a dielectric, the one conductor layer electrode is connected to the High concentration that is of the same conductivity type as the semiconductor substrate and whose threshold voltage (also called flat band voltage) is greater than the sum of the voltage to be applied to the semiconductor substrate and the voltage to be applied to the electrode at the other end of the capacitor. A highly concentrated impurity layer of the same conductivity type as the semiconductor substrate is provided below the electrode of the MOS transistor connected to the capacitor and connected to the conductive layer electrode. A semiconductor integrated circuit is obtained.

According to the present invention, the degree of integration of the integrated circuit can be extremely increased, and the characteristics can be stabilized.

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows the structure of a memory element to which the present invention is applied, in which a is a cross-sectional view, b is a plan view, and c is an equivalent circuit diagram. However, in the plan view of b, in order to make the drawing easier to see, the oxide film (described later) formed over almost the entire area is removed. In the figure, 1 is a p-type semiconductor substrate, 2 is a selection transistor section, and 3 is a data storage capacitor section, and the memory as a whole usually has a large number of selection transistors and data storage capacitors lined up. Further, 4 and 5 are both n ⁺ diffusion layers, and constitute the source electrode and drain electrode of the selection transistor section 2, respectively. And in this case source electrode 4
form the pit lines of the memory element. Reference numeral 6 denotes a metal wiring, which serves as the gate electrode of the selection transistor 2 and also forms a word line. Reference numeral 7 is a silicon oxide film having a high dielectric constant, which is very thin at about 1000 Å, and serves to form an n-channel region along the semiconductor surface between the source electrode 4 and the drain electrode 5. Reference numeral 8 is a conductor layer (may be made of polycrystalline silicon) of about 5000 Å, which forms one electrode of the storage capacitor 3 and is coupled to the drain electrode 5. Reference numeral 9 is an oxide film having a thickness of about 1000 Å and having a high dielectric constant. This may be the same as the oxide film 7. A highly concentrated p-type impurity layer 10 is particularly provided in the present invention and forms the other electrode of the storage capacitor 3. Note that the dimensions of this element in the planar direction may be considered in proportion to the dimensions in the figure, with the width of the built line (source electrode) 4 in b being approximately 5 microns.

The impurity concentration of the p-type impurity layer 10 is kept sufficiently high, and its flat band voltage V _FB is determined by the bias voltage between the conductive layer electrode 8 and the semiconductor substrate 1 being equal to the power supply voltage V _DD and the substrate bias voltage, that is, the back gate voltage V _BG The majority carriers do not disappear on the semiconductor surface even when the sum of In other words, when the voltage value is expressed as an absolute value, the following relationship is maintained: V _FB >V _DD +V _BG (1). Such a relationship can be established, for example, by setting the impurity concentration of p-type silicon to 1×10 ¹⁵ atoms/cm ³ , using silicon oxide with a dielectric constant ε of approximately 12 as the oxide film, and making the thickness approximately 1,000 μm.
Å, V _DD is 12 V, and V _BG is −5 V, the amount of impurity to be implanted is approximately 5×10 ¹² atoms/cm ³ if B ⁺ boron ions are implanted.

P-type impurity layer 10 formed as above
, the voltage between the conductor layer electrode 8 and the semiconductor substrate 1 is V
Since a depletion layer does not substantially occur in it unless _DD +V _BG is exceeded, it can be regarded as a conductive layer like the electrode 8. Therefore, the semiconductor substrate 1 can be used as a power supply line 1a coupled to one terminal of a data storage capacitor. Furthermore, since this p-type impurity layer 10 has a conductivity type opposite to that of the drain electrode 5, which is an n ⁺ layer, it is useful for separating the selection transistor 2. Moreover, at this time, it is also useful for separating the bit lines 4. Therefore, a high impurity layer for separation, which was conventionally provided independently, becomes unnecessary. That is, the entire surface of the selection transistor 2 other than the channel, source region, and drain region can be used as a capacitor. This means that the conductor layer electrode 8 drawn in figure b
Although it looks small at first glance in Figure A, it can be seen that it has become extremely large, covering all parts except the bit line 4 and word line 6. Correspondingly, a p-type impurity layer 10 is formed on the entire surface of the semiconductor substrate 1 except for the bit line 4, the drain electrode 5, and the n-channel forming region between this and the source electrode. Transistor 2 is completely isolated from the others. Note that the space between adjacent elements 11 (only a part of the ends) will be explained later.

Therefore, according to the present invention, the memory element can be made much smaller than the conventional one. An additional advantage is that the capacitance of the storage capacitor can be kept close to a maximum value depending on the material and dimensions. Conventionally, the capacitance between a semiconductor and a conductive layer without special treatment decreases as the applied voltage increases, and in reality, variable capacitance is often utilized. . However, from a practical standpoint, a capacitance change of about 10% is often not a particular problem, so the impurity concentration may be reduced as long as it does not violate the conditions shown in equation (1) above.

FIG. 1c shows an equivalent circuit of a memory element having a p-type impurity layer formed as described above.
As can be seen from the figure, since this device can use the semiconductor substrate 1 as the power supply line 1a, it becomes a two-wire memory requiring only the bit line 2 and word line 3 as wiring.

Note that the capacitance of the storage capacitor formed in this manner includes the capacitance between the drain electrode 5, which is an N ⁺ diffusion layer, and the semiconductor substrate 1, so before forming the drain electrode 5, the capacitance between the semiconductor substrate 1 and the drain electrode 5 is If a p ⁺ impurity layer 12 of the same conductivity type is formed, it will be more effective because it will be connected to the p ⁺ impurity layer 10. If conditions are selected appropriately, the p ⁺ impurity layer 1
It can be increased by about 50% compared to the case without 2. In order to further increase the capacity of the storage capacitor, silicon nitride, which has a higher dielectric constant, may be used as the oxide film 9 instead of silicon oxide.

The only difference in the manufacturing method of the device shown in FIG. 1 from conventional devices is that the step of forming the conductor layer 8 is increased, and this step can be carried out without any special measures. It is. Therefore, a description of the manufacturing of the device will be omitted. However, in b, there is a gap of about 4 microns between adjacent elements 11, but this is not desirable in terms of mass production, as it would require considerably high precision to make them closer than this when using a normal mask.
A solution to this point will be explained later. Regarding the details, the insulating film 13
(The thick portion is about 6000 Å) does not need to be thick over the entire conductor film 8, but only the lower part of the word line 6 in the capacitor 3 portion needs to be thick.

FIG. 2 shows a second embodiment of the present invention, in which a is a cross-sectional view and b is an equivalent circuit. In contrast to the case of FIG. 1, this element is a three-transistor dynamic memory cell. In the figure, 21 is a data storage transistor, 22 is a read selection transistor, 23 is a write transistor, 24 is a storage capacitor, _X1 is a read word line, _X2 is a write word line, _Y1 is a read bit line, and Y ₂ represents a write bit. and 25 is a semiconductor substrate, 26
The five similar regions represented by are the n ⁺ layers and serve as the electrodes of each transistor or storage capacitor. In this case, the conductive film 27 serves not only as one electrode of the storage capacitor 24 but also as the gate electrode of the data storage transistor 21. Therefore, the larger the capacitance of the capacitor, the longer the data retention time becomes, and the conditions for reproduction are relaxed. This device can be manufactured in an extremely simple manner, starting from the n ⁺ layer 26 and forming it sequentially upward. Approximately 1000Å represented by 28
The process can be simplified by forming three oxide films at the same time.

FIG. 3 is a diagram showing a third embodiment of the present invention,
A shows a plan view, and b shows a cross section taken along the line A-A'. Earlier, in the description of the embodiment shown in FIG. 1, it was mentioned that the spacing between the elements was kept below a certain level, but this embodiment is intended to solve this problem. Its feature is that the storage capacitor's conductor layer (8 in Figure 1) is composed of two types: one that is completely flat (31) and one that is raised at both ends (32), and these elements are arranged alternately. . In particular, as can be seen from b, each conductor layer can be formed in two steps and at two levels, so there is no need to provide space for a mask in between, and the capacitors can be formed laterally (below the bit line 33). direction) without any gaps, and it is possible to improve the degree of integration. Note that the construction of the word line 34 and other parts other than the conductor layer is exactly the same as in the case of FIG.

FIG. 4 shows a fourth embodiment of the present invention, in which a is a plan view, b is a sectional view taken along line B-B' in a, and c is a view taken along C-C' in the same way. . The preparation of two types of conductor layers, a flat one 41 and one with raised ends 42, is the same as in the case of FIG. 3, but the upper end is in the direction of the word line 43, Therefore, the elements can be formed without gaps in the word line direction, and the bit line 44 is completely different from that in FIG. To explain the latter, the bit line 44 is connected to the semiconductor substrate 1.
This is because only the source electrode 45 is formed in the semiconductor substrate. This is because it is necessary to form (part of) the conductor layer 42 and the p-type impurity layer 47 also in the portion indicated by 46 in a. For this reason contact 4
8 to connect the source electrode 45 and the bit line 44. Therefore, the manufacturing process becomes somewhat complicated. However, the technique itself can be performed using conventionally well-known methods.

FIG. 5 shows a plan view of a fifth embodiment of the present invention. This converts the conductor layer of the capacitor into 3
It is formed of three levels 51, 52, and 53, and all regions other than the channel region, source region, and drain region of the transistor are tightly packed without any gaps. This embodiment is a combination of the embodiments shown in FIGS. 3 and 4, and uses the same bit line 54 and word line 55 as in the embodiment shown in FIG.

FIG. 6 shows a sixth embodiment of the present invention, in which a is a sectional view and b is a plan view.

Further, FIG. 7 shows an equivalent circuit of the element shown in FIG. 6. A memory element of the type is shown in which the gate electrode 62 of the selection transistor 61 is in common with an electrode portion 64 forming 63a of one of the storage capacitors 63. 63b forms the other storage capacitor of the same construction as that in FIG. In this case, the conductive film layer 65 becomes a common electrode for both capacitors, and as compared to the case of FIG.
The capacity as shown in FIG. The p-type impurity layer 66 is formed on a wide surface corresponding to the conductor layer 65. The bit line 67 (source electrode) and drain electrode 68 may have exactly the same structure as in the case of FIG.

FIG. 8 shows a seventh embodiment of the present invention, in which a is a sectional view and b is a plan view. The equivalent circuit of this embodiment is exactly the same as that shown in FIG. It is basically the same as the embodiment shown in FIG. 6, but the difference is that the word line 71 and the upper capacitor electrode 72 are separated, and the transistor gate electrode 73 and capacitor electrode 72 are integrated. be. The advantage of this is that the conductor layer 74 and the gate electrode 73 (electrode 72) can be formed in two separate steps, so that the conductor layer 74 and the gate electrode 73 (electrode 72) can be formed in two steps. For the same reason as the level, the gate electrode 73 and the conductor layer 74 can be placed close to each other. Therefore, the drain electrode can be made smaller, which has the effect of increasing the degree of integration. Or, expressed in another way, the capacitance of the capacitor can be increased.

FIG. 9 is a cross-sectional view of an eighth embodiment of the present invention, in which the capacitor is formed in a concave shape, and the capacitor region 81 and the selection transistor 82 region are flat along the direction of the word line 83. ing. The equivalent circuit is the same as that shown in FIG. Since the surface is flat, there is no need to worry about disconnection of the word line 83. Each n ⁺ electrode represented by 84 is preferably formed by ion implantation.

FIG. 10 shows a cross section of a second embodiment of the invention, which is substantially the same as that of FIG. The only difference is that in the case of Figure 9, a mask was used to make the part where the capacitor was to be formed into a concave shape, whereas in this implementation, the 1.00 plane of Si was etched without using a mask, so-called V
It has a groove formed therein. In this case, there is an advantage that the effective area of the capacitor section is slightly larger than that of FIG. 9. However, the flatness of the surface is slightly reduced.

In the above description, a p-type semiconductor substrate is used, but it goes without saying that it is also possible to replace this with an n-type semiconductor substrate. At this time, it is necessary to change the conductivity type of each electrode and impurity layer.
There is no need for any particular explanation.

Furthermore, although the above embodiments were carried out regarding memory elements, the present invention is not limited thereto;
Needless to say, the present invention can be applied to all other semiconductor logic circuits that include both MOS transistors and MOS diode type capacitors.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of a memory element to which the present invention is applied, a is a cross-sectional view, b is a plan view, and c is an equivalent circuit diagram, and FIG. 2 is a cross-sectional view a of a second embodiment of the present invention.
FIG. 3 shows the equivalent circuit b of the present invention.
FIG. 4 is a diagram showing plane a and cross section b of the fourth embodiment of the present invention, FIG. 5 is a diagram showing plane a and cross section (b and c) of the fourth embodiment of the present invention, and FIG. FIG. 6 is a diagram showing cross section a and plane b of the sixth embodiment of the present invention, FIG. 7 is a diagram showing an equivalent circuit of the element in FIG. 6, and FIG. is the seventh aspect of the present invention.
FIGS. 8, 9 and 10 are diagrams showing the cross section a and plane b of the embodiment of the present invention.
It is a figure which showed each cross-sectional view of 8th and 9th Example. Explanation of symbols: 1 is a p-type semiconductor substrate, 2 is a selection transistor, 3 is a storage capacitor, 4 is a source electrode (n ⁺ ), 5 is a drain electrode (n ⁺ ), 6 is a gate electrode (word line), 7 is a oxide film, 8 is a conductor layer,
Reference numeral 9 indicates an oxide film, and reference numeral 10 indicates a p-type impurity layer.

Claims (1)

[Claims] 1 MOS transistor and
MOS diode type capacitors are arranged in parallel, one conductor layer electrode of the capacitor not connected to the MOS transistor is formed on the surface of the semiconductor substrate, and the other conductor layer electrode is connected to the MOS transistor. In an integrated circuit in which a layer electrode is provided above the one conductor layer electrode via a dielectric, the one conductor layer electrode is of the same conductivity type as the semiconductor substrate and has a threshold voltage that is higher than that of the semiconductor substrate. The impurity layer has a high concentration such that the voltage is greater than the sum of the voltage to be applied to the substrate and the voltage to be applied to the electrode at the other end of the capacitor, and the impurity layer has a high concentration that is higher than the voltage that is the sum of the voltage to be applied to the substrate and the voltage to be applied to the electrode at the other end of the capacitor. A semiconductor integrated circuit characterized in that a high concentration impurity layer of the same conductivity type as the semiconductor substrate is provided below and connected to the conductor layer electrode.