JPS6244471B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frame frequency conversion circuit for television signals, and particularly to a circuit system for converting a signal with a low frame frequency, such as a television signal based on the PAL system, into a television signal with a high frame frequency.

Currently, the frame frequency of television signals is
This varies depending on the television signal system, and some, like the PAL system mentioned above, have a frame frequency as low as 25Hz. When an image reproduced from a television signal with such a low frame frequency is received in a bright room, it may cause flickering due to human visual characteristics, which may be bothersome. However, when the frame frequency becomes 30Hz or higher, the flicker disappears.

On the other hand, regarding the method of converting a signal of one television standard to a television signal of another standard,
It is conventionally known as a format converter for television signals (for example, "Recent Television Standard Format Converter", Journal of the TV Society, Vol. 29, No. 10). In this conventional device, the television format before conversion and the television format after conversion each have their own standards, such as the NTSC format and the PAL format.
Both must meet strict standards.

Therefore, there are many difficulties in the configuration of the device, such as the need to provide a slight difference in the writing and reading frequencies of the field memory or frame memory that records the screen of the television signal. It is also necessary to perform interpolation in conjunction with the conversion of the number of scanning lines.

However, if the purpose is simply to increase the frame frequency to prevent flicker based on the frame frequency, this is a problem within the receiver, and there is a degree of freedom in the form of the converted signal. Therefore, problems in device configuration based on the above-mentioned standard conversion do not necessarily occur. Further, there is no need to store all portions of the television signal that are not displayed on the screen in the memory.

The present invention is to realize a frame frequency conversion circuit for a television signal with a simple configuration in order to obtain an image with less flicker.

In order to achieve the above object, the television signal frame frequency conversion circuit according to the present invention stores a television signal with a frame frequency f ₁ in a storage device, and out of the total number of frames N of the stored signal, N×
The present invention is characterized in that it is configured to equivalently read out pixels of f ₁ /f ₂ and reproduce a television signal of frame frequency f ₂ .

Hereinafter, the present invention will be explained in detail using the drawings.
Figure 1 is a general explanatory diagram for frame frequency conversion, and the line A above shows a part of the frame frequency of 25Hz, with a period of 5 frames.
They are numbered A ₁ , A ₂ , A ₃ ...A ₅ . Line B at the bottom of the figure shows a frame with a frame frequency of 30Hz, and the second frame A ₂ is repeated twice,
B ₁ , B ₂ , B ₂ ′, B _{3 .} . . are numbered and shown with a period of six frames.

Now, assume that frame A ₁ is written to the memory and read out at time B ₁ (a method for shortening the time of B ₁ compared to the time of A ₁ will be described later).
Similarly, A ₂ and B ₂ are written and read respectively. At this time, it is assumed that the writing and reading of frames A ₂ and B ₂ are set to be completed synchronously. When reading frame B ₂ ', focusing on an arbitrary address, since frame A ₃ has not yet been written when frame B ₂ is read, the information of frame A ₂ will be read. Then, the information of frame A ₃ will be read out at the time of frame B ₃ . Repeat the same operation below. In this way, frames A ₁ , A ₂ , A ₃ ,
The information of A ₄ , A ₅ is transferred to frames B ₁ , B ₂ , B ₂ ′, B ₃ , B ₄ ,
It is read out as _B5 and the frame number is converted.

FIG. 2 is a diagram showing the configuration of an embodiment of a television signal frame frequency conversion circuit according to the present invention.

An analog television signal whose frame frequency is to be converted passes through an input terminal 1, and a portion thereof is converted into a digital signal by an A/D converter and is applied to a memory 4.

FIG. 3 is a diagram for explaining the relationship between the number of pixels or the capacity of the memory when writing to and reading from the memory.

Now, as an example, a television signal based on the PAL system will be described as an original signal with a low frame frequency (A ₁ , A ₂ , . . . in FIG. 1).
As shown in the outer frame of FIG. 3, one frame of a PAL television signal can be expressed as 625 scanning lines and 966 pixels on one scanning line. Therefore, the total number of pixels in one frame is 625×966.
Some of this total number of pixels are not directly related to image reproduction, so as shown in the inner frame of Figure 3, only 875 pixels out of the pixels of one scanning line are used for 575 scanning lines. When used for readout, the total number of pixels and the number of pixels used for readout are 575×875/625×966=5/6 times.

In other words, if the original input signal is recorded over an area of 625 x 966 pixels, and then read out only 575 x 875 pixels by synchronizing the pixel frequency, the time will be precisely multiplied by 5/6. , the operations shown in FIG. 1 are performed.

Note that at this time, it is not necessary to prepare a memory device for 625×966 pixels, but it is sufficient to prepare a memory device for 575×875 pixels. Furthermore, it is obvious that the synchronization signal does not necessarily have to be prepared. In this case, it is possible that only the address circuit operates and there is no corresponding memory cell, or that the address circuit is inactive.

Returning now to FIG. 2, the original input television signal is applied to timing circuit 6. The timing circuit 6 separates and extracts the vertical synchronization signal. and,
The counters of the write address circuit 7 and the read address circuit 8 are reset once every five frames (corresponding to time t=0 in FIG. 1). Further, a horizontal synchronizing signal is extracted by a conventionally known method, and a sampling clock is generated 966 times per scanning line by a conventionally known phase pull-in circuit or the like. This clock is connected to each address circuit 7, 8.
and is added to the D/A converter 5. After this,
The counter of the write address circuit 7 counts 625.times.966 as a synchronization, and the counter of the read address circuit 8 performs writing and reading of information in the range shown in FIG. 3 using 575.times.875 as a synchronization. As a result, the frame frequency is converted according to the time relationship shown in FIG.

As described above, according to the present invention, the same clock signal is used from the A/D conversion circuit 3 for digitizing the original input signal to the D/A conversion circuit 5 for the converted signal. The configuration is extremely simple in that it can operate without interpolation between scanning lines.

It is clear that the present invention is not limited to the first embodiment, and for example, the following modifications can be considered.

In the above embodiment, each frame of the converted television signal has exactly the same number of pixels and is perfectly periodic, but even though it is not necessarily perfect, some margin period is provided, etc. , it is also possible to shift within a range that does not cause any problems in terms of the circuit.

The memory includes not only a completely random memory but also various modifications, such as switching delay lines in blocks, as long as they can equivalently input and output signals as in the above embodiment.

[Brief explanation of the drawing]

FIG. 1 is a time chart explaining the principle of operation of the present invention, FIG. 2 is a configuration diagram of an embodiment of a television signal frame frequency conversion circuit according to the present invention, and FIG. 3 is an explanation of the number of pixels in the above embodiment. This is a diagram. 1...Input terminal, 2...Output terminal, 3...A/
D conversion circuit, 4...frame memory, 5...D/
A converter, 6... synchronous signal separation circuit, 7... write address circuit, 8... read address circuit.

Claims (1)

[Scope of Claims] 1. A storage device, means for storing a television signal with a frame frequency f ₁ in the storage device, and means for reading out N·f ₁ /f ₂ pixels out of the total number of pixels N of the signal. What is claimed is: 1. A frame frequency conversion circuit for a television signal, comprising: a frame frequency converting circuit for reproducing a television signal having a frame frequency _f2 ;