JPS6244733B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a serial data transmission system using a time division multiplex transmission method used for remote control, equipment control, etc. Recently, relatively large-scale centralized control systems using programmable logic controllers are often seen in control systems for general mechanical plants and the like. In such centralized control systems, in many cases, various input devices such as limit switches, temperature switches, proximity switches, photoelectric switches, etc., and various output devices such as motors, plungers, and solenoid valves are connected to the center using separate signal lines. connected to the control device. In this case, in systems where there are a large number of these input/output devices and each input/output device is distributed over a relatively wide space, the wiring space and wiring cost that connect each input/output device and the central control unit become a major problem. Therefore, there is a strong desire to simplify signal transmission during this time by applying appropriate multiplex transmission. Various multiplex transmission systems have been known in the past, and can be used for signal transmission in the control system described above. However, conventional multiplex transmission systems assign a unique address to each terminal,
Each terminal has a circuit that determines its address,
The transmission control procedure including this address discrimination circuit is extremely complicated and sophisticated, resulting in an expensive device. Of course, there is a point in using such an advanced circuit system, but the control system using the programmable logic controller described above has many unnecessary functions, and therefore cannot adequately meet the above demands. Ta. This invention was made in view of the above-mentioned conventional problems, and the first purpose is to provide an optimal and simple method for signal transmission between input/output equipment and a central device in a control system using a programmable logic controller or the like. The object of the present invention is to provide a serial data transmission system. A further object of the present invention is to provide a serial data transmission system in which the wiring of the transmission line and the transmission and reception of data can be performed more simply and rationally in the above-mentioned transmission system. Hereinafter, embodiments of the present invention will be described in detail based on the drawings. FIG. 1 shows an embodiment of the configuration of a serial data transmission system according to the present invention. This system includes a master station 1 and an appropriate number of terminal devices 2A and 2B.
Each terminal device 2A, 2B is connected in series on a single transmission line l whose one end (left end) is connected to the master station 1. There are two types of terminal devices 2A and 2B: an input terminal device 2A to which an input device such as a limit switch is connected, and an output terminal device 2B to which an output device such as a motor or plunger is connected. However, these are not necessarily distinguished; for example, the terminal device may have both input and output functions. In the embodiment shown in FIG. 1, in order to make it easier to understand, two types of terminal devices are arranged, that is, an input terminal device 2A is arranged near the master station 1 side (left side), and an output terminal device is arranged in the subsequent stage. 2B is arranged, and the subsequent terminal devices are omitted. The master station 1 has one transmitting/receiving end Pm to which the left end of the line I is connected. Then, via the transmitting and receiving end Pm, it is connected to line l, a or b in Fig. 2.
As shown in the output waveform format, 4
The output mode is configured such that output operations are sequentially performed in each output mode M1, M2, M3, and M4 as one cycle. First, in the output mode M1, the first synchronization signal S
Outputs 1. This signal S1 is formed by continuously outputting a specific level ("L" or "H") for a certain period of time or more, which is sufficiently larger than the period to of the clock pulse CP. In the embodiment, the "L" output state is made continuous as shown in FIG. 2a or b. Next, in output mode M2, output data signals D1, D2, and D3 to be transmitted are output. These signals D1, D2, D3 are the clock pulses mentioned above.
It is sent superimposed on cp. In other words, the amplitude voltage (“H”) of each clock pulse cp is further increased by two levels.
They are superimposed by changing the values (“HH” and “HL”), and a predetermined number of these are output. In output mode M3, second synchronization signal S2 is output. This signal S2 is formed by continuously outputting a specific level ("H" or "L") different from the first synchronizing signal S1 for a predetermined period of time which is sufficiently larger than the period to of the clock pulse CP. In the embodiment, the "H" output state is made continuous as shown in FIG. 2a or b. And output mode M
4, in order to receive output data D6, D5, D4, a clock pulse cp of constant amplitude (“H”) is applied.
Output a predetermined number of. Next, the terminal devices 2A and 2B each include a relay transmission circuit 3, first and second synchronization signal detection circuits 4a and 4b, left and right data discrimination circuits 5a,
5b, a bidirectional shift register 6, a right data transmission circuit 7a, and a left data transmission circuit 7b. Here, to describe the input terminal device 2A in detail, the relay transmitting circuit 3 receives and relays a signal from the master station 1 side applied to its left transmitting/receiving end Pl,
The signal is output from the right transmitting/receiving end Pr to the subsequent terminal device connected in series thereto. The signals relayed by this circuit 3 are the data signal components D1, D2, D3 from the first synchronization signal S1 in the output mode M1 and the clock pulse cp in which the data signals D1, D2, D3 in the output mode M2 are superimposed. A clock pulse of constant amplitude (“H”) that is removed
cp, second synchronization signal S2 in output mode M3, and clock pulse in output mode M4.
It is cp. First and second synchronization signal detection circuits 4a, 4b
detect the first and second synchronization signals S1 and S2 applied to the left transmitting/receiving end Pl, respectively. The first synchronization signal detection circuit 4a outputs a detection signal S3 of the first synchronization signal S1 as shown in FIG. 2d, and the second synchronization signal detection circuit 4b outputs a detection signal S3 as shown in FIG. 2e. As such, the detection signal S4 of the second synchronization signal S2
are output respectively. The left and right data discrimination circuits 5a and 5b receive the clock pulses cp on which the data signals D1 to D6 are superimposed, which are applied to the left transmitting/receiving end Pl and the right transmitting/receiving end Pr, respectively, and output the data signals D1 to D6.
Discriminate and extract. FIG. 2c shows the discrimination and extracted signals D1 to D6. The bidirectional shift register 6 is switched to the right shift mode in response to the output S3 of the first synchronization signal detection circuit 4a, and is switched to the left shift mode in response to the output S4 of the second synchronization signal detection circuit 4b. can be switched to Further, the clock pulse cp applied to the left transmitting/receiving end Pl in output modes M2 and M4 is used as a shift clock. and,
The data signals D1 to D6 output from the left data discrimination circuit 5a are used as right shift inputs, and the data signals D6 to D6 output from the right data discrimination circuit 5b.
D4 and the subsequent "L" level empty data signal are input as left shift inputs. In this case, in the embodiment, input terminals P1 to P3 of the terminal devices 2A and 2B
Since there are three output terminals P4 to P6, each of them is provided with a 3-bit shift capacity accordingly. Further, the empty data signal is outputted until all the data signals D1 to D6 finish moving to the master station 1. The right data transmitting circuit 7a operates in an output mode M2 in which the shift register 6 is shifted to the right, and outputs the right shift output data D1 to D3 of the shift register 6 to the clock pulse cp output from the relay transmitting circuit 3. Overlap the right transmitting and receiving end Pr
Output from. Further, the left data transmission circuit 7b is
The shift register 3 operates in an output mode M4 in which the shift register 3 is shifted to the left.
The left shift output data D6 to D4 are superimposed on the clock pulse cp applied to the left transmitting/receiving end Pl and outputted from the left transmitting/receiving end Pl. The output terminal device 2B receives the data D1, D2, and D3 transmitted from the master station 1 in the output mode M2, and outputs parallel output from the shift register 6 in response to the output S4 of the second synchronization signal detection circuit 4b. is latched by a latch circuit 8 connected to output terminals P4, P5, and P6. Also, output mode M
4, input data signals D6, D5, D4 to the master station 1.
In the input terminal device 2A that transmits data D6, D5, D4 to be transmitted in response to the output S4 of the second synchronization signal detection circuit 4b, the input terminals P1, P
2, read from P3 as parallel inputs of the shift register 6. On the other hand, in master station 1, output mode M
4, the clock pulse output by its master station 1
It is configured to discriminate and extract data signals D6 to D1 superimposed on cp from the terminal devices 2A and 2B. Here, as described above, the data signals D1 to D6 transmitted back and forth between the master station 1 and the terminal devices 2A and 2B include the output data signals D1 and D6 transmitted from the master station 1 to the output terminal device 2B. D2, D3, and input data signals D6, D5, D4 transmitted from the input terminal device 2A to the master station 1. Therefore, for example, in the illustrated embodiment, the output data signals D1, D2, and D3 are superimposed on the first three clock pulses cp of the six clock pulses output from the master station 1 in the output mode M2. Input data signals D6, D5, and D4 are superimposed on the first three clock pulses cp of the six clock pulses output from the master station 1 in the output mode M4. What should be noted here is that the movement directions (shift directions) of the input/output data signals D1 to D6 are opposite to each other in the output mode M2 and the output mode M4. That is, the output data D6 superimposed on the last clock pulse cp in output mode M2 is superimposed on the first clock pulse cp in output mode M2. The output order of the clock pulse cp output from the master station 1 is determined by the input/output terminals P1 to P6 of the input/output terminal devices 2A and 2B.
It has meaning as a type of address information that specifies the address. In the illustrated embodiment, the clock pulses cp output from the master station 1 are provided with auxiliary codes cp1, cp2, cp for identifying the output order.
3, cp4, cp5, and cp6, in output mode M2, clock pulses cp1 to cp6 and input/output terminals P1 to P1 have the relationship shown in Table 1 below.
P6 corresponds.

[Table] Therefore, in output mode M2, output terminal device 2
In order to provide output data signals D1, D2, and D3 to the output terminals P6, P5, and P4 of B, the aforementioned "HH" or "HL" signal is superimposed on the first three clock pulses cp1, cp2, and cp3. In output mode M4, clock pulses cp1 to cp6 correspond to input/output terminals P1 to P6 in the relationship shown in Table 2 below.

[Table] In other words, in output mode M4, input terminal device 2
The input data signals D6, D5, and D4 of the input terminals P1, P2, and P3 of A are the first three clock pulses.
It is superimposed on cp1, cp2, and cp3. Therefore,
These three clock pulses cp1, cp2, cp3
The data signals D6, D5, D4 superimposed on the
Just extract it. Here, if the input/output data signals D1 to D6 are all "L" as shown in FIG. 2a, for example,
The amplitude voltages of each of the clock pulses cp1 to cp6 are all "HL", that is, the amplitude is "H" without being superimposed. However, for example, if "H" output data signals D1, D3 are given to the output terminals P6, P4, or "H" input data signal D5 is given to the input terminal P2.
(The remaining data signals D2, D4, and D6 are set to "L"), as shown in Fig. 2b.
As shown in , first, in the output mode M2, the signals D1 and D3 are superimposed on the first and third clock pulses cp1 and cp3, and only the first and third clock pulses cp1 and cp3 become "HH". (Other clock pulses cp2, cp
4, cp5, and cp6 are output as they are at the "HL" level. ). Next, in output mode M4, as shown in FIG. 2b, master station 1 receives the second clock pulse.
When cp2 is output, the level of this second clock pulse cp2 becomes "HH". At this time, the first and third clock pulses cp1 and cp corresponding to the other input signals D6 and D4 (nothing is "L")
3 remains “HL”. This is then discriminated and extracted on the master station 1 side. What should be noted here is that the transmission and reception of the data signals D1 to D6 by the master station 1 to the input/output terminals P1 to P6 of the terminal devices 2A and 2B is carried out only through the transmission line l, which has only a single signal transmission capacity. can be carried out on a single transmission line
This means that it is sufficient to connect only one end (left end) to the master station 1 side. And each terminal device 2
In A and 2B as well, the main component is a shift register 6 having a shift capacity corresponding to each input terminal or output terminal.
Furthermore, the capacitance of this register 6 can be reduced in accordance with the number of terminals, and if the number of terminals is only one, it is of course only necessary to have a shift capacitance of one bit. As a result, a necessary and sufficient data transmission system can be obtained with a simple and streamlined configuration that best suits the number of input/output terminals, without requiring an unnecessarily sophisticated and expensive system configuration. Furthermore, in addition to the advantage that the above-mentioned transmission line 1 only needs to have a single transmission capacity, only one end (the left end) needs to be connected to the master station 1 side, which further simplifies the wiring work. Furthermore, it is convenient that it is possible to easily add a terminal device to the other end (right end). Now, to explain the system shown in FIG. 1 in more detail, first, the master station 1 is
A transmission shift register 9a for sending out output data signals D1, D2, D3 in a predetermined order to the output terminal device 2B, and input data signals D6, D5, D sent out from the input terminal device 2A.
4 and a reception shift register 9b for guiding the signal to a predetermined input terminal row. Each register 9a,
Each of the bits 9b has a shift capacity of 6 bits, and is driven to shift in synchronization with the clock pulse CP. The shift output of the transmission shift register 9a is synchronized with the clock pulse cp by the AND gate 10, and then superimposed on the transmission and reception end Pm by the first driver 11a having an output amplitude of "HH". be done. This transmitting/receiving end Pm receives the clock pulse cp by a second driver 11b having an output amplitude of "HL", that is, "H".
is now being output. Therefore, the output end
From Pm, output data signals D1, D2,
D3 will now be output. Further, although not shown, the first and second synchronization signals S1 and S2 are outputted via the second driver 11b.
In addition, the input data signals D6, D5, D4 sent to the transmitting/receiving end Pm are the clock pulses mentioned above.
“HH” level comparator having a reference voltage Vh (“HL”<Vh<“HH”) higher than the amplitude voltage “H” or “HL” of cp and lower than the amplitude voltage “HH” of the superimposed data signal The signal is discriminated and extracted by C1, shifted into the receiving shift register 9b, and further shifted in parallel to the latch circuit 9c. Next, regarding the terminal devices 2A and 2B, the relay transmitting circuit 3 is set to an intermediate level between "H" and "L" amplitude levels of the clock pulse CP and the first and second synchronizing signals S1, S2, etc. reference voltage
The comparison output of the "H" level comparator C2 having Vl is converted into a normal driver 1 having an "H" output level.
3 to be relayed. Comparator C2
The comparison input of is connected to the left transmitting/receiving end Pl, and the output of the driver 13 is connected to the right transmitting/receiving end Pr. Further, the first and second synchronization signal detection circuits 4
Each of a and 4b is a so-called on-delay timer. Here, if the input of the first synchronization signal detection circuit 4a is in negative logic and the input state remains at "L" level for a certain period of time or more, a detection output S3 as shown in FIG. 2d is generated. . The input of the second synchronizing signal detection circuit 4b is of positive logic, and when the input state remains at the "H" level for a certain period of time or more, a detection output S4 as shown in FIG. 2e is generated. Both detection circuits 4a,
Both inputs of 4b are the "H" level comparator C2.
Obtained from the comparison output of . "HH" level comparators C1, C1 having the reference voltage of Vh are used in the left and right data discrimination circuits 5a, 5b. This comparator C1,
C1 Each input side is the left transmitting/receiving end Pl and the right transmitting/receiving end Pr
are connected to each. Further, its output becomes a right shift input and a left shift input of the bidirectional shift register 6. The bidirectional shift register 6 includes terminal devices 2A, 2
B's respective input or output terminals P1, P
It has a shift capacity corresponding to the number of P2, P3 or P4, P5, and P6. If there is only one terminal, a 1-bit shift capacitor may be sufficient. This double-sided shift register 6 has the above-mentioned detection output S as shown in FIG. 2f.
The shift direction is controlled by the set output state of the RS flip-flop 14, which is set by the output signal S3 and reset by the detection output S4.
In the embodiment, when the set output is "H", the shift is to the right, and when the set output is "L", the shift is to the left. The shift clock of register 6 receives the clock pulse cp from the "H" level comparator C2.
However, in order to ensure more reliable reading of the data signal, it is slightly delayed by the delay circuit 15 before being used as a shift clock. The right data transmitting circuit 7a and the left data transmitting circuit 7b each include a driver having an output amplitude of "HH". Each of these drivers synchronizes the right shift output or left shift output of the shift register 6 with the clock pulse cp by an AND gate 10 and outputs "HH".
Alternatively, output at the “HL” level and
It is applied to Pl or the right transmitting/receiving end Pr and superimposed on the clock pulse cp. In addition, each transmitting circuit 7
a and 7b are controlled by the set output state of the RS flip-flop 14, and when the register 6 is being driven to shift to the right, the right data transmitting circuit 7a
When the left data transmitting circuit 7b is shifted to the left, only the left data transmitting circuit 7b is activated and performs a transmitting operation. As explained in detail above, the serial data transmission system according to the present invention uses a bidirectional shift register, and transmits data signals by superimposing them on clock pulses. This makes the signal transmission between input/output devices and central equipment in control systems using programmable logic controllers, etc., more sophisticated than necessary. Moreover, it can be carried out using an optimal and simple system according to the needs, without using an expensive system. Furthermore, for data transmission, only one end of a single transmission line needs to be connected to the master station for both sending and receiving, which further simplifies wiring and allows for easy expansion by adding terminal equipment to the other end. be able to.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the system according to the present invention, and FIG. 2 is a timing chart showing an example of its operation. 1... Master station, 2A... Input terminal device, 2B...
Output terminal device, 3... Relay transmitting circuit, 4a...
First synchronization signal detection circuit, 4b...Second synchronization signal detection circuit, 5a...Left data discrimination circuit, 5b
...Right data discrimination circuit, 6...Bidirectional shift register, 7a...Right data transmission circuit, 7b...Left data transmission circuit, 8...Latch circuit, l...Signal line, Pm...Transmission/reception end, Pl……Left transmitting/receiving end,
Pr...Right transmitting/receiving end, P1, P2, P3...Input terminal, P4, P5, P6...Output terminal, M1~M
4...Output mode, cp...Clock pulse, D
1 to D6...input/output data, S1...first synchronization signal, S2...second synchronization signal.

Claims (1)

[Claims] 1. The master station transmits the following output mode M at one transmitting/receiving end.
Output operation is performed in order with 1, M2, M3, and M4 as one cycle; Output mode M1... Outputs the first synchronization signal in which the output state at a specific level continues for a certain period of time that is sufficiently larger than the period of the clock pulse shown below. Output mode M2... Set the amplitude voltage of each pulse to high or low.
Outputs a predetermined number of clock pulses made by superimposing the data signal to be transmitted by changing the value; Output mode M3...An output state of a specific level different from the output mode M1 is set sufficiently larger than the period of the clock pulse. Outputs a second synchronization signal that is continuous for a certain period of time; Output mode M4... Outputs a predetermined number of clock pulses with a certain amplitude; The terminal device; Receives a signal from the master station side that is applied to the left transmitting and receiving end. A first synchronization signal in output mode M1, a clock pulse with a constant amplitude obtained by removing the data signal component from a clock pulse on which a data signal is superimposed in output mode M2, and a second synchronization signal in output mode M3. and output mode M
a clock pulse and synchronization signal relay transmitting circuit that outputs the clock pulse in step 4 from the right transmitting/receiving end to a subsequent terminal device connected in series thereto; First and second synchronizing signal detection circuits for detecting; left and right data discrimination circuits for receiving clock pulses on which data signals are superimposed and applied to the left transmitting/receiving end and the right transmitting/receiving end, and discriminating and extracting the data signals; ; In response to the output of the first synchronization signal detection circuit, the mode is switched to the right shift mode, and the second synchronization signal detection circuit is switched to the right shift mode;
The clock pulse applied to the left transmitting/receiving end is used as the shift clock in output modes M2 and M4, and the data signal output from the left data discrimination circuit is shifted to the left shift mode in response to the output of the synchronization signal detection circuit. input, a bidirectional shift register whose left shift input is the data signal output from the right data discrimination circuit; the shift register operates in an output mode M2 in which the shift register is shifted right, and the right shift output data of the shift register is shifted to the right; A right data transmitting circuit that superimposes the clock pulse output from the relay transmitting circuit and outputs it from the right transmitting/receiving end; The shift register operates in output mode M4 in which the shift register is shifted to the left, and the left-shifted output data of the shift register is A left data transmitting circuit that outputs data from the left transmitting and receiving end so as to be superimposed on a clock pulse applied to the left transmitting and receiving end; In a terminal device that receives data transmitted from the master station in output mode M2, the second The parallel output of the shift register is latched in a latch circuit in response to the output of the synchronization signal detection circuit; in a terminal device transmitting data to the master station in output mode M4, the output of the second synchronization signal detection circuit is The data to be transmitted in response is read as parallel inputs of the shift register; the master station discriminates and extracts the data signal superimposed from the terminal device side on the clock pulse output by the master station in output mode M4; A serial data transmission system consisting of: