JPS6244820B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to field effect semiconductor devices, and more particularly to junction field effect transistors that can be implemented in integrated circuits using insulated gate field effect transistors.

Digital signal processing technology has progressed rapidly in recent years, but since many physical quantities and information that humans can perceive are analog quantities, analog circuits and analog-to-digital conversion circuits are required in the input/output part of signal processing. become. Digital signal processing circuits require a huge number of transistors, so
It is appropriate to realize this using a highly integrated insulated gate field effect semiconductor integrated circuit (hereinafter referred to as a MOS integrated circuit). On the other hand, analog circuits have hitherto been possible with bipolar integrated circuits. However, as a result of recent advances in MOS analog circuit technology, it has become possible to implement analog circuits using MOS integrated circuits. MOS that mixes analog and digital circuits on the same semiconductor chip
Integrated circuits are being put into practical use. however,
When realizing analog circuits with MOS devices,
There are many problems. One of them is the instability of the threshold voltage. Changes in threshold voltage over time reduce confidence in the accuracy of analog circuits. Furthermore, MOS transistors are generally susceptible to gate breakdown. This is disadvantageous for analog circuits in which the gate of a transistor is often directly connected to an external terminal. Furthermore, MOS transistors have extremely large 1/f noise and generally cannot handle low frequency signals on the order of microvolts.

It is an object of the present invention to provide a field effect semiconductor device which is free from the above-mentioned drawbacks. That is,
An object of the present invention is to provide a junction field effect transistor (hereinafter referred to as
The purpose of the present invention is to provide a field-effect semiconductor device in which a MOS integrated circuit (JFET) is built into a MOS integrated circuit.

A feature of the present invention is that a plurality of regions of opposite conductivity type are formed on one main surface of a semiconductor substrate of one conductivity type, and at least two adjacent regions of opposite conductivity type overlap each other in adjacent portions, and this overlapping In the field effect semiconductor device, one part is formed shallower than another part, and a high concentration impurity region of one conductivity type is formed in this overlapping part to a depth that does not reach the semiconductor substrate of one conductivity type. It is preferable that opposite conductivity type high concentration impurity regions are formed in two adjacent opposite conductivity type regions, and these regions are used as a source and drain, respectively, and one conductivity type high concentration impurity region is used as a gate. In other words, the features of the present invention are:
For example, in a complementary MOS integrated circuit, in order to realize a first conductivity type (n type) MOS transistor, a second conductivity type MOS transistor provided on one principal surface of a first conductivity type (n type) semiconductor substrate is used. A diffusion layer (P-well) is formed, a plurality of these diffusion layers are arranged at an interval narrower than twice the junction depth of those diffusion layers, and The diffusion layers of partially overlap each other due to lateral diffusion during indentation diffusion, and a junction shallower than the junction depth of these diffusion layers is formed in the overlapping region, and on this shallow junction, A first conductivity type high concentration diffusion layer (n ⁺ SD diffusion layer) shallower than this shallow junction is formed, and a second conductivity type At least two second conductivity type high concentration diffusion layers (P ⁺ SD diffusion layers) shallower than these second conductivity type diffusion layer junctions are formed in the diffusion layer (P well), and this A junction field effect transistor uses a first conductivity type high concentration diffusion layer (n ⁺ SD diffusion layer) as a gate and a second conductivity type high concentration diffusion layer (P ⁺ SD diffusion layer) as a source or drain.

An embodiment of the present invention will be described below with reference to the drawings. Since the present invention is particularly compatible with complementary MOS (hereinafter referred to as CMOS) processes, an example of implementing a JFET in a CMOS integrated circuit will be described below. There are various CMOS manufacturing processes, but here we will use a silicon gate process that creates a P-well on a standard n-type silicon substrate as an example.

FIG. 1 shows P formed on an n-type silicon substrate 1.
The JFET fabricated in well 2 is shown. Here, 3 and 5 are P ⁺ -type diffusion layers forming the source/drain regions of the P-channel MOS transistor, and 4 is an n ⁺ -type diffusion layer forming the source/drain regions of the N-channel MOS transistor. In order to operate as a JFET, the P ⁺ type diffusion layers 3 and 5 are used as the source and the drain, and the N ⁺ type diffusion layer 4 is used as the gate. The channel area is
This is the lower part 6 of the n ⁺ diffusion layer 4. Although the JFET having the structure shown in FIG. 1 can be realized without making any changes to the CMOS process, good electrical characteristics cannot be obtained. This is because the junction depth of the P well is large, on the order of several μm to 10 μm, and the depth of the n ⁺ diffusion layer is on the order of 0.5 μm to 1 μm, resulting in a large channel depth.

Therefore, in order to reduce the channel depth, P
Utilizes lateral diffusion in well-pushing diffusion. That is, a plurality of P-wells are placed close to each other and partially overlapped by lateral diffusion.
This situation is shown in FIG. Here, 7 is the diffusion window of the P-well. The two P-wells 2, 2' overlap at a portion 8 due to lateral diffusion. In the P-well overlap part 8, the P-well junction becomes shallower.
If this part is used as a JFET channel, a shallow channel depth can be achieved even if a deep P-well is used.

FIG. 3 shows the structure of a JFET realized using the principle shown in FIG. A gate region 11 is formed so that a portion 9 where the P wells 2 and 2' overlap becomes a channel region. The gate region 11 can be formed at the same time as the source and drain regions of the n-channel MOS transistor. The source and drain regions 10 and 12 of the JFET are P channel
It can be made at the same time as the source and drain regions of a MOS transistor. In this way, the JFET according to this embodiment can be fabricated in a CMOS LSI without adding anything to the normal CMOS process.

The channel depth in this embodiment is uniquely determined by the interval between the P-well diffusion windows 7 and 7' shown in FIG. 2 and the junction depth of the P-well. The spacing between the P-wells is determined by the accuracy of photolithography, and with today's technological level it is easy to achieve an accuracy of about +0.5 μm. Further, although P-well diffusion is performed by ion implantation and high-temperature indentation diffusion, the reproducibility of the junction depth is extremely good. Therefore,
Shallow channel depth can be achieved with good reproducibility.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view showing the structure of a conventional JFET, Fig. 2 is a cross-sectional view for explaining the manufacturing process of an embodiment of the present invention, and Fig. 3 is a cross-sectional view of a JFET according to an embodiment of the present invention. It is a diagram. In addition, in the figure, 1... n-type silicon substrate,
2, 2'...P well, 3...P ⁺ source (drain) region, 4...n ⁺ gate region, 5...P ⁺ drain (source) region, 6...channel region,
7, 7'...P-well diffusion window, 8...P-well overlapping portion, 9...shallow channel region, 10
...P ⁺ source (drain) region, 11 ... n ⁺ gate region, 12 ... P ⁺ drain (source) region.

Claims (1)

[Claims] 1. A first insulated gate transistor having a channel region of an opposite conductivity type is formed on one main surface of a semiconductor substrate of one conductivity type, and a plurality of opposite conductivity types having the same depth are formed on the one main surface of the semiconductor substrate. a second insulated gate transistor having a channel region of one conductivity type is formed in a predetermined one of the opposite conductivity type regions, and the other two of the opposite conductivity type regions are adjacent to each other. , the adjacent portions overlap, the overlapping portion is formed shallower than the other portions, and a high concentration impurity region of one conductivity type is formed in the overlapping portion to a depth that does not reach the semiconductor substrate of the one conductivity type. A field effect semiconductor device characterized in that the two regions of opposite conductivity type and the high concentration impurity region of one conductivity type constitute a junction transistor.