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JPS6244837B2 - - Google Patents
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JPS6244837B2 - - Google Patents

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Publication number
JPS6244837B2
JPS6244837B2 JP56004495A JP449581A JPS6244837B2 JP S6244837 B2 JPS6244837 B2 JP S6244837B2 JP 56004495 A JP56004495 A JP 56004495A JP 449581 A JP449581 A JP 449581A JP S6244837 B2 JPS6244837 B2 JP S6244837B2
Authority
JP
Japan
Prior art keywords
layer
film
electrode
gap
tin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56004495A
Other languages
Japanese (ja)
Other versions
JPS57117284A (en
Inventor
Katsumi Tsujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP449581A priority Critical patent/JPS57117284A/en
Priority to NLAANVRAGE8200038,A priority patent/NL186354C/en
Priority to DE19823200788 priority patent/DE3200788A1/en
Publication of JPS57117284A publication Critical patent/JPS57117284A/en
Priority to US06/681,710 priority patent/US4553154A/en
Publication of JPS6244837B2 publication Critical patent/JPS6244837B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/83Electrodes
    • H10H20/832Electrodes characterised by their material
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/019Manufacture or treatment of bond pads
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/81Bodies
    • H10H20/822Materials of the light-emitting regions
    • H10H20/824Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/83Electrodes
    • H10H20/831Electrodes characterised by their shape
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/59Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/931Shapes of bond pads
    • H10W72/934Cross-sectional shape, i.e. in side view

Landscapes

  • Led Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Led Device Packages (AREA)

Description

【発明の詳細な説明】 本発明は、−族化合物半導体装置、特に
GaP、GaAs、GaAs1-xPx等のGa化合物半導体の
単結晶を用いた発光ダイオード(以下、LEDと
略記)における電極の構造に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to - group compound semiconductor devices, particularly
This article relates to the structure of electrodes in light emitting diodes (hereinafter abbreviated as LEDs) using single crystal Ga compound semiconductors such as GaP, GaAs, and GaAs 1-x Px.

従来、LEDは可視光を発光するものとしてGaP
或いはGaAs1-xPxの結晶を用いたものが実用化さ
れており、各種のパイロツトランプや数字表示素
子として一般に広く使用されている。又、赤外光
の発光を目的とするものとしてGaAsの結晶を用
いたものがリモートコントロールや、ソリツド、
ステートリレー等に使用されている。このような
Ga化合物半導体のLEDの中で大きなウエイトを
占めているGaPLED(赤色から緑色まで種々の発
光色を得る事が可能)について以下説明を行な
う。
Conventionally, LEDs emit visible light using GaP.
Alternatively, devices using GaAs 1-x Px crystals have been put into practical use and are generally widely used in various pilot lamps and numeric display elements. In addition, devices using GaAs crystal for the purpose of emitting infrared light are used for remote control, solid,
Used in state relays, etc. like this
GaPLEDs (capable of emitting light of various colors from red to green), which account for a large portion of Ga compound semiconductor LEDs, will be explained below.

このGaPLEDの従来の製造方法を第1図を用い
て説明する。
The conventional manufacturing method of this GaPLED will be explained using FIG.

次に製造工程順に説明する。 Next, the manufacturing process will be explained in order.

LEC法により得られたn型GaPウエハー1上
に液相エピタキシヤル法により、n型GaP層2
及びP型GaP層3を結晶成長させる…第1図
a。
On the n-type GaP wafer 1 obtained by the LEC method, an n-type GaP layer 2 is formed by the liquid phase epitaxial method.
and crystal growth of the P-type GaP layer 3...FIG. 1a.

次に上記結晶成長面(P型層面)及びn型ウ
エハー面(裏面)を機械的に研磨し、ウエハー
を所定の厚みにする。
Next, the crystal growth surface (P-type layer surface) and the n-type wafer surface (back surface) are mechanically polished to give the wafer a predetermined thickness.

そしてP型成長層側の電極4としてAuとBe
の合金(以下、Au−Beと略記)或いはAuとZn
の合金(以下、Au−Znと略記)を、またn型
基板側の電極5としてAuとSiの合金(以下、
Au−Siと略記)或いはAuとGeの合金(以下、
Au−Geと略記)を真空蒸着する…第1図b。
Then, Au and Be are used as the electrode 4 on the P-type growth layer side.
alloy (hereinafter abbreviated as Au-Be) or Au and Zn
(hereinafter abbreviated as Au-Zn), and an alloy of Au and Si (hereinafter abbreviated as Au-Zn) as the electrode 5 on the n-type substrate side.
(abbreviated as Au-Si) or an alloy of Au and Ge (hereinafter referred to as
Au-Ge (abbreviated as Au-Ge) is vacuum deposited...Figure 1b.

その後、フオトエツチング法により、各々所
定の電極形状になすべく加工を行ない、更に
500℃〜600℃の熱処理を施して電極のオーム性
接触を形成する…第1図c。
After that, each electrode is processed into a predetermined shape using a photo-etching method, and then
Heat treatment at 500°C to 600°C to form ohmic contacts of the electrodes...Figure 1c.

そして次にダイシング法、或いはスクライビ
ング法により、ウエハーを所定の大きさのチツ
プに加工する…第1図d。
Then, the wafer is processed into chips of a predetermined size by a dicing method or a scribing method...FIG. 1d.

そしてこの様にして得られたLEDのチツプ
を第1図eの様に、Auペースト(或いはAgペ
ースト)6により、ステム7上に固定した後、
P側電極4とステムのポスト8とを、金細線9
で熱圧着法により結合する。そしてこのステム
の上部をエポキシ樹脂で被う事によりLEDの
ランプは完成する。
After fixing the LED chip thus obtained on the stem 7 with Au paste (or Ag paste) 6, as shown in Figure 1e,
Connect the P-side electrode 4 and the stem post 8 with a thin gold wire 9.
They are bonded by thermocompression bonding. The LED lamp is then completed by covering the top of this stem with epoxy resin.

ところで、この様な金細線9によるワイヤー・
ボンドが、良好に行なえるか否かは、P側電極4
の表面状態に大きく左右され、従来のAu系合金
電極を用いた場合では、良好なオーム性接触は得
られるものの、Zn、Be等のAuに添加されている
金属による影響、及び熱処理工程を経る際に起る
と考えられる半導体基板中のGaの電極層内への
拡散による影響などにより、金細線がうまく電極
表面へ熱圧着出来ず、良好なワイヤーボンデイン
グ性を得るのが困難であつた。そのため、従来
LEDの生産におけるワイヤーボンド工程の歩留
りは、満足するものが得られなかつた。
By the way, a wire made of such a thin gold wire 9
Whether or not bonding can be performed well depends on the P side electrode 4.
Although good ohmic contact can be obtained when using conventional Au-based alloy electrodes, it is affected by metals added to Au such as Zn and Be, and due to the heat treatment process. Due to the influence of diffusion of Ga in the semiconductor substrate into the electrode layer, which is thought to occur in the process, the thin gold wire could not be properly thermocompressed onto the electrode surface, making it difficult to obtain good wire bonding properties. Therefore, conventionally
The yield of wire bonding process in LED production was not satisfactory.

一方Si基板を用いた半導体素子の配線材料とし
て使用されているAlは、周知の通り、良好なワ
イヤー・ボンデイング性を有しているが、−
族化合物半導体、特に液相エピタキシヤル法によ
り成長させたGaPやGaAsの結晶の様な、不純物
濃度の低い半導体結晶に対しては、上記Au系合
金とは逆にオーム性接触を得るのが困難であり、
この様な半導体結晶にAlをオーム性電極として
用いることは、不可能であつた。
On the other hand, Al, which is used as a wiring material for semiconductor devices using Si substrates, has good wire bonding properties as is well known, but -
Contrary to the above-mentioned Au-based alloys, it is difficult to obtain ohmic contact with group compound semiconductors, especially semiconductor crystals with low impurity concentrations such as GaP and GaAs crystals grown by liquid phase epitaxial method. and
It has been impossible to use Al as an ohmic electrode in such semiconductor crystals.

これに対し、同出願人は特願昭53−149263号
(特開昭55−75276号公報)において、Agを主成
分とした合金層を第1層、Ti、Mo、W、または
Ti、Mo、Wと他の合金からなる高融点金属(バ
リア層として働く)を第2層、Al層を第3層と
する電極構造を提案した。上記電極構造により、
一応、Alによる良好なワイヤー・ボンデイング
性が得られた。
On the other hand, in Japanese Patent Application No. 53-149263 (Japanese Unexamined Patent Publication No. 55-75276), the same applicant proposed that the first layer is an alloy layer mainly composed of Ag, Ti, Mo, W, or
We proposed an electrode structure in which the second layer is a high-melting point metal made of Ti, Mo, W, and other alloys (which acts as a barrier layer), and the third layer is an Al layer. With the above electrode structure,
For the time being, good wire bonding properties were obtained with Al.

しかし、第1層にAgを主成分とした合金を用
いた場合は、抵触抵抗が高くそしてその順方向電
圧がいく分高い側で広範囲にバラツク欠点があつ
た。
However, when an alloy containing Ag as the main component was used for the first layer, the contact resistance was high and the forward voltage varied widely on the somewhat high side.

本発明は、以上の従来欠点に鑑みなされたもの
であり、−族化合物半導体のP側電極とし
て、Au系合金を含む多層構造を持つ電極を形成
する事により結晶基板とは接触抵抗が低く、良好
なオーム性接触を持ち、かつ良好なワイヤー・ボ
ンデイング性を持つ電極を備えた半導体装置を提
供することを目的とするものである。
The present invention has been made in view of the above conventional drawbacks, and by forming an electrode with a multilayer structure containing an Au-based alloy as the P-side electrode of a - group compound semiconductor, the contact resistance with the crystal substrate is low. It is an object of the present invention to provide a semiconductor device having an electrode having good ohmic contact and good wire bonding properties.

即ち、結晶基板とオーム性接触を形成するため
の電極としてAu−Be、或いはAu−Znの層を設
け、更に良好なワイヤー・ボンデイング性を得る
ための電極の表面層としてAl層を設けるもので
あつて、更に前記2者の相互拡散を防ぐためのバ
リア層として両者の中間に窒化チタニウム
(TiN)とチタニウム(Ti)の2層を設ける事に
より上記目的を実現したものである。
That is, an Au-Be or Au-Zn layer is provided as an electrode to form ohmic contact with the crystal substrate, and an Al layer is provided as a surface layer of the electrode to obtain better wire bonding properties. Furthermore, the above object is achieved by providing two layers of titanium nitride (TiN) and titanium (Ti) between the two as a barrier layer to prevent mutual diffusion of the two.

以下本発明に係わる一実施例について説明す
る。
An embodiment of the present invention will be described below.

実施例 GaPLEDに本発明を適用した実施例について、
第2図によつて説明を行なう。
Example Regarding an example in which the present invention is applied to GaPLED,
The explanation will be given with reference to FIG.

LEC法により得られたn型GaP基板10に、液
相エピタキシヤル法により、n型GaP11及びp
型GaP12を成長し、p−n接合13を形成す
る。次に、このGaPウエハーの両面をラツピング
及びポリツシングして所定の厚みに加工した後、
n側電極として裏面にAu−Si18を真空蒸着す
る。そしてフオト・エツチング法により、このn
側電極を所定の形状にエツチングし、窒素雰囲気
中で500〜600℃の熱処理を施す事により、オーム
性接触を形成する。次にこのGaPウエハーのP層
表面に真空蒸着法により、重量パーセントで0.2
〜1.0%のBeを含むAu−Be膜14を500〜5000Å
の膜厚に堆積する。さらに続けて、スパツタリン
グ法により、TiN膜15、Ti膜16及びAl膜17
を順次堆積させる。膜厚は、TiN膜が500〜2000
Å、Ti膜が1000〜4000Å、Al膜が0.8〜2.0μmで
ある。ここでTiN膜15はTiのターゲツトを窒素
ガス雰囲気中でリアクテイブスパツタする事によ
り得られるので、1つのTiターゲツトを窒素ガ
ス及びアルゴンガスでスパツタリングする事で
TiN及びTiは連続して堆積出来る。
On the n-type GaP substrate 10 obtained by the LEC method, n-type GaP 11 and p
A type GaP 12 is grown to form a pn junction 13. Next, after processing both sides of this GaP wafer to a predetermined thickness by wrapping and polishing,
Au--Si 18 is vacuum-deposited on the back surface as an n-side electrode. Then, by photo-etching, this n
The side electrodes are etched into a predetermined shape and heat treated at 500 to 600°C in a nitrogen atmosphere to form ohmic contact. Next, the P layer surface of this GaP wafer was coated with 0.2% by weight by vacuum evaporation method.
Au-Be film 14 containing ~1.0% Be with a thickness of 500 to 5000 Å
Deposits to a film thickness of . Furthermore, by sputtering, TiN film 15, Ti film 16 and Al film 17 are
are deposited sequentially. The film thickness is 500 to 2000 for TiN film.
Å, the Ti film is 1000 to 4000 Å, and the Al film is 0.8 to 2.0 μm. Here, the TiN film 15 is obtained by reactive sputtering of a Ti target in a nitrogen gas atmosphere, so one Ti target can be sputtered with nitrogen gas and argon gas.
TiN and Ti can be deposited sequentially.

次に、この様にして積層した4層膜をフオト・
エツチング法により所定の形状に加工するが、こ
の際Al膜のエツチングは80〜90℃に加熱したリ
ン酸(H3PO4)で、TiN膜及びTi膜はアンモニア
水(NH4OH)と過酸化水素水(H2O2)の混合液
で、そしてAu−Be膜はヨウ素(I2)とヨウ化アン
モニウム(NH4I)の混合液で容易にエツチング
出来る。
Next, the four-layer film laminated in this way was photographed.
It is processed into a predetermined shape using an etching method. At this time, the Al film is etched with phosphoric acid (H 3 PO 4 ) heated to 80-90°C, and the TiN film and Ti film are etched with aqueous ammonia (NH 4 OH). The Au-Be film can be easily etched with a mixture of hydrogen oxide (H 2 O 2 ), and the Au-Be film can be etched with a mixture of iodine (I 2 ) and ammonium iodide (NH 4 I).

次にこのGaPウエハーを窒素雰囲気中で420〜
500℃の熱処理を施こす事により、オーム性接触
を形成する。
Next, this GaP wafer was heated at 420°C in a nitrogen atmosphere.
Ohmic contact is formed by heat treatment at 500℃.

この様にして得られたGaPウエハーは第1図に
示した従来のGaPウエハーと同様にダイシング或
いはスクライブにより所定の大きさに加工され、
ステムにマウントされてLEDランプとなる。以
上のGaPLEDの製造過程におけるワイヤー・ボン
デイング工程において、従来のAu−Beを用いた
電極に比べて飛躍的な向上が見られ、ワイヤー・
ボンデイング工程の歩留りが大巾に向上した。ま
たGaP基板との接触抵抗は、従来のAu−Beを用
いた電極と何ら変わりなく良好であり、長時間の
通電に対しても安定であつた。そしてこの様に上
記電極が優れた特性を示すのは、中間層として設
けているTiN膜及びTi膜がオーム性接触を得るた
めの熱処理の際に生じるAu、BeやGaP基板中の
Gaの電極表面への拡散を阻止するバリアとして
働き、表面のAl膜への不純物の混入が生じない
と共に、良好なオーム性接触を得るに必要なGaP
とAu−Beとの合金化が安定して行なわれるため
である。なお、バリア層としてTiN或いはTiを単
独で用いた場合には、その働きは不充分であり、
オーム性接触を得るための熱処理後、Au−Beと
Alとの反応が見られる。
The GaP wafer thus obtained is processed into a predetermined size by dicing or scribing in the same way as the conventional GaP wafer shown in FIG.
It is mounted on a stem and becomes an LED lamp. The wire bonding process in the GaPLED manufacturing process described above has been dramatically improved compared to the conventional Au-Be electrode.
The yield of the bonding process has been greatly improved. In addition, the contact resistance with the GaP substrate was as good as that of conventional electrodes using Au-Be, and it was stable even when energized for a long time. The reason why the above electrode exhibits such excellent properties is that the TiN film and Ti film provided as the intermediate layer are free from Au, Be, and GaP substrates that are generated during heat treatment to obtain ohmic contact.
GaP acts as a barrier to prevent Ga from diffusing to the electrode surface, prevents impurities from entering the Al film on the surface, and is necessary to obtain good ohmic contact.
This is because alloying with Au-Be is performed stably. Note that when TiN or Ti is used alone as a barrier layer, its function is insufficient;
After heat treatment to obtain ohmic contact, Au−Be and
A reaction with Al can be seen.

すなわち、Au系合金を用いた場合、良好なオ
ーム性接着を得るには、少なくとも420℃以上の
熱処理を施こすことが必要である。しかし、Ti
等の単一の高融点金属はAu系合金に対しては反
応が生じ易く、例えばTiはAu系合金に対しては
370〜380℃以上の温度で反応を起し、そのバリア
性を破壊してAu系合金とAlを反応させてしま
う。つまり、Au系合金で良好なオーム接触が得
られる温度では、Au系合金中へAlが拡散し、結
果として良好なオーム性接触が得られなくなる。
That is, when using an Au-based alloy, it is necessary to perform heat treatment at at least 420° C. or higher in order to obtain good ohmic adhesion. However, Ti
Single high-melting point metals such as Ti tend to react with Au-based alloys; for example, Ti tends to react with Au-based alloys.
A reaction occurs at temperatures above 370-380°C, destroying its barrier properties and causing the Au-based alloy to react with Al. In other words, at a temperature at which good ohmic contact can be obtained with the Au-based alloy, Al diffuses into the Au-based alloy, and as a result, good ohmic contact cannot be obtained.

同出願人が先に提案した特願昭53−149263号
は、Ag系合金と高融点金属との特殊性に着目し
たもので、Ag系合金では、Ag系合金で良好なオ
ーム性接触を得る温度でも、Ti等の単一の高融
点金属との反応がなく、単一層でもバリア層とし
て有効に働く。しかしながら前述したとおり、こ
の電極構造では、順方向電圧が高くバラツキも大
きい。
The patent application No. 53-149263, which was previously proposed by the same applicant, focused on the special characteristics of Ag-based alloys and high-melting point metals. Even at high temperatures, it does not react with a single high-melting point metal such as Ti, and even a single layer works effectively as a barrier layer. However, as described above, this electrode structure has a high forward voltage and large variations.

一方、TiNは導電性を有し化学的に非常に安定
した化合物である。このTiNは、Au系合金で良
好なオーム性接触が得られる温度に耐え、バリア
層として働かせることが可能である。ところが、
TiN膜を単一層でバリア層として有効に働かせる
には、膜厚を4000〜5000Å以上と非常に厚くする
必要がある。しかし実験によれば、膜厚を厚くす
ることによつて、Au系合金とTiN膜間の機械的
接着強度が低下し、ワイヤー・ボンデイングの際
に電極が剥離する現象が生じバリア層として使用
できなかつた。またTiN膜をリアクテイブスパツ
タ法により形成する場合は生成速度が遅く、TiN
層単独で充分なバリア性を有するだけの膜厚を得
るのが非常に困難であつた。
On the other hand, TiN is an electrically conductive and chemically very stable compound. This TiN can withstand temperatures at which good ohmic contact is achieved with Au-based alloys and can act as a barrier layer. However,
In order for a single TiN film to function effectively as a barrier layer, the film must be extremely thick, at 4000 to 5000 Å or more. However, experiments have shown that increasing the film thickness reduces the mechanical adhesion strength between the Au-based alloy and the TiN film, causing the electrode to peel off during wire bonding, making it unsuitable for use as a barrier layer. Nakatsuta. In addition, when forming a TiN film by the reactive sputtering method, the formation rate is slow, and the TiN
It has been extremely difficult to obtain a film thickness sufficient to provide sufficient barrier properties as a single layer.

TiN膜(例えば500〜2000Å)の上にTi膜(例
えば1000〜4000Å)を積層形成したのは上記諸点
によるもので、第1層としてAu系合金を用いた
場合にあつて、バリア性として最も安定した層が
得られた。
The reason why a Ti film (for example, 1000 to 4000 Å) was layered on top of a TiN film (for example, 500 to 2000 Å) was based on the above points. A stable layer was obtained.

なお、第2層にTi膜、第3層にTiN膜を形成す
ると、Ti膜とAu系合金との間で反応が起り、ま
たその上のTiN膜の膜厚が薄いので、結局Au系
合金中へAlが拡散し良好なオーム性接触は得ら
れない。
Note that when a Ti film is formed as the second layer and a TiN film is formed as the third layer, a reaction occurs between the Ti film and the Au-based alloy, and since the thickness of the TiN film on top of the Ti film is thin, the Au-based alloy eventually Al diffuses inside and good ohmic contact cannot be obtained.

第3図に本発明による電極構造と特願昭53−
149263号による電極構造の特性比較を示してお
く。横軸は順方向電圧、縦軸は個数である。本発
明においては、その接触抵抗が小さくかつバラツ
キも少なく、従つて、順方向電圧の低いものがバ
ラツキなく安定して得られることが明らかであ
る。
Figure 3 shows the electrode structure according to the present invention and the patent application filed in 1983.
A comparison of the characteristics of the electrode structure according to No. 149263 is shown below. The horizontal axis is the forward voltage, and the vertical axis is the number. In the present invention, it is clear that the contact resistance is small and has little variation, so that a low forward voltage can be stably obtained without variation.

以上のような実施例では、Au−Beを真空蒸着
で堆積したが、これをスパツタリング法等で行な
つてもよく、またTiN、Ti、Alを本実施例では、
スパツタリングにより堆積したが、これを真空蒸
着で堆積してもよい。
In the above examples, Au-Be was deposited by vacuum evaporation, but this may also be done by sputtering, etc. In this example, TiN, Ti, and Al were deposited by
Although it was deposited by sputtering, it may also be deposited by vacuum evaporation.

なお、上記実施例の電極構造は、GaPばかりで
なく、GaAs、GaAsP、GaAlAs等の他の−
族化合物半導体の電極構造としても適用出来る。
Note that the electrode structure in the above embodiments is applicable not only to GaP but also to other metals such as GaAs, GaAsP, and GaAlAs.
It can also be applied as an electrode structure for group compound semiconductors.

以上説明した如く本発明の半導体装置によれば
その電極は良好なワイヤーボンデイング性を有す
るとともに基板に対しオーム性接触を有すること
ができるものである。
As explained above, according to the semiconductor device of the present invention, the electrode has good wire bonding properties and can have ohmic contact with the substrate.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のGaPLEDの製造工程を示す説明
図、第2図は本発明に係るGaPLEDの側面断面図
である。また、第3図は特性比較図である。 図中、1……n型GaP基板、2……n型GaP
層、3……P型GaP層、4……Au−Be或いはAu
−Zn、5……Au−Si或いはAu−Ge、6……Au
ペースト或いはAgペースト、7……ステム、8
……ステムのポスト、9……金細線、10……n
型GaP基板、11……n型GaP層、12……P型
GaP層、13……p−n接合、14……Au−Be
層、15……TiN層、16……Ti層、17……Al
層、18……Au−Si層。
FIG. 1 is an explanatory diagram showing the manufacturing process of a conventional GaPLED, and FIG. 2 is a side sectional view of a GaPLED according to the present invention. Moreover, FIG. 3 is a characteristic comparison diagram. In the figure, 1... n-type GaP substrate, 2... n-type GaP
Layer 3...P-type GaP layer, 4...Au-Be or Au
-Zn, 5...Au-Si or Au-Ge, 6...Au
Paste or Ag paste, 7...Stem, 8
...Stem post, 9...Gold wire, 10...n
type GaP substrate, 11...n type GaP layer, 12...p type
GaP layer, 13...p-n junction, 14...Au-Be
layer, 15...TiN layer, 16...Ti layer, 17...Al
Layer, 18...Au-Si layer.

Claims (1)

【特許請求の範囲】[Claims] 1 P型化合物半導体とオーム性接触を成す、金
を主成分とした合金層を第1層、窒化チタニウム
層を第2層、チタニウム層を第3層、アルミニウ
ム層を第4層として順次積層して電極とした事を
特徴とする−族化合物半導体装置。
1 A first layer is an alloy layer mainly composed of gold, which makes ohmic contact with a P-type compound semiconductor, a second layer is a titanium nitride layer, a third layer is a titanium layer, and a fourth layer is an aluminum layer. - group compound semiconductor device, characterized in that a - group compound semiconductor device is used as an electrode.
JP449581A 1981-01-13 1981-01-13 3-5 group compound semiconductor device Granted JPS57117284A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP449581A JPS57117284A (en) 1981-01-13 1981-01-13 3-5 group compound semiconductor device
NLAANVRAGE8200038,A NL186354C (en) 1981-01-13 1982-01-07 SEMICONDUCTOR DEVICE COMPRISING III-V CONNECTIONS WITH A COMPOSITE ELECTRODE.
DE19823200788 DE3200788A1 (en) 1981-01-13 1982-01-13 ELECTRODE FOR SEMICONDUCTOR COMPONENTS
US06/681,710 US4553154A (en) 1981-01-13 1984-12-13 Light emitting diode electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP449581A JPS57117284A (en) 1981-01-13 1981-01-13 3-5 group compound semiconductor device

Publications (2)

Publication Number Publication Date
JPS57117284A JPS57117284A (en) 1982-07-21
JPS6244837B2 true JPS6244837B2 (en) 1987-09-22

Family

ID=11585648

Family Applications (1)

Application Number Title Priority Date Filing Date
JP449581A Granted JPS57117284A (en) 1981-01-13 1981-01-13 3-5 group compound semiconductor device

Country Status (1)

Country Link
JP (1) JPS57117284A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04109674A (en) * 1990-08-29 1992-04-10 Victor Co Of Japan Ltd Compound semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6034827B2 (en) * 1977-06-28 1985-08-10 株式会社東芝 Gallium phosphide light emitting device
JPS5575270A (en) * 1978-12-02 1980-06-06 Semiconductor Res Found Static induction transistor
JPS5575276A (en) * 1978-12-02 1980-06-06 Sharp Corp 3[5 group compound semiconductor device

Also Published As

Publication number Publication date
JPS57117284A (en) 1982-07-21

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