JPS6246882B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a scan type programmable controller provided with a shift register type memory.

[Conventional technology]

Conventionally, programmable controllers have been considered as a computer application, and the storage devices include randomly accessible core memory, wire memory, etc.
RAM/ROM has been used.

It is certain that the processing capacity of a programmable controller could be increased by dynamically changing the program execution order using a jump function or an interrupt function, assuming that the storage device is randomly accessible.

[Problem that the invention seeks to solve]

However, it should be noted that a programmable controller is a device that skillfully hides the complexity of computers and is intended to make them easier to understand on the surface, and that jump instructions can make programs difficult to understand and debug. For example, the above method is not purposeful.

In addition, core memory and wire memory used as random access memory are expensive, RAM is volatile, and ROM has disadvantages such as the difficulty of changing the memory contents.

SUMMARY OF THE INVENTION An object of the present invention is to provide a programmable controller that is easy to understand and economical, eliminating the above-mentioned drawbacks.

[Means for solving problems]

The present invention is characterized in that a shift register type storage device is used as a storage device, programs are executed in the order in which they are stored, and changes in programs and execution order can be made by replacing/inserting instructions.
This can be easily done with the erase function.

[Effect]

The present invention, which is a programmable controller with a shift register type memory, has the function of replacing, inserting, and erasing instructions in its storage device.

〔Example〕

This will be explained below using figures.

FIG. 1 is a block diagram of one embodiment of the present invention, in which a shift register type memory is used as the storage device.

In FIG. 1, 1 is a storage device for storing the program of the programmable controller;
is a processing device that decodes and executes instructions read from the storage device, 3 is an input/output device that the processing device 2 refers to when executing the instruction, and 4 ₁ to 4 _n are addresses of the input/output device 3 by the processing device 2. ₅₁ to _5o are data buses consisting of n signal lines for the processing device 2 to exchange data with the input/output device 3, and 6 is the processing device. Address bus 4 ₁ to 4 _n from 2 to input/output device 3
The contents of the address specified by data bus 5 ₁ ~
_5. Read command for commanding to output on
7 is a data bus 5 from the processing device 2 to the input/output device 3.
₁ to _5o are write commands for instructing to write the data output on the address buses ₄₁ to _4n to the addresses specified, ₁₀₁ to _10p are the q bits that constitute the storage device 1. ₁₁₁ to _11p are the outputs of the shift register type memories ₁₀₁ to _10p , ₁₁₁ is the 1st bit of the instruction code, ₁₁₂ is the 2nd bit of the instruction code, and so on. _p is an instruction signal corresponding to the p-th bit of the instruction code (one instruction consists of p bits), 20 is an instruction register for latching the instruction signals 11 ₁ to 11 _p given from the storage device 1, and 21 is an instruction decoder. 22 is a calculation unit that controls data arithmetic operations and logical operations; 23 ₁ to 23 _p are instruction codes given to the control unit 21 from the instruction register 20;
24 is a latch signal that provides timing for latching the instruction signals 11 ₁ to 11 _p to the instruction register; 25
is a pulse-like shift signal that provides timing for shifting the shift register type memories 10 ₁ to 10 _p by 1 bit.

Next, the operation of such a configuration will be explained.

The control unit 21 decodes the instruction temporarily stored in the instruction register 20, sets the address of the input device in addresses 4 ₁ to 4 _n according to the type of instruction, and outputs the read command 6.
The state of the input/output signal is output to the data bus 5 ₁ to 5 _o , the data output to the data bus 5 ₁ to 5 _o is read into the calculation unit 22 and calculated, and the calculation result of the calculation unit 22 is sent to the data bus 5 ₁ to 5
_o , sets the address of the input/output device on the address buses ₄₁ to _4n , and outputs a write command 7 to write the operation result to the input/output device.

Whether the above operation is executed with one instruction or multiple instructions is determined by the number p of constituent bits of the instruction and how the bits are used. Output.

The command register 20 has command signals 11 ₁ to 11 _p
The status of is stored, and instruction codes 23 ₁ to 23 _p are output.

Subsequently, the shift signal 25 is output, and the shift register memories 10 ₁ to 10 _p are shifted by 1 bit, and each bit of the instruction that has already been temporarily stored in the instruction register 20 is shifted to the input side of the corresponding shift register memory. The bits closest to each other are returned to, and a new command is outputted to the command signals 11 ₁ to 11 _p .

After the above operations are completed, the control unit 21 again starts executing the instructions temporarily stored in the instruction register 20.

When the shift register type memories 10 ₁ to 10 _p are composed of q bits, q instructions can be stored, and the program completes one cycle by executing q instructions.

The above embodiment is a shift register type memory 10 ₁
10 _p forms a part of the processing device 2, that is, is directly connected to the processing device 2 in this example, but it is also possible to connect to the processing device 2 via the data buses 5 ₁ to 5 _o .

A schematic diagram of the embodiment is shown in FIG. 2, and the names of each part are shown below.

12 connects the command signals 11 ₁ to 11 _p to the data bus 5
Gate for outputting to ₁ to 5 _o (tap, p≦
n), 13 is the address bus 4 ₁
~4 An address decoder that determines that the address specified by _n belongs to the storage device 1, 14 is a gate signal for opening and closing the gate 12, and the names of other parts are the same as in FIG. be.

In such a configuration, the _operation of executing an instruction is the same as that shown in _FIG . Outputs 6.

The decoder 13 detects that the contents of the address buses 4 ₁ to 4 _n match the addresses assigned to the storage devices, and outputs the gate signal 14 .

This causes the gate 12 to open and output the command signals 11 ₁ to 11 _p to the data buses 5 ₁ to 5 _o .

The control unit 21 outputs a latch signal 24 and temporarily stores the command signals output to the data buses 5 ₁ to 5 _o .

After that, the decoder 13 stops outputting the gate signal 14 and outputs the shift signal 25.
Shift registers 10 ₁ to 10 _p are shifted by 1 bit.

In this way, the control unit 21 can sequentially read and execute new instructions.

In the above example, it has been described that the shift signal for shifting the shift register type memories 10 ₁ to 10 _p by 1 bit is given sequentially by the control unit 21.
Since ₁ to 10 _p are generally shifted in synchronization with a clock signal, it is also possible to have the control section decode and execute instructions in synchronization with this clock signal.

However, either the clock cycle can be lengthened to complete the decoding and execution of one instruction within one clock cycle, or the intermediate results of an operation can be temporarily saved every clock cycle, and the operation can be restarted from the intermediate result after one scan. Some consideration is required.

Shift register type memory ₁₀₁ to _10p refers to a storage device whose contents appear one after another on the output side without being specified by the application side.
Non-volatile memory such as magnetic bubble memory, drum, disk, etc. is preferable, and charge-coupled memory (CCD) can be used if volatility is not a concern.

Further, as part of the input/output device 3, it is also possible to include a storage device 1 for storing intermediate results of calculations.

Next, shift register type memories 10 ₁ to 10 _p
A detailed block diagram of an embodiment of the storage content changing circuit is shown in FIG.

Each of 41 ₁ to 41 _p and 42 ₁ to 42 _p is a 1-bit shift register for shifting the corresponding bit in synchronization with a shift signal applied to the shift register type memories 10 ₁ to 10 _{p ;}
~43 _p is a flip-flop for temporarily storing the instruction code to be replaced or inserted, 44 ₁ ~44
_p , 45 ₁ ~ 45 _p , 46 ₁ ~ 46 _p , 47 ₁ ~ 4
7 _p is an AND gate, 48 ₁ to 48 _p are OR gates, 49 is a reset signal output from the program counter 50, 51 is a comparator, 52 is a switch for setting the replacement point, insertion point, and erasure point, 53. 54 and 55 are flip-flops that memorize requests for replacement, insertion, and deletion, respectively; 56 and 57 are output signals of the comparator 51; ``Greater signal'' turns on (ON) ・``Match signal'' turns on when equal, 58 and 59 are OR gates, 6
0 to 63 are AND gates, 64 to 72 are AND gates (○ indicates that the signal phase is inverted), and 73 to 75 are flip-flops (53 to 5
5, the S and R inputs operate on the differential of the rising edge), 76 to 78 are filters, and 79.
80 and 81 are replacement, insertion, and deletion request pushbuttons, 82 ₁ to 82 _p are shaping circuits, and 83 ₁ to 8
3 _p is a filter, 84 ₁ to 84 _p are setting push buttons,
85 ₁ to 85 _p are digital switches. In addition, 82 ₁ to 82 _p , 83 ₁ to 83 _p , 84 ₁ to 8
4 _p is provided corresponding to each of 43 ₁ to 43 _P , but only one set common to 43 ₁ to 43 _P may be sufficient.

FIGS. 4a to 4j are time charts of the operation of the storage content changing circuit shown in FIG. 3.

Fig. 4a shows the shift signal, Fig. 4b shows the contents of the program counter 50 with the minimum value O, maximum values q and r are intermediate count values, and Fig. 4c shows the output of the shift register type memories ₁₀₁ to _10p . where O is the order 0, r is the memory content of the order r, 0 is the memory value 0, Figure 4 d is the output of the shift registers 41 ₁ to 41 _p , Figure 4 e
are the outputs of the shift registers 42 ₁ to 42 _p , FIG. 4 f is the output of the flip-flops 43 ₁ to 43 _p , and represents the instruction code I. are the command signals 11 ₁ to 11 _p , and if there is no change in the memory contents, the order r
When replacing the instruction with instruction code I, the order r
This is a time chart when inserting instruction code I between and order r+1, erasing the instruction at order r and moving subsequent instructions to the front.

The operation of the configuration shown in FIG. 3 will now be described.

Shift register type memories 10 ₁ to 10 _p , shift registers 41 ₁ to 41 _p , and 42 1 to 42 _p constitute a series of shift registers, and each time a shift signal 25 is output, the shift register type memories 10 1 to 10 p, shift registers 41 ₁ to 41 p, and 42 1 to 42 p are shifted to the right by 1 bit, and the command signal is The outputted contents of 11 ₁ to 11 _p are read into shift register type memories 10 ₁ to 10 _p .

The program counter 50 counts the shift signals 25 and outputs a reset signal 49 when the count value exceeds the number of bits q of the shift register type memory.
Sets own count value to 0.

At the same time, shift registers 41 ₁ to 41 _p , 42
₁ to _42p are also reset by the reset signal 49.

Furthermore, if there is a request for replacement, insertion, or deletion, one of the flip-flops 53, 54, 55 is set, and if there is no request, all the flip-flops 53, 54, 55 are reset.

First, a case where there is no change request will be explained.
When the program counter 50 is reset to 0, the flip-flops 53, 54, and 55 have all been reset, so the output of the AND gate 63 is turned on, and only the AND gates ₄₅₁ to _45p are opened and the shift register ₄₁₁ is turned on. The outputs of ~ _41P pass through OR gates ₄₈₁ ~ _48P and become command signals ₁₁₁ ~ _11P . Thereafter, every time the shift signal 25 is issued, the shift register type memories 10 ₁ to 10
The contents of 10 _p are sequentially shifted into shift registers 41 ₁ to 41 _P.
, and become command signals 11 ₁ to 11 _P.
During this time, the contents of the program counter 50 are incremented by 1 and reset to 0 when it exceeds q. A time chart of the above operation is shown in FIG. 4g.

Next, a case will be described in which the contents of the shift register type memories 10 ₁ to 10 _P in order r are replaced with instruction codes given in advance to the flip-flops 43 ₁ to 43 _P.

At this time, it is assumed that the switch 52 is set to r+1.

When program counter 50 is reset to zero, flip-flop 53 is set.

Before the contents of the program counter 50 reach r+1, the AND gate 63 is on, and the AND gates 45 ₁ to 45 _P are open and the shift register 4
The outputs of 1 ₁ to 41 _p become command signals 11 ₁ to 11 _p .

When the contents of the program counter 50 match r+1, a match signal 57 is output from the comparator 51, the AND gate 61 is turned on, and the AND gate 63 is turned off.

Therefore, AND gates 47 ₁ -47 _p are opened, and the outputs of flip-flops 43 ₁ -43 _p become command signals 11 ₁ -11 _p .

When the contents of the program counter 50 exceed r+1, the AND gate 61 is turned off again, the AND gate 63 is turned on, and the shift registers 41 ₁ to 4
The output of 1 _p becomes command signals 11 ₁ to 11 _p .

A time chart of the above operation is shown in FIG. 4h.

Next, the order r+1 specified by the switch 52
A case will be described in which the contents given in advance to the flip-flops 43 ₁ to 43 _p are inserted, the contents after the order r+1 are shifted, and the final data is erased.

When program counter 50 is reset to zero, flip-flop 54 is reset.

Before the contents of the program counter 50 reach r+1, the AND gate 63 is on, and the AND gates 45 ₁ to 45 _p are open and the shift register 41
The outputs of ₁ to 41 _p become command signals 11 ₁ to 11 _p .

When the contents of the program counter 50 match r+1, a match signal 57 is outputted from the comparator 51, the AND gate 61 is turned on, and the AND gate 63 is turned off.

Therefore, AND gates 47 ₁ -47 _p are opened, and the outputs of flip-flops 43 ₁ -43 _p become command signals 11 ₁ -11 _p .

A time chart of the above operation is shown in FIG. 4i.

Next, a case will be described in which the contents of the order r+1 specified by the stitch 52 are deleted, the contents after the order r+1 are shifted, and 0 is inserted as the final data.

When program counter 50 is reset to zero, flip-flop 55 is set.

Before the contents of the program counter 50 reach r+1, the AND gate 63 is on, and the AND gates 45 ₁ to 45 _p are open and the shift register 4
The outputs of 1 ₁ to 41 _p become command signals 11 ₁ to 11 _p .

When the contents of the program counter 50 exceed r+1, the AND gate 62 is turned on and the AND gate 63 is turned off.

Therefore, the AND gates 46 ₁ to 46 _p are opened, and the outputs of the shift register memories 10 ₁ to 10 _p become command signals 11 ₁ to 11 _p .

The above time chart is shown in Figure 4j.

5a to 5d are flip-flops ₄₃₁
~43 This is a time chart showing the input/output status of _p .

Figure 5a shows digital switches ₈₅₁ to _85p.
A thick solid line indicates a setting change from off to on, a thin solid line indicates a setting _change from on to _off , and FIG. Figure c shows the shaping circuits 82 ₁ to 82 _p
Figure 5d shows the latch timing signal at the output of
represents the data latched at the outputs of the flip-flops ₄₃₁ to _43p , and the thick solid lines and thin solid lines correspond to those in FIG. 5a.

6a to 6g are flip-flops 53 to 6g.
55 is a time chart showing the status of input and output.

Fig. 6a shows pressing the request push button (“0” →
FIG. 6b shows a "coincidence signal" 57 that turns on when the comparator 51 is equal.
The waveform of FIG. 6c is for flip-flops 73 to 75.
The output waveform of FIG. 6d is the AND gate 66.6
9.72 output waveform, Figure 6e is AND gate 6
FIG. 6f shows the output waveforms of the AND gates 65, 68, and 71, and FIG. 6g shows the output waveforms of the flip-flops 53, 54, and 55.

In the embodiment of FIG.
The larger signal 56 and the match signal 57 are used as the output of the gate, but it is possible to switch the gate by using 2 of the 3 signals including the smaller signal, or by using all 3 signals. .

If the insertion and deletion functions described above were to be implemented using a random access type memory, the circuit would become complicated or extra time would be consumed for insertion and deletion.

〔Effect of the invention〕

Thus, as described above, according to the present invention, programs are executed only in the order in which they are stored, and even if the programs are changed, they can be rearranged to the order in which they are executed, so that the programs remain orderly. This invention is easy to understand, eliminates the need for jump instructions, improves memory usage efficiency, and reduces the cost of programmable controllers.
I think this will greatly contribute to the spread of new technology.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
The figure is a schematic diagram of another embodiment of the present invention, FIG. 3 is a detailed block diagram of the storage content changing circuit of the shift register type memory, and FIGS. 4a to 4j are timing diagrams of the operation of the circuit. 5a to 5d are time charts showing the input and output states of the flip-flops ₄₃₁ to _43p , and FIGS. 6a to 6g show the input and output states of the flip-flops 53 to 55. This is a time chart. 1... Storage device, 2... Processing device, 3... Input/output device, 4 ₁ to 4 _n ... Address bus, 5 ₁ to 5 _o
...Data bus, 6...Read command, 7...Write command, ₁₀₁ to _10p ...Shift register type memory, ₁₁₁ to _11p ...Command signal, 12...Gate, 13...Address coder , 14... Gate signal, 20... Instruction register, 21... Control unit, 2
2... Arithmetic unit, 23 ₁ to 23 _p ... Instruction code,
24...Latch signal, 25...Shift signal.

Claims (1)

[Claims] 1. A shift register type memory from which instructions are sequentially read out in synchronization with a shift signal, a first shift register whose input is the output of this shift register type memory, and an output of the first shift register. It is equipped with a second shift register as an input and a setting device for setting an instruction code as a signal source of an instruction signal, and also has a shift setting number and a shift current value indicating the timing at which the instruction code should be replaced, inserted, or deleted. A comparator is provided that derives a comparison signal that indicates the result of the comparison. Select one of the replacement signal, insertion signal, deletion signal, and no change request signal that commands instruction code replacement, insertion, deletion, or no change request. When the replacement or insertion signal is on and the set shift number P is equal to the current shift value q, p=q,
The output of the setting device is used as a command signal, and when the insert signal is on and the shift setting number p is larger than the current shift value q, p>q, the output of the second shift register is used as a command signal, and the erase signal is on and When the shift setting number p is greater than or equal to the current shift value q (p≧q), the output of the shift register type memory is used as the command signal, and when there is a no change request signal, the output of the first shift register is used as the command signal. Programmable controller with shift register type memory.