JPS6246914B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device in a telemeter that converts analog quantities and transmits them digitally.

An example of a conventional information processing device of this type is shown in FIG. The analog quantity AN to be transmitted is converted into digital information DI by the slave station SC, which is a transmitting station, and transmitted to the master station MC, which is a receiving station, to obtain an analog quantity instantaneous value AIV and an integrated digital value INV. In other words, the slave station SC converts the input analog quantity AN into a digital quantity DN.
A conversion circuit 1 and a transmission circuit 2 for transmitting the digital quantity DN to the master station MC as digital information DI.
The analog quantity AN is transmitted to the master station MC as digital information DI. On the other hand, the master station outputs an integrated digital value INV indicating the integrated value of the analog quantity AN inputted to the slave station SC from the input digital information DI, and an analog quantity instantaneous value AIV indicating the value of the analog quantity AN at that point in time. A receiving circuit 3 that receives digital information DI, a DA conversion circuit 4 that converts the digital information DIA from this receiving circuit 3 into an analog signal (analog quantity instantaneous value AIV), and an analog quantity It consists of a voltage frequency conversion circuit 5 that converts the instantaneous value AIV into a pulse signal FS of a frequency corresponding to its magnitude (voltage), and an integration counter 6 that integrates the pulse signal and outputs an integrated digital value INV. ing.

However, in such a conventional information processing device for a telemeter, the transmitted digital information DI is first converted into an analog signal by the DA conversion circuit 4 to obtain an analog instantaneous value AIV, and then the digital information DI is converted to an analog signal by the voltage frequency conversion circuit 5. A frequency signal FS, which is a digital signal, is obtained and integrated and counted, thereby outputting an integrated digital value INV. Therefore, since the signal conversion is performed twice, the configuration is complicated and the accuracy of the integrated digital value INV is reduced.

An object of the present invention is to provide an information processing device for a telemeter that overcomes the above-mentioned drawbacks. For this purpose, a pulse width modulation type DA conversion circuit is used as the DA conversion circuit in the master station MC to obtain the analog quantity instantaneous value AIV, and a pulse width modulation type DA conversion circuit is used to obtain the analog quantity instantaneous value AIV. Focusing on the pulse width of the output pulse of the pulse width conversion circuit, which is a component of the circuit, the integrated digital value INV is obtained by counting the reference clock using this pulse width as the gate time of the reference clock. It is a feature.

An embodiment of the present invention shown in the drawings (FIGS. 2 and 3) will be described below.

As shown in FIG. 2, the slave station SC includes an AD conversion circuit 1 and a transmission circuit 2 similar to the conventional example shown in FIG. The master station includes a receiving circuit 3 similar to the conventional example shown in FIG. A pulse width conversion circuit 8 that forms and outputs a pulse signal PW having a duty cycle (pulse width interval) corresponding to the output value BF of the buffer register 7;
Analog amount input to slave station SC by converting PW
a low-pass filter circuit 9 that outputs an analog signal (instantaneous analog quantity value) AIV corresponding to AN;
Pulse signal output from pulse width conversion circuit 8
It is provided with an integration counter 10 that counts the reference clock RCP in accordance with the pulse width of PW and outputs an integrated digital value INV per unit time. Here, the buffer register 7, pulse width conversion circuit 8, and low pass filter circuit 9 constitute a pulse width modulation type DA conversion circuit 11.

The buffer register 7 temporarily stores digital information DI (full scale N bits) corresponding to the analog quantity AN, and the data changes with the period of the transmission cycle. Further, the pulse width conversion circuit 8 converts the digital output value BF (full scale N bits) of the buffer register 7 corresponding to the analog quantity AN into a pulse signal having a duty cycle (pulse width interval) corresponding to the digital output value BF (full scale N bits).
The pulse signal has a duty of 100% when the digital output value BF is full scale N bits, a duty of 0% when it is 0 bits, and a duty of 50% when it is N/2 bits.

Next, the operation of the above embodiment will be explained. An analog quantity AN input to the slave station SC is converted into a digital quantity DN by an AD converter 1, and this digital quantity DN is transmitted to the master station MC by a transmitting circuit 2 as digital information DI. In the master station MC, the reception circuit 3 receives the transmitted digital information DI, and the buffer register 7 temporarily stores it. The digital output value BF from the buffer register 7 is converted by a pulse width conversion circuit 8 into a pulse signal PW having a duty cycle (pulse width interval) corresponding to this output value, and is converted into a pulse signal PW by a low-pass filter circuit 9 in an analog manner. It is averaged and output as the analog quantity instantaneous value AIV. Further, the pulse signal PW from the pulse width conversion circuit 8 is input to the gate section of the integration counter 10, and the integration counter 10 integrates the reference clock RCP of a predetermined frequency using this pulse width as the gate time, and converts the counted value into an integration digital signal. value INV
Output as .

In this way, in this embodiment, unlike the conventional example, the main station
MC's D-A conversion circuit performs analog conversion to obtain the analog instantaneous value AIV, and then converts the analog output to obtain the integrated digital value INT. Since the integrated digital value INV is directly obtained using the output of the pulse width conversion circuit 8 constituting the circuit, a highly accurate integrated digital value INV can be obtained, and the circuit can also be simplified.

FIG. 3 shows a specific configuration example of the main part of this embodiment shown in the block diagram in FIG. 2, and this configuration example shows the case where a comparison circuit is added for the purpose described later. There is.

As shown in FIG. 3, the pulse width conversion circuit 8 is
Digital output value BF from buffer register 7
A pulse width converter 81 that inputs the pulse signal PW and outputs the digital value BFA.
and a comparison circuit 82 that compares the digital output value BF with a cancel value set by a strap, switch, etc., and outputs a cancel signal CA1.
The comparator circuit 83 compares the digital value BFA from the pulse width converter 81 with a cancel value set by a strap, switch, etc. and outputs a cancel signal CA2.

In addition, the integration counter 10 receives a cancel signal CA1,
It is composed of a gate circuit 101 that allows the reference clock RCP to pass only while CA2 is not output and a pulse signal PW is output, and a counter 102 that counts the reference clock RCP via the gate circuit 101. The counting speed of this counter 102 can be set using a strap, a switch, etc., and the counting speed can be arbitrarily set using a program counter or the like. The low-pass filter circuit 9 is a scale conversion circuit 9 that converts the amplitude (voltage level) of the pulse signal PW to a predetermined width.
1, and a low-pass filter 92 that outputs an analog signal (instantaneous analog value) AIV corresponding to the pulse width of the scale-converted pulse signal. Note that a clock signal FCP is separately input to the buffer register 7 and the pulse width converter 81.

In such a configuration, the low pass filter 9
2 outputs the analog instantaneous value AIV, and the counter 102 outputs the integrated digital value INV, but the comparison circuit 82 outputs the input digital value.
BF is compared with a set cancel value, and if the digital input value is less than the cancel value, a cancel signal CA1 is output, the gate circuit 101 is closed, and the input of the reference clock RCP to the counter 102 is cut off. In this way, the lower digits of the input digital value BF can be invalidated to cancel errors caused by fluctuations in the analog quantity AN. Further, the comparison circuit 83 compares the input digital value BFA with a set cancel value, and closes the gate circuit 101 if the value is less than the cancel value. Therefore, the comparison circuit 83 and the counter 102 invalidate the lower digits, and in combination with the integration counter, scale conversion corresponding to the analog input can be performed.

As described above, according to the present invention, since digital processing can be performed directly in the master station MC without converting to analog, it is possible to obtain a highly accurate integrated digital value INV. In addition, the circuit for obtaining the integrated digital value INV is an analog quantity instantaneous value.
It can be used in common with the DA conversion circuit 11 for obtaining AIV, and is very effective when it is desired to simultaneously output an analog quantity and an integrated digital value.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a conventional information processing device in a telemeter, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 is a circuit showing an example of a detailed configuration of the main parts of Fig. 2. It is a diagram. SC...Slave station, MC...Master station, 1...A-D conversion circuit,
2... Transmission circuit, 3... Receiving circuit, 7... Buffer register, 8... Pulse width conversion circuit, 9... Low pass filter circuit, 10... Integration counter, 11... D-A conversion circuit, 82, 83... Comparison circuit.

Claims (1)

[Claims] 1. In an information processing device in a telemeter that converts analog quantities and transmits them as digital information; a buffer register that receives and stores the transmitted digital information; and a duty cycle ( a pulse width conversion circuit that forms and outputs a pulse signal with a pulse width interval); a low-pass filter that converts the pulse signal and outputs an analog signal corresponding to the analog amount; 1. An information processing device for a telemeter, comprising an integration counter that counts clocks and outputs an integrated digital value per unit time.