JPS6247376B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit configuration of a phase lock loop, and in particular, to each oscillation of a voltage controlled oscillator (hereinafter referred to as VCO) of a plurality of phase lock loops (hereinafter referred to as PLL). This invention relates to a circuit that can commonly adjust frequency with single control.

Conventionally, in a circuit with multiple PLLs,
The oscillation frequencies of the VCOs in each PLL were adjusted individually, so even if the oscillation frequencies of these VCOs were related to each other, the adjustment required a lot of man-hours, and if it was integrated into an integrated circuit, the number of external components would increase. arise.

In the present invention, we have created a PLL circuit that can easily and reliably adjust multiple oscillation frequencies, especially when there is no input signal, with a single adjustment, which is the drawback mentioned above, and is also suitable for integrated circuits. It is about providing.

According to the invention, first and second phase-lock loops each include a phase comparator, a low-pass filter, and a voltage-controlled oscillator; first and second transistors;
a variable constant current source that supplies a constant current to the emitters of the transistors, and a differential amplifier that takes out outputs from the respective collectors of the first and second transistors; First phase lock
A phase lock loop is obtained having a voltage controlled oscillator of the loop and means for feeding a voltage controlled oscillator of a second phase lock loop.

Next, the present invention will be explained in more detail with reference to the drawings.

First, an embodiment of the present invention will be described with reference to a simple configuration diagram shown in FIG.

An input signal is applied from the first input terminal 55 as one input of the first phase comparator 1, and the output of the first phase comparator 1 is converted to DC via the first loop filter 3. 1st at output level
VCO2 is controlled, the output of this first VCO2 is added as the other input of the first phase comparator 1, and the first
It constitutes a phase lock loop. Furthermore, it consists of a second phase comparator 4, a second loop filter 6, and a second VCO 5, and a second input terminal 5
It has a second PLL which receives an input signal from 6. Fixed or variable reference oscillation frequency signals are applied to the first and second input terminals 55 and 56 as first and second input signals, respectively. 1st
The second VCOs 2 and 5 are further supplied with respective collector outputs of transistors 8 and 9 constituting a differential amplifier.

The transistors 8 and 9 are differential amplifiers in which offset correction resistors 10 and 11 are connected to their emitters, and a variable resistor 14 is connected as a current source to the connection point between the resistors 10 and 11. Each output of this differential amplifier is connected to the highest potential 1 through loads 12 and 13.
5. On the other hand, the other end of the variable resistor 14 serving as a current source is connected to the lowest potential 16.
Each input of the differential amplifier (the bases of transistors 8 and 9) is connected to the same bias circuit 7.

The first VCO 2 is controlled by the signal obtained by converting the output of the first phase comparator 1 into DC by the first loop filter 3 and the output of the differential amplifier, but when there is no first input signal, , first loop filter 3
Since there is no output, the free-running oscillation frequency with no input is determined by the output of the differential amplifier. That is, the first VCO 2 follows the frequency of the first input signal by changing the output of the first loop filter 3, and free-running oscillation occurs when there is no input signal to the input terminal 55. The frequency is determined only by the differential amplifier output. Similarly, in the second VCO 5, the free-running oscillation frequency in the absence of an input signal to the input terminal 56 is determined only by the output of the differential amplifier.

The free-running oscillation frequencies of the first and second VCOs 2 and 5 can be freely selected by changing the variable current source (variable resistor 14) of the differential amplifier.

In addition, the transistors 8 and 9 and the resistors 10 and 11 of the differential amplifier are adjusted in advance so that the free-running oscillation frequency of the first and second VCOs 2 and 5 becomes the desired frequency.
It can also be freely obtained by calculating the relative ratio of each load 12 and 13.

In this way, the free-running oscillation frequencies of the two PLLs can be easily and reliably adjusted with one adjustment.

Next, a specific example will be described using FIG.

As in FIG. 1, the differential amplifier consisting of transistors 8 and 9 is connected to the lowest potential 16 via a resistor 14 as a variable current source, also as in FIG. Transistor 8 as the load of the differential amplifier
The base and collector of a PNP transistor 17 are commonly connected to the collector of the transistor 17, and the emitter of this transistor 17 is connected to the highest potential 15
is connected to. Similarly, the collector of the transistor 9 is connected to the base and collector of the PNP transistor 18 in common, and the emitter of the transistor 18 is connected to the highest potential 15 via a resistor 22. The inputs of the differential amplifier, ie the bases of transistors 8 and 9, are connected to a bias circuit 7.

The base of the PNP transistor 19 is connected to the base-collector connection point of the transistor 17 and the output of the first loop filter 3, and the emitter of the transistor 19 is connected to the highest potential 1 through a resistor 24.
5 by connecting transistors 17 and 1
9 constitute a first current mirror circuit. Similarly, the base of the PNP transistor 20 is connected to the base-collector connection point of the transistor 18 and the output of the second loop filter 6,
The emitter of transistor 20 is connected to highest potential 15 through resistor 23, so that transistors 18 and 20 form a second current mirror circuit.

The output currents of these current mirror circuits are used as charging currents for capacitors 25 and 26, and the oscillation frequency is controlled by this change.

The output of the first current mirror circuit (collector of PNP transistor 19) connects capacitor 25 to
The output of the second current mirror circuit (collector of PNP transistor 20) is connected to the lowest potential 16 via a capacitor 26. The input of a first comparator consisting of transistors 37 and 38 (base of transistor 38) is connected to the connection point between the first current mirror circuit and capacitor 25, and the connection point between the second current mirror circuit and capacitor 25 is connected to
6 is connected to the input of a second comparator consisting of transistors 39 and 40 (transistor 3
9 base) is connected.

The other input of the first comparator is connected to the first bleeder circuit output consisting of resistors 45, 49, 53 and transistor 55, and the other input of the second comparator is connected to resistor 46, 50, 54 and transistor 55. 56 is connected to a second bleeder circuit output consisting of 56. Further, the constant current source of the first comparator is constituted by a resistor 41, and the constant current source of the second comparator is constituted by a resistor 42, and the other ends of these resistors 41 and 42 are connected to the lowest potential 16.

The capacitor 25 is charged by the charging current of the first current mirror circuit, and when the voltage reaches or exceeds the output level of the first bleeder circuit, the transistor 38 of the first comparator is turned on, and the collector current is connected to the collector of the transistor 38. A current is supplied to the resistor 31 through the third current mirror circuit composed of the transistors 33 and 35, and a bias potential is applied to the transistor 29, turning on this transistor 29, and the resistor 27 connected to the collector of the transistor 29 is turned on. The charge in the capacitor 25 is discharged to the lowest potential 16 via the capacitor 25 . Due to this charging and discharging, the other output of the first comparator (the connection point between the collector of the transistor 37 and the resistor 43)
The signal is then input to the first phase comparator 1 through a first buffer circuit consisting of an emitter follower circuit formed by a transistor 47 and a resistor 51. In addition, the first input signal is inputted from the input terminal 55 to the other input of the first phase comparator 1, and the output thereof is converted to DC through the first loop filter 3, and the transistor 8
The first PLL circuit is connected to the collector of the first PLL circuit.

Similarly, the capacitor 26 is charged by the charging current of the second current mirror circuit, and when the voltage exceeds the output level of the second bleeder circuit, the transistor 39 of the second comparator is turned on, and the collector current is transferred to the transistor 39. A current is supplied to the resistor 32 through a fourth current mirror circuit consisting of transistors 34 and 36 connected to the collector of the resistor 32 to turn on the transistor 30 connected to the connection point between the fourth current mirror circuit and the resistor 32. The charge on the capacitor 26 is discharged to the lowest potential 16 via a resistor 28 connected to the collector of the transistor 30. Due to this charging and discharging, the other output of the first comparator (the connection point between the collector of the transistor 40 and the resistor 44) is transferred to Second phase comparator 4
Enter. In addition, a second input signal is input to the other input of the second phase comparator 4, and the output thereof is converted to direct current through the second loop filter 6, and connected to the collector of the transistor 9 to control the second input signal. 2 of
Form a PLL.

In the above circuit, if the variable resistance is changed, the free-running oscillation frequency of the first and second PLLs when no input is input changes in proportion to the change, and the desired free-running oscillation frequency can be easily obtained.

[Brief explanation of the drawing]

FIG. 1 is a simple circuit configuration diagram according to an embodiment of the present invention, and FIG. 2 is a specific circuit diagram thereof. 1... First phase comparator, 2... Second voltage controlled oscillator, 3... First loop filter, 4...
Second phase comparator, 5... Second voltage controlled oscillator, 6... Second loop filter, 7... Bias circuit, 8, 9... Transistor, 10, 11...
...Resistance, 14...Variable resistance, 15...Highest potential,
16...Lowest potential, 17, 18, 19, 20, 3
3, 34, 35, 36...PNP transistor, 3
7, 38, 39, 40, 47, 48, 29, 30
...NPN transistor, 21, 22, 23, 2
4, 27, 28, 41, 42, 43, 44, 4
5, 46, 49, 50, 51, 52...Resistance, 2
5,26... Capacitor.

Claims (1)

[Claims] 1 first and second phase lock loops each including a phase comparator, a low-pass filter, and a voltage-controlled oscillator, and a variable current source at the emitter of each of the first and second transistors. a differential amplifier that takes out first and second outputs from the collectors of the first and second transistors, respectively; and a voltage-controlled type of differential amplifier that connects the first output of the differential amplifier and a first phase lock loop. and means for connecting a second output of the differential amplifier to a second voltage controlled oscillator of a second phase lock loop.・Loop circuit.