JPS624744B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a failure handling method for a console control device having two processors.

Conventionally, in a console control device using a microprocessor, even if a fault is detected in the vicinity of the processor or the memory, due to the configuration of the microprocessor, there is no guarantee of subsequent operation, and correct fault handling cannot be performed. In addition, to improve reliability, processors are duplicated, and normally two processors share processing tasks and monitor each other.
When a failure occurs in one processor, the processing functions of that processor can be taken over by the other processor, but there is still no means to handle the failure of the other processor.

An object of the present invention is to provide a means for collecting failure information from the other console processor and performing recovery processing when a failure occurs in one of the console processors.

An embodiment of the present invention will be explained with reference to FIG. The console control device is composed of two processors that operate independently. The A processor 1 and the B processor 2 have equal functions, and each has a microprocessor unit 3 as its center.
- Executes normal operations between the main storage device 4 and the IO adapter groups 5 and 6 via the BUS7 and B-BUS8. In addition, both processors also use scan-out buses X-BUS9 and Y-BUS for troubleshooting.
Bus switching mechanism BUSSW of the present invention having 10
11 to each microprocessor unit. Normally, X-BUS9 is connected to microprocessor unit 3 of processor A, and
The BUS 10 is connected to the microprocessor unit 3 of the B processor, and serves as a means for collecting data for fault handling that each processor can independently perform. If one processor, for example the A processor, detects a serious fault, for example a fault in the microprocessor unit itself, and it becomes impossible for the A processor to continue processing the fault, the A processor will issue a message to the other B processor. It then issues a machine check interrupt request, stops the process itself, and retains the fault information. Processor B, which has received a machine check interrupt request from processor A, issues a request acceptance signal when processing becomes possible. FIG. 2 shows a circuit of the bus switching mechanism BUSSW according to the above operation. Interrupt request signal from A processor
When AERRiNT14 is issued and an acceptance signal BACPT15 is returned from the B processor, the bus is switched. The same applies to the opposite case. After switching, the B processor can scan out each unit of the A processor as if it were its own unit, and can collect fault information in the A processor.

According to the present invention, information about a failure that occurs in one processor that makes it impossible to continue processing can be easily collected from the other processor.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a console control device according to the present invention, and FIG. 2 is a block diagram illustrating the logic of a bus switching mechanism. 1...A processor, 2...B processor, 4
. . . Main storage device, 11 . . . Bus switching unit.

Claims (1)

[Claims] 1. In a console control device that has two processors that can operate independently of each other, the scan bus that is normally controlled on each side can be crossed over and transferred to the other processor in the event of a failure in one processor. In addition, a fault handling method for a console control device is characterized in that control of the scan bus is entrusted to the other party, and fault information of the processor on the faulty side can be collected.