JPS6248371B2 - - Google Patents
Info
- Publication number
- JPS6248371B2 JPS6248371B2 JP53087926A JP8792678A JPS6248371B2 JP S6248371 B2 JPS6248371 B2 JP S6248371B2 JP 53087926 A JP53087926 A JP 53087926A JP 8792678 A JP8792678 A JP 8792678A JP S6248371 B2 JPS6248371 B2 JP S6248371B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- glass
- glass film
- guard ring
- width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Formation Of Insulating Films (AREA)
- Bipolar Transistors (AREA)
- Thyristors (AREA)
Description
【発明の詳細な説明】
本発明は表面安定化のためにガラス被膜を設け
た半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device provided with a glass coating for surface stabilization.
半導体素子の表面安定化は、特に高耐圧を要求
される半導体装置の信頼性向上のためには重要な
課題であり、これに関しては多くの技術が開発さ
れている。一方素子に対する外界の影響をしや断
するためにはケース内に気密封入するハーメチツ
ク封止形が最もすぐれているが、樹脂封止形もコ
スト面から極めて魅力があるので広く採用されて
いる。樹脂封止形で高耐圧の半導体装置を得るに
はモールド樹脂中の電荷の影響を防ぐために表面
安定化の問題はより重要になる。表面安定化のた
めの表面絶縁保護膜としては二酸化ケイ素膜、窒
化ケイ素膜、有機性保護膜などもあるが、ガラス
保護膜は十分な保護作用を有し、しかも他の表面
保護膜にくらべて処理コストが安い利点がある。
しかしガラス膜の厚さを厚くすると半導体素片の
そりがひどくなりガラス膜にクラツクが生じやす
く、また後の微細加工がやり難い。一方ガラス膜
を薄くした場合、その厚さが不均一で断面が波形
であると、そのさらに薄い部分を中心にピンホー
ルの発生が多くなり、保護膜としての弱点を生ず
る。 Surface stabilization of semiconductor elements is an important issue especially for improving the reliability of semiconductor devices that require high breakdown voltage, and many techniques have been developed in this regard. On the other hand, a hermetically sealed type in which the element is hermetically sealed in a case is the best way to cut off the influence of the outside world on the element, but a resin sealed type is also widely adopted because it is extremely attractive from a cost standpoint. In order to obtain a resin-sealed semiconductor device with high breakdown voltage, the problem of surface stabilization becomes more important in order to prevent the influence of electric charge in the mold resin. There are silicon dioxide films, silicon nitride films, organic protective films, etc. as surface insulating protective films for surface stabilization, but glass protective films have a sufficient protective effect and are more effective than other surface protective films. It has the advantage of low processing cost.
However, if the thickness of the glass film is made thicker, the semiconductor chip becomes more warped, the glass film is more likely to crack, and subsequent microfabrication becomes difficult. On the other hand, when a glass film is made thinner, if its thickness is uneven and its cross section is corrugated, pinholes will occur more frequently in the thinner portion, resulting in a weak point as a protective film.
本発明は特に樹脂封止形において、経済的に適
用できるガラス保護膜のピンホールの発生を防い
だ信頼性の高い半導体装置を得ることを目的とす
る。 The object of the present invention is to obtain a highly reliable semiconductor device which is economically applicable and prevents pinholes from forming in a glass protective film, especially in a resin-sealed type.
この目的は前記最大空乏層領域内に設けられて
いる前記ガードリング部の表面を少なくとも該部
の幅の40μmを覆う絶縁薄膜部を除くようにガラ
ス保護膜が分割して付着されかつそれぞれの保護
膜の幅は500μm以下にされることにより達成さ
れる。 The purpose of this is to attach a glass protective film to the surface of the guard ring part provided in the maximum depletion layer region in parts so as to remove an insulating thin film part that covers at least 40 μm of the width of the part, and to attach each protective film separately. This is achieved by setting the width of the membrane to 500 μm or less.
以下図と実験データを引用して本発明を詳細に
説明する。 The present invention will be described in detail below with reference to figures and experimental data.
第1図は高耐圧プレーナ構造サイリスタの半導
体素子の断面を示す。n形基板の両面から拡散し
てp形領域が設けられ、さらに一方のp形領域中
への拡散によりn+領域が設けられてpnpn構造と
され、アノード電極1、カソード電極2およびゲ
ート電極3が固着される。さらに上記の拡散の際
に同時にnベース領域にはp形ガードリング層4
およびn形ガードリング層5がそれぞれ設けられ
ている。図においては電極部2,3および半導体
素片の端部6を除いてガラス膜7が被覆される。
端部6には選択拡散時のマスクの役をする酸化膜
が残されている。しかしこのような場合にはガラ
ス膜7が広いため膜厚が一様にならず図示のよう
に波形を示し、膜の薄い部分を中心にピンホール
の発生が多くなり保護作用の低下を来す。第2図
はガラス膜幅Wとガラス膜中のピンホール密度の
関係を示す。この場合のガラス膜の厚さtは10〜
20μmであり、それ以上厚くすると前述のような
不利を招くので適用できない。この図から明らか
なように、ガラス膜中のピンホール密度はガラス
膜の幅Wが600μmを超えると急激に増加する。
研究の結果、これがガラス膜の断面形状と関係す
ることが判つた。すなわち、ガラス膜の幅がほぼ
600μmになると第1図のような波形を呈する。
従つてガラス膜が波形になるのを避ける必要があ
る。第3図はこのような知見に基づいた本発明の
一実施例であるプレーナ構造サイリスタである。
このサイリスタ素子においてはnベース領域に設
けられたp形ガードリング層4およびチヤンネル
カツトのためのn形ガードリング層5の上面およ
び端部6には選択拡散時にマスクとして用いた二
酸化ケイ素膜8を残しておき、他の部分のみをガ
ラス膜9で被覆する。このようなガラス膜は分割
される結果その幅は500μm以下になるが、その
条件を満すために必要によつてはガードリングの
配置が考慮される。 FIG. 1 shows a cross section of a semiconductor element of a high breakdown voltage planar structure thyristor. A p-type region is provided by diffusion from both sides of the n-type substrate, and an n + region is further provided by diffusion into one p-type region to form a pnpn structure, and an anode electrode 1, a cathode electrode 2, and a gate electrode 3 is fixed. Furthermore, during the above diffusion, a p-type guard ring layer 4 is simultaneously formed in the n-base region.
and n-type guard ring layer 5 are provided, respectively. In the figure, a glass film 7 covers the electrode parts 2 and 3 and the end part 6 of the semiconductor piece.
An oxide film is left on the end portion 6 to serve as a mask during selective diffusion. However, in such a case, since the glass film 7 is wide, the film thickness is not uniform and shows a waveform as shown in the figure, and pinholes occur more often in the thinner parts of the film, resulting in a decrease in the protective effect. . FIG. 2 shows the relationship between the glass film width W and the pinhole density in the glass film. The thickness t of the glass film in this case is 10~
The thickness is 20 μm, and if it is thicker than that, the above-mentioned disadvantages will occur, so it cannot be applied. As is clear from this figure, the pinhole density in the glass film increases rapidly when the width W of the glass film exceeds 600 μm.
As a result of research, it was found that this is related to the cross-sectional shape of the glass membrane. In other words, the width of the glass film is approximately
When it reaches 600 μm, it exhibits a waveform as shown in Figure 1.
Therefore, it is necessary to prevent the glass film from becoming corrugated. FIG. 3 shows a planar structure thyristor which is an embodiment of the present invention based on such knowledge.
In this thyristor element, a silicon dioxide film 8 used as a mask during selective diffusion is provided on the upper surface and end portion 6 of the p-type guard ring layer 4 provided in the n-base region and the n-type guard ring layer 5 for channel cutting. Only the other parts are covered with the glass film 9. As a result of such a glass film being divided, its width becomes 500 μm or less, but in order to satisfy this condition, placement of a guard ring may be considered if necessary.
ガラス膜により挾まれる酸化膜の幅はあまり狭
くしないのが望ましい。さもないとガラス膜が酸
化膜の上を乗り越えて隣りのガラス膜とつながつ
てしまい本発明の効果がなくなる虞れがある。本
発明者等の実験によれば40μm以上とすることで
充分満足のいく結果が得られることを確めてい
る。残された酸化膜8は一般に2μm以下と薄い
がガードリング部では表面電位傾度が低いため表
面保護膜として十分役立つ。そして他の電位傾度
の高い表面部分はこれに比して膜厚が厚く、表面
保護作用の確実なガラス膜で被覆しているので樹
脂封止をしても信頼性の高い半導体装置が得られ
る。 It is desirable that the width of the oxide film sandwiched between the glass films is not too narrow. Otherwise, there is a risk that the glass film will climb over the oxide film and connect with the adjacent glass film, thereby loosing the effect of the present invention. According to experiments conducted by the present inventors, it has been confirmed that sufficiently satisfactory results can be obtained by setting the thickness to 40 μm or more. The remaining oxide film 8 is generally as thin as 2 μm or less, but since the surface potential gradient is low at the guard ring portion, it is sufficiently useful as a surface protective film. Other surface areas with high potential gradients are thicker than this and are covered with a glass film that has a reliable surface protection effect, making it possible to obtain a highly reliable semiconductor device even when resin-sealed. .
第4図は本発明の別の実施例であるプレーナ構
造のトランジスタを示す。この場合酸化膜8は表
面電位傾度の低いp形のガードリング層14、チ
ヤンネルカツト用n形層およびエミツタベース間
のpn接合の上面を被覆し、ガラス膜9はそれら
の間の面を被覆している。 FIG. 4 shows a planar transistor according to another embodiment of the invention. In this case, the oxide film 8 covers the p-type guard ring layer 14 with a low surface potential gradient, the channel cut n-type layer, and the upper surface of the pn junction between the emitter bases, and the glass film 9 covers the surface between them. There is.
なおガラス膜以外の絶縁膜として上の実施例で
は二酸化ケイ素膜を挙げたが、これをリン又はホ
ウ素などを含ませた酸化膜、あるいは窒化シリコ
ン膜その他の絶縁膜に代えてもよく、必ずしもガ
ラス膜より表面保護作用の劣るものに限定されな
いので、ガラス膜以外の絶縁膜の被覆する部位は
上記実施例のガードリング部のような表面電位傾
度の低い部分に限る必要はない。またガラス膜の
表面への設置方法は電気泳動法、沈降法などどの
方法も適用可能である。 In the above embodiment, a silicon dioxide film is used as an insulating film other than a glass film, but this may be replaced with an oxide film containing phosphorus or boron, or a silicon nitride film or other insulating film. Since the insulating film other than the glass film is not limited to those having a surface protection effect inferior to that of the film, the portion covered with the insulating film other than the glass film does not need to be limited to a portion with a low surface potential gradient such as the guard ring portion in the above embodiment. Furthermore, any method such as electrophoresis, sedimentation, etc. can be used for installing the glass membrane on the surface.
第1図は従来のガラス膜被覆プレーナ構造サイ
リスタ素子の断面図、第2図はガラス膜の幅とガ
ラス膜中のピンホール密度との関係を示す線図、
第3図は本発明の一実施例を示すプレーナ構造サ
イリスタ素子の断面図、第4図は同じくプレーナ
構造トランジスタ素子の断面図である。
4,14:p形ガードリング部、5:n形ガー
ドリング部、8:二酸化ケイ素膜、9:ガラス
膜。
FIG. 1 is a cross-sectional view of a conventional glass film-coated planar structure thyristor element, and FIG. 2 is a diagram showing the relationship between the width of the glass film and the pinhole density in the glass film.
FIG. 3 is a sectional view of a planar structure thyristor element showing one embodiment of the present invention, and FIG. 4 is a sectional view of a planar structure transistor element. 4, 14: p-type guard ring part, 5: n-type guard ring part, 8: silicon dioxide film, 9: glass film.
Claims (1)
接合を取り囲むガードリングを有し、該pn接合
表面に拡がりうる最大の空乏層領域の全面に500
μm以上の幅でガラス保護膜が施こされるものに
おいて、最大空乏層領域内に設けられている前記
ガードリング部の表面を少なくとも該部の幅の40
μmを覆う絶縁薄膜部を除くようにガラス保護膜
が分割して付着されかつそれぞれの保護膜の幅は
500μm以下にされてなることを特徴とする半導
体装置。1 At least one planar pn junction and the pn
It has a guard ring surrounding the junction, and a 500°
In the case where a glass protective film is applied with a width of 1 μm or more, the surface of the guard ring portion provided in the maximum depletion layer region is at least 40 μm in width.
The glass protective film is applied in parts to remove the insulating thin film covering the μm area, and the width of each protective film is
A semiconductor device characterized by having a thickness of 500 μm or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8792678A JPS5515227A (en) | 1978-07-19 | 1978-07-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8792678A JPS5515227A (en) | 1978-07-19 | 1978-07-19 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5515227A JPS5515227A (en) | 1980-02-02 |
| JPS6248371B2 true JPS6248371B2 (en) | 1987-10-13 |
Family
ID=13928515
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8792678A Granted JPS5515227A (en) | 1978-07-19 | 1978-07-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5515227A (en) |
-
1978
- 1978-07-19 JP JP8792678A patent/JPS5515227A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5515227A (en) | 1980-02-02 |
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