JPS6248391B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a three-terminal controlled rectifier element and a method for manufacturing the same.

A controlled rectifying element with a PNPN four-layer structure is also called a thyristor. Thyristors having three terminals include reverse blocking thyristors, reverse conducting thyristors, reverse conducting thyristors, bidirectional thyristors, and the like. In addition, recently, with advances in manufacturing technology, a wide range of current capacities ranging from several hundred mA to several thousand A has come to be produced.

The present invention relates to the structure of a reverse-blocking thyristor of several amps or less and a reverse-conducting thyristor among these thyristors, and in the following description, details thereof will be explained by taking the reverse-blocking thyristor as an example.

First, FIG. 1 shows a cross-sectional structure of a conventional reverse blocking thyristor. Further, FIG. 2 shows the state of the impurity distribution in the vertical direction along the line X--X' in FIG.

In FIG. 1, 1 is an N-type base region made of an N-type silicon single crystal substrate, and 2 is an N-type base region formed by diffusing P-type impurities from the lower surface of the N-type silicon single crystal substrate having the N-type base region 1. A P-type emitter region 3 is also a P-type base region formed by diffusing P-type impurities from the upper surface of the N-type silicon single crystal substrate, and 4 is an inward direction from a partial surface region of the P-type base region 3. This is an N-type emitter region formed by diffusing N-type impurities. 5 is an anode metallized electrode (hereinafter referred to as A electrode) that makes low resistance contact with the surface of the P-type emitter region 2;
is a cathode metallized electrode (hereinafter referred to as K electrode) that makes low resistance contact with the surface of the N-type emitter region 4;
7 is a gate electrode (hereinafter referred to as G) forming a low resistance contact formed on a partial region of the surface of the P type base region 3.
(referred to as electrodes). 8 is an external impedance consisting of a resistor and a capacitor externally connected between the G and K electrodes. 9 and 10, the A electrode 5 is K
When a predetermined voltage is applied to the electrode 6 to have a positive potential and the junction J ₂ is reverse biased, each end of the space charge region extending toward the N-type base region 1 side and the P-type base region 3 side is show. The sum of the extension width W _do of the space charge region toward the N-type base region 1 side and the extension width W _dp of the space charge region toward the P-type base region 3 side is the extension width W _d of the space charge region. I _A is the above A
A current flowing through the terminal portion of the electrode 5, I _K is a current flowing through the terminal portion of the K electrode 6, I _G is an electrode flowing through the terminal portion of the G electrode 7, I _S is a current flowing through the junction J ₂ , and R _P is the lateral resistance of the effective P-type base region (region of width W _pB ).

Recently, thyristors of several amperes or less are required to have a small gate firing current (I _GT ) and a large dV/dt (forward applied voltage increase rate) tolerance depending on the intended use.

In general, it is known that a short emitter structure is used as an effective method to increase the dV/dt withstand capability of a thyristor, but this structure has the disadvantage that the gate firing current becomes too large. It cannot be used as a structure. An alternative method is to insert a resistor or capacitor between the G and K electrodes to externally lower the impedance between the G and K electrodes, but if very high dV/dt tolerance is required,
This method alone is not sufficient and requires a structural review.

Next, the relationship between structure and dV/dt tolerance will be described. N
α _opo is the current amplification factor of an NPN transistor composed of a P-type emitter region 4, a P-type base region 3, and an N-type base region 1. The current amplification factor of the PNP transistor is α _pop , and the amplification factors for electrons and holes in the space charge region are M _o and M _h , respectively.
The gate current is I _G , and a predetermined voltage V is applied between the A electrode 5 and the K electrode 6 so that the A electrode 5 side has a positive potential.
Let I _S be the current flowing through the junction J ₂ when J 2 is applied, then the anode current I _A is expressed by the following equation.

I _A = M _o α _opo I _GT + I _S /1−(M _o α _op
o + M _h α _pop )……(1) Here, if M _o M _h = M, then I _A = M α _opo I _GT + I _S /1−M (α _opo +
α _pop )...(2) Here, I _S is expressed as I _S = I _SO + I _GR + I _dis ... (3). On the right side of equation (3), I _SO is the saturation current of the junction J ₂ when voltage V is applied, I _GR is the generated/combined current in the space charge region, and I _dis is the displacement current when voltage V is applied. is the charging current of the junction capacitance of junction J ₂ .
This I _dis is the junction capacitance of the junction J ₂ , and the electric charge is Q.
Then, I _dis = d _Q /dt=d(CV)/dt=CdV/d
tVdC/dt...(4) Also, by substituting the junction capacitance C=ε ₀ S/W _d , I _dis =CdV/dt-CV/W _d・dW _d /dt...
...(5) In addition, I _S in equation (3) is the P-type effective base area (area with a width indicated by W _dp ) when voltage V is applied.
It is also expressed as the sum of the current component I Sp flowing through the current component I _Sp and the current component I _So flowing into the N-type emitter region 4 . I
It is thought that I _So is small until _Sp saturates, and when I _Sp saturates, I _So increases rapidly. Also, the current amplification factors α _opo and α _p of the two transistors are
_op depends on the magnitude of the current flowing inside the transistor, and as the current increases, the current amplification factor also increases.
The thyristor turn-on process due to dV/dt can be explained from the above relational expression and the phenomenon described above.
Considering the case of I _GT = 0, the high dV/dt potential V is A
- When voltage is applied between the K electrodes so that the A electrode 5 side has a positive potential, a charging current (displacement current) I _dis flows as shown in equation (5). Along with this, I _S increases significantly as shown in equation (3). Of the current components of I _S , I
_Sp also increases, but as I _S increases further, the current component I _Sp saturates, and finally I _So begins to increase, resulting in NPN
The current amplification factor α _opo of the transistor increases.
As this α _opo becomes larger, the value of the denominator of equation (2) becomes smaller and I _A (=I _S ) increases. By repeating such a positive feedback phenomenon, the equation finally becomes 1-M (α _opo + α _pop ) → 0, and I _A comes to be determined by the impedance of the external circuit. That is, the thyristor is turned on. The maximum value of I _Sp is expressed by the following relational expression, where V _RP is the voltage drop due to the lateral resistance R _p of the P-type effective base region, and V _D is the diffusion potential of the junction J ₃ .

(V _RP ) I _Sp = I _Spnax + Z _GK × I _Spnax = V _D ...(6) When I _Sp becomes larger than the value I _Spnax determined by equation (6), the P-type effective base area → G-K electrode gap The voltage drop across impedance Z _GK is the diffusion potential of junction J ₃ V
becomes larger than _D , forward biasing the junction _J3 , and electrons are injected from the N-type base region 4 to the P-type base region 3, as shown by the dotted arrow line in FIG. When these electrons diffuse through the P-type base region 3 and reach the junction _J2 , they are transferred from the P-type emitter region 2 to N
Holes are injected into the shaped base region 1 as shown by the solid arrow line in FIG. As a result, I _S increases, current amplification factors α _opo and α _pop increase, and finally, the equation becomes 1-M (α _opo + α _pop )→0, and the thyristor is turned on. dV/
Broadly speaking, the following three methods can be cited as methods for increasing the dt tolerance, based on equations (1) to (6).

(1) Current amplification factors α _opo and α _p of the two transistors
Make _op smaller.

(2) Reduce the charging current I _dis caused by applying dV/dt.

(3) The current component I _So flowing into the N-type emitter region 4 of I _S is reduced.

Among these, consider method (3). In order to reduce the leakage current, that is, the current component I _So of the current I _S flowing through the junction J ₂ , other current component I _Sp
Just make it bigger. In equation (6), it is difficult to change Z _GK because it is restricted by circuit conditions. V _D cannot be easily increased considering other characteristics. Therefore, consider reducing the lateral resistance R _p and increasing the current component I _sp . In FIG. 1, assuming a structure in which the K electrode 6 and the G electrode 7 are arranged in parallel, the N-type base region 4
When the lateral dimension of the lower P-type base region 3 is a and the depth width is b, the lateral resistance R _p of the effective P-type base region width W _pB is expressed by equation (7).

R _p =ρ×a/b×W _dp ……(7) Therefore, the voltage drop V _Rp when the current component I _Spnax of I _S flows through the P-type base region is that I _Spnax is uniform over the entire junction J _{2 Assuming} that _{the current flows} with _{a current density of} If ΔR _p is reduced, the voltage drop V _Rp will be 2Δ
It can be seen that the effect of reducing RI _Spnax and reducing the lateral resistance R _p is large. Furthermore, ρ in equation (7) represents the impurity distribution of the P-type base region 3 as N=
When N ₁ (x), it is expressed by the following equation.

Here, q is the amount of charge of electrons, and μ is the mobility of holes. Further, when the P-type base region 3 is formed by a diffusion method as in the conventional case, it is generally expressed as an error function or an exponential function of the distance x. However, x
_j2 , x _j3, etc. are the junctions J ₂ , J ₃ as shown in Figure 2.
is the distance from the K electrode 6. From equation (9), it can be seen that in order to reduce ρ, the average impurity concentration of the P-type base region 3, which is shaded in FIG. 2, should be increased. However, in order to satisfy other characteristic ratings, such as gate firing current (I _GT ) and on-voltage (V _TM ), the hole concentration Nj in the P-type base region 3 at junction J ₃ must be ₃ needs to be appropriately small, making it impossible to increase the overall impurity distribution in the P-type base region 3 and lower ρ.

This invention was made in view of the above points, and without changing the hole concentration Nj ₃ at the junction J ₃ ,
The present invention aims to provide a structure that can reduce the lateral resistance of the P-type base region. This invention will be explained below.

FIG. 3 shows the impurity distribution of a reverse blocking thyristor showing an embodiment of the present invention, where the impurity distribution N=N ₂ (x) of the P-type base region 3 is expressed as A region including the extension width W _dp is formed by diffusion, and the remaining region is formed by epitaxial growth so as to have a constant concentration Nj ₃ . In this embodiment, the lateral resistance R _p is reduced without sacrificing other characteristics and ratings, such as gate firing current (I _GT ) and on-voltage (V _TM ). Furthermore, in the structure shown in FIG. 3, the space charge region is extended to the P-type base region 3 side to increase the width W _d of the entire space charge region, thereby reducing the junction capacitance of the junction J ₂ . , as can be seen from equations (4) and (5), the charging current (displacement current) I _dis when dV/dt is applied is made small, and the lateral resistance R _p of the P-type base region 3 is also made small. It is.

The correlation between the hole concentration Nj ₃ at the junction J ₃ and the normalized value of I _GT , dV/dt is as shown in FIG. 4. On the other hand, the standards for I _GT and dV/dt tolerance are I _G
Since _T is defined as an upper limit and dV/dt tolerance is defined as a lower limit, the appropriate range for Nj ₃ is 2×10 ¹⁶ to 5×10 ¹⁶ cm ^-3
It can be seen that it is. Therefore, as Nj ₃ , 2×
It is formed by selecting an arbitrary concentration within the range of 10 ¹⁶ to 5×10 ¹⁶ cm ⁻³ .

Next, a manufacturing method of an embodiment of the present invention will be explained.

FIGS. 5a to 5e are process diagrams for explaining the method of manufacturing the controlled rectifier of the present invention.

First, P-type impurities are deeply diffused from one surface of a substrate 1 made of N-type silicon single crystal as shown in FIG. do. Next, as shown in FIG. 5b, a P-type impurity is diffused shallowly from the other surface of the substrate 1 at a relatively low surface concentration to form a portion 3a of the P-type base region. The formation diffusion depth of this portion 3a of the P-type base region is set to be deeper than the width W _dp of the space charge region that extends when a predetermined reverse bias is applied to the junction J ₂ . Next, as shown in FIG. 5c, the remaining P-type base region 3b is formed by epitaxial growth so that the impurity concentration becomes a predetermined constant concentration _Nj3 . As a result, a P-type base region 3 is formed on one surface of the substrate 1. Reference numeral 11 indicates a boundary line between a portion 3a of the P type base region formed by the diffusion method and the remaining P type base region 3b formed using the epitaxial growth method. The impurity distribution in the P-type base region 3 formed in this manner is as shown in the impurity distribution in the portion indicated by N ₂ (x) in FIG. 3 (distribution between x _j3 and x _j2 on the horizontal axis). Next, as shown in FIG. 5d, N-type impurities are diffused at a high concentration into a part of the surface layer region of the P-type base region 3 to form an N-type emitter region 4. Next, the fifth
As shown in Figure e, A electrodes 5 and K are metallized electrodes that make low resistance contact with each surface of the P-type emitter region 2, N-type emitter region 4, and P-type base region 3.
Electrode 6 and G electrode 7 are formed.

By the way, the lateral resistance R _p of the P-type base region 3
Reducing I GT works to increase the gate firing current (I _GT ), which increases power loss. FIG. 6 shows the structure of an embodiment of a method for preventing this. That is, the width of a part of the P-type base region near the gate is narrowed to increase the lateral resistance of that part. In the embodiment shown in FIG. 6, a convex portion is provided in the N-type emitter region 4a near the gate, and the width of the P-type base region 3 below the convex portion is narrowed. By doing this, the gate current 1
By increasing the voltage drop caused by 3, electrons can be more easily injected into the P-type base region 3 from the N-type emitter region 4a near the gate, as shown by the dotted arrow 14. Furthermore, since the convex portion 4a of the N-type emitter region 4 is formed only near the gate,
The effect on dV/dt tolerance is small.

In the embodiment shown in FIG. 6, a convex portion 4a is provided in the N-type emitter region 4 in order to narrow the width of the P-type base region 3 near the gate. The width of the P-type base region 3 may be narrowed by providing a convex portion in both the N-type emitter region 4 and the N-type base region 1,
It goes without saying that the same effect can be obtained even if the width of the P-type base region 3 is narrowed.

As explained in detail above, in this invention, the impurity concentration of the P-type base region has a slope near the junction with the N-type base region, and the other regions have a constant concentration, so that the extension of the space charge region W _d , that is, C=ε ₀ S/W _d , and I _dis
By reducing the lateral resistance of the P-type base region and reducing the voltage drop due to _Idis , it is possible to improve the dV/dt tolerance.

Thus, according to the present invention, there is an advantage that a controlled rectifier element having a large dV/dt tolerance and a small power loss can be easily obtained.

[Brief explanation of the drawing]

Fig. 1 is a diagram for explaining the cross-sectional structure of a conventional control rectifier, Fig. 2 is a diagram for explaining the impurity concentration distribution in the X-X' longitudinal section of Fig. 1, Figs. The figure is a correlation diagram between the normalized values of N _j3 and I _GT , dV/dt, and FIGS.
FIG. 6 is a cross-sectional view of a controlled rectifier element showing another embodiment of the present invention. In the figure, 1 is an N-type base region, 2 is a P-type emitter region, 3 is a P-type base region, 4 is an N-type emitter region, N ₂ (x), N ₃ (x) are impurity distributions, and N _j3 is an impurity. It is concentration. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. An N-type base region, a P-type emitter region formed on one main surface of this N-type base region, a P-type base region formed on the other main surface of the N-type base region, and a partial region of this P-type base region. It consists of a PNPN4 layer structure with an N-type emitter region formed on the surface region.
In the three-terminal control rectifier element having an anode metallized electrode in contact with the surface of the P-type emitter region, a cathode metallization electrode in contact with the surface of the N-type emitter region, and a gate electrode in contact with the surface of the P-type base region, a uniform concentration layer with a constant impurity concentration in which the P-type base region is in contact with the N-type emitter region; and the impurity concentration at the junction with the uniform concentration layer is lower than the concentration of the uniform concentration layer, and the concentration is lower than the concentration of the uniform concentration layer in the N-type base region. The boundary between the cathode metallized electrode and the gate electrode of the P-type base region sandwiched between the N-type emitter region and the N-type base region The thickness is the same as that of the other N-type emitter regions mentioned above.
A three-terminal control rectifying element characterized in that the thickness is thinner than that of a P-shaped base region sandwiched between the P-shaped base region and the P-shaped base region.