JPS6248401B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase-locked oscillation circuit, and particularly to a phase-locked oscillation circuit with good transient response characteristics.

A conventional phase-locked oscillator circuit (hereinafter referred to as a PLO circuit) has a phase comparator circuit 10 as shown in FIG.
1 is applied to the voltage controlled oscillation circuit 103 via the 1/N frequency divider circuit 104.
(hereinafter referred to as the VCO circuit) is fed back to the phase comparison circuit, the phases of both input signals are compared, and an output voltage 2 corresponding to the phase difference is generated.

In this case, the low frequency circuit 102 removes spurious signals included in the output signal 2 of the phase comparison circuit 101, that is, unnecessary harmonic components and noise.
It also has the function of determining the response characteristics and synchronization characteristics of the PLO circuit. Connected to the output of the low frequency circuit 102
The VCO circuit 103 is an oscillation circuit that determines the oscillation frequency based on the output signal 3 of the low frequency circuit 102, and its output signal 4 is frequency-divided via the 1/N frequency divider circuit 104 as the signal 5 as described above. It is fed back to the phase comparator circuit 101. However, 1/N frequency divider circuit 10
4 is a circuit that divides the frequency of the output signal 4 of the VCO circuit 103, and is not essential to the PLO circuit, so it may be omitted in some cases.

FIG. 3 shows an example of the characteristics of the phase comparator circuit 101 described above. When a phase difference occurs between the two input signals 1 and 5 of the phase comparison circuit 101, a voltage corresponding to the phase difference is generated at its output, and this voltage causes
The VCO circuit 103 is controlled so that its output 4 is synchronized with the input signal 1. but,
Due to frequency fluctuations of input signal 1 and changes in ambient temperature
In order to cover the frequency fluctuations of the VCO circuit 103 and obtain faster response characteristics, it is necessary to increase the loop gain. However, by increasing the loop gain, the characteristic shown in FIG. 3 becomes a saturation characteristic of the output voltage for a phase difference greater than a certain level, as shown in FIG. 4. Therefore, in the characteristics shown in FIG. 4, the phase difference in the range where the output voltage is saturated is
, the output signal 4 of the VCO circuit 103
moves slowly in the direction of reducing the phase difference with the input signal 1, and when the characteristic shown in FIG. 4 reaches a point where it has a slope, it becomes synchronized rapidly. Such characteristics are
The phase comparison circuit 10 may be damaged due to momentary interruption of the input signal 1.
When the above-mentioned phase difference occurs between the input signals 1 and 5, the disadvantage is that the transition time until the PLO circuit becomes synchronized is much longer than the momentary interruption time of the input signal 1.

An object of the present invention is to provide a phase-locked oscillator circuit that improves the above drawbacks, and its gist is to provide a phase-locked oscillator circuit that includes a phase comparison circuit, a low-frequency circuit connected to the output of the phase comparison circuit, and a A voltage controlled oscillator circuit connected to the output of the low frequency circuit, a 1/N frequency divider circuit that divides the output, and a phase synchronized oscillation circuit that returns the frequency divided output to the phase comparison circuit and compares it with the input signal. An asynchronous detection circuit, and a phase control circuit constituted by a gate circuit, a delay circuit, and a gate control circuit are added to the circuit, and the asynchronous detection circuit monitors the relative relationship between the output signal of the frequency dividing circuit and the input signal. , when the two signals are in an asynchronous state, an asynchronous alarm signal is generated to control the gate circuit which receives the input signal, and its output signal is delayed to connect the phase comparator circuit, the frequency divider circuit, and the gate circuit. A phase synchronized oscillation circuit is provided, characterized in that an input is input to a gate control circuit and an output of the gate control circuit is fed back to the gate circuit.

FIG. 2 shows a block diagram of a PLO circuit according to the invention. The phase comparison circuit 101 constantly compares the phases of the input signal 1 and another signal 5, that is, the output of the 1/N frequency divider circuit, and outputs a voltage 2 corresponding to the phase difference. The low frequency circuit 102 that receives this output removes harmonics and noise contained in the output 2 of the phase comparator circuit 101, and uses its amplitude and phase characteristics to
It functions to determine the response characteristics and synchronization characteristics of the circuit.
VCO connected to output 3 of low frequency circuit 102
The circuit 103 is an oscillation circuit whose oscillation frequency is controlled by the voltage of the low frequency circuit output 3.
The VCO circuit output 4 is frequency-divided by a 1/N frequency divider circuit 104 and fed back to the phase comparator circuit 101 as a signal 5. On the other hand, the signal 5 is simultaneously input to the asynchronous detection circuit 105, which constantly monitors the phase relationship with the input signal 1, and detects the asynchronous state of the two inputs 1 and 5 of the phase comparator circuit 101 due to momentary interruption of the input signal 1, etc. When detected, an asynchronous alarm signal 6 is output. A block diagram 109 surrounded by a dotted line is a phase control circuit, which is composed of a gate circuit 106, a delay circuit 107, and a gate control circuit 108. Next, a specific example of the phase control circuit 109 is shown in FIG. In the figure, a gate circuit 106 is controlled by an asynchronous alarm signal 6 and inputs the input signal 1 to a delay circuit 107. Delay circuit 107 can be implemented by a flip-flop circuit and delays input signal 1 by a certain amount of time. This delay is
This corresponds to an operation that uniquely determines the relative phase relationship between the input signal 1 and the other input signal 5 of the phase comparison circuit 101.

Hereinafter, the operation of the phase control circuit shown in FIG. 5 will be explained using FIG. 6 as well.

FIG. 6 is a timing diagram of the circuit of FIG. As shown in FIG. 6, when the phase relationship between the two input signals 1 and 5 of the phase comparison circuit 101 is in an asynchronous state, the asynchronous detection circuit 105 generates an asynchronous alarm signal 6 and opens the gate circuit 106. Therefore, the input signal 1 becomes the signal 7 at the output of the gate circuit.
is output as The delay circuit 107 uses a reference signal (for example, a clock signal) or the like to delay a certain amount of time depending on the period of the reference signal. The delay circuit output signal 8 is transmitted between the phase comparison circuit 101 and the phase comparison circuit 101.
This is a signal that simultaneously controls the 1/N frequency divider circuit 104. In the 1/N frequency divider circuit 104, by resetting the frequency divider circuit and starting a new frequency division of the VCO circuit output signal 4 from that point, a new 1/N frequency divider circuit 104 is generated.
Frequency divider output signal, that is, new phase comparator circuit 1
The relative relationship between the other input signal 5' of 01 and the input signal 1 can be determined with a certain delay time. Furthermore, in the phase comparison circuit 101,
By controlling its initial state, the input signal 1
The rise or fall of another new input signal 5', which has a relative relationship with the rise or fall of , with a certain delay time, coincides with the rise or fall of the input signal 1. Perform an operation to limit the processes to only one process. This operation will be explained in detail with reference to FIG. In FIG. 7, T _D is a new input signal 5' for the input signal 1.
is a constant delay time. Also, T _P is the time obtained by subtracting T _D from the period of input signal 1, that is,
This is the time interval between the new input signal 5' and the next input signal 1, and is controlled by the delay circuit 107 so that T _D << T _P . In FIG. 7, there are two synchronization processes for the new input signal 5': one that corresponds to the direction of decreasing T _D with respect to input signal 1, and the other that corresponds to the direction of decreasing T _P. However, the time interval, that is, the phase difference, of T _P is much larger than that of T _D , and in the process of matching in the direction of decreasing T _P , the phase difference between the two input signals is large, so in Fig. 4, As explained above, since the phase difference is in the saturation region, the transition time becomes very long. Therefore _{, as described above, the synchronization process of the two input signals whose phase difference is controlled to be a constant delay time (phase difference) T D is}
The initial state of the phase comparator circuit 101 is controlled so that a matching process occurs only in the direction of shrinking the phase comparator circuit 101.
By this operation, the phase difference between the two input signals corresponds to a region with a slope in the characteristics shown in FIG. 4, so that the transition time until synchronization becomes extremely short.
Next, the gate control circuit 108 can be realized by a monostable multivibrator or the like as shown in FIG.
The frequency dividing circuit 104 is controlled and the phase comparator circuit 101
The gate circuit is closed until the two input signals 1 and 5 are synchronized and the asynchronous alarm signal 6 is released, and a secondary function is provided to prevent malfunction caused by the next input signal 1 during the synchronization process. Plays the role of gate control.

By the way, as shown in FIG. 4, the characteristics of the phase comparator circuit 101 are such that by increasing the loop gain, it is possible to cover frequency fluctuations caused by temperature changes in the VCO circuit 103 and obtain fast response characteristics. However, the output voltage has a saturated characteristic when the phase difference exceeds a certain level. The phase comparator circuit 10 using the phase control circuit 109 described above
Even if the phase difference between these two input signals is in the saturation region as shown in Fig. 4, the phase control of the input signal 1 of input signal 1 and the input signal 5 of the other input signal 5 can be performed in a region with a slope (region of fast response characteristics). The goal is to control the phase difference.

Therefore, the PLO circuit according to the present invention can greatly improve the transition time until synchronization in any phase asynchronous state of the PLO circuit due to instantaneous interruption of the input signal.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional phase-locked oscillation circuit, Fig. 2 is a block diagram of a phase-locked oscillation circuit according to the present invention, and Fig. 3 shows output voltage characteristics with respect to phase difference of input signals in a phase comparator circuit. figure,
Figure 4 shows that by increasing the loop gain,
A characteristic diagram of a phase comparator circuit in which the output voltage is saturated when the phase difference exceeds a certain level, FIG. 5 is a block diagram showing an example of the phase control circuit of FIG. 2, and FIG. 6 is a diagram of the circuit of FIG. 5. FIG. 7 shows a more specific timing diagram of the relative relationship between input signals 1 and 5' in FIG. In the figure, 109: phase control circuit, 1 to 9
is an input or output signal.

Claims (1)

[Claims] 1. A phase comparison circuit, a low frequency circuit connected to the output of the phase comparison circuit, a voltage controlled oscillator circuit connected to the output of the low frequency circuit, a frequency dividing circuit that frequency divides the output thereof, and An asynchronous detection circuit, a phase control circuit constituted by a gate circuit, a delay circuit, and a gate control circuit are added to a phase synchronized oscillation circuit that feeds the divided output back to the phase comparator circuit and compares it with the input signal. The detection circuit monitors the relative relationship between the output signal of the frequency dividing circuit and the input signal, and generates an asynchronous alarm signal when the two signals are in an asynchronous state to control the gate circuit that receives the input signal as an input. A phase synchronized oscillation circuit characterized in that the output signal is delayed and input to the phase comparator circuit, the frequency divider circuit, and the gate control circuit, and the output of the gate control circuit is fed back to the gate circuit.