JPS6248429B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image reading device such as a facsimile device, and more particularly to an image signal reading processing device that reads an image of a document and converts the read analog image signal into a binary image signal.

A schematic configuration of a signal processing section of a conventional image signal reading and processing device is shown in FIG. 1a. In FIG. 1a, 1 is an amplifier, 2 is a capacitor for holding the peak value of an analog image signal, 3 is a variable resistor for voltage division, and 4 is a comparison circuit.

The peak value holding circuit is composed of a capacitor 2 and a resistor 3, and the output divided voltage of this circuit is determined by a comparator circuit 4.
It is used as a reference voltage (threshold voltage) for binarizing an analog image signal. In other words,
The comparison circuit 4 compares the voltage at the slider end of the variable resistor 3 with the analog image signal, and when the latter level exceeds the former level, binarizes it into a high level "1" or a low level "0". Outputs the image signal. The divided voltage, that is, the threshold voltage, is determined as a percentage of the terminal voltage of capacitor 2 by setting the slider of variable resistor 3.
The voltage is set at this voltage, and therefore changes in proportion to changes in the peak value of the analog image signal.

The document DP to be read is sent to the image reading unit along the reference line RL, as shown in FIG. 1b, but the reading scan is performed over an area wider than the width of the document. As a result, the optical image for one line of scanning is projected onto a solid-state scanning device (CCD: charge coupled device, PDA: photodiode array, etc.) used as a photoelectric converter, and each solid-state scanning device is When reading segment information (corresponding to pixels) at a constant speed, or when providing image information by sequentially scanning an original at a constant speed using a rotating mirror or the like to a light-receiving semiconductor element, the analog information obtained from those elements is The image signal has a waveform shown in FIG. 1c in one line scanning. The high level parts on both edges of the waveform are the reading parts of the scans that are off the original, and the part between them
DPI is the original image part.

In this way, the analog image signal is at a high level outside the document width, so when scanning is from right to left in FIG. Since the time constant of capacitor 2 and resistor 3 is large, the voltage of capacitor 2 does not immediately follow the level of image area DPI, and therefore the threshold voltage given to comparator circuit 4 by resistor 3 is As shown by the one-dot chain line in FIG. 1c, the signal level of the image area DPI does not reach the predetermined setting percentage. the result,
There is no longer a predetermined correspondence relationship between the analog image signal and the binary image signal of the image portion DPI. to photoelectric converter
When using a photoelectric conversion solid-state element such as a CCD or PDF that charges up during light reception and mechanically driving it for scanning, the scanning point falls within the width of the document DP, as shown in Figure 1d, for example. Increase the scanning speed so that it is at a constant speed before the scanning point is aligned with the document.
Scanning speed control is performed in which when the device deviates from the DP, it decelerates, stops at a predetermined turning point, and then accelerates in the opposite direction from there. However, when stopping, accelerating, and decelerating, the speed of each pixel is lower than when scanning at a constant speed. As the light receiving time becomes longer, the charge-up voltage of the photoelectric conversion solid-state element becomes higher, as shown in Figure 1e, and the level of the analog image signal (more precisely, the scanning read signal) becomes higher before constant speed scanning is started. . This increases the threshold voltage, making it impossible to obtain a desired binary signal when reading and scanning the original.

The present invention prevents disturbances in the binarization process of the original image signal due to scanning reading being performed outside the width of the original and the read analog signal containing level fluctuations unrelated to the original image. purpose.

In order to achieve the above object, in the present invention,
An analog gate is inserted before the peak value holding circuit; a photoelectric converter is mounted on the carriage; a reading width timing device is provided to generate a document width scanning period display signal according to the document size; The period display signal turns on the analog gate only during the document width scanning section, and the analog image signal is supplied to the peak value holding circuit.

By doing this, the holding circuit is given an analog image signal only during document scanning, so the threshold voltage is a preset percentage of the peak value analog image signal level of the document image. Thus, the desired binarized image signal processing is performed.

As the analog gate, an analog switch circuit, a zero clamp circuit or a shunt circuit can be used.

The reading width timing device identifies the size-corresponding timing signal from the input size signal among the reading signals of the index for timing signal generation at the position corresponding to the start edge of a document and the position corresponding to the end edge of several types of originals, and calculates the size-corresponding timing signal. A logic processing device may be used to generate the document width scanning period indicating signal from generation to generation of the specified size-corresponding timing signal.

The reading width timing device also uses a sub-scanning synchronization pulse (one pulse of the document emitted every one line of main scanning).
With the step feed command pulse) and the carriage scan synchronization signal as input, the counter is cleared every time the sub-scan synchronization pulse arrives and the carriage scan synchronization signal is counted. When the count value reaches the value corresponding to the document scan start point, the flip-flop is activated. It can be a combination circuit of a counter and a gate circuit that resets the flip-flop when the count value reaches a value corresponding to the end point of document scanning.

FIG. 2a shows mainly the mechanical structure of an embodiment of the present invention, and FIG. 2b shows the structure of the reading width timing device of the embodiment.

This image reading processing device is used in a facsimile machine, and scans with a carriage 9 to which a reading head 7 and a recording head 8 are fixed.
The carriage 9 has guide bars 10 ₁ and 10 ₂
and is driven reciprocally by a main scanning drive motor 13 via a wire 11 and a guide roller 12.
On the carriage 9, there are two light receiving elements PD1 and PD.
A photocoupler 14 having 2 is fixed,
The light emitting element and the light receiving element PD1 of the photocoupler 14,
A slit plate 15 is located between the PDs. The slit plate 15 is fixed to a support rod 16. High-density slit marks 15M are carved on the slit plate 15 facing the light receiving element PD1 so as to generate a carriage scanning synchronizing pulse at a rate of one pulse every time the carriage 9 moves over a predetermined extremely short distance. Also, on the slit plate 15, there is a start mark.
MS and end marks MA, MB are engraved. The document DP is fed in front of the reading head 7 by a feed roller, and since the document is inserted along the guide wall with one edge of the document along the reference RL, the start mark MS is set at a position opposite to the light receiving element PD2 when the reading point of the reading head 7 is on the reference line RL. Endmark MA also supports A4 size originals.
When the DP is set along the reference line RL in the relationship shown in FIG. There is. Similarly, the end mark MB can be used to mark one end of a B4 or B5 document as a reference line.
When aligned with RL, the other end is set at a position facing the light receiving element PD2 when read by the reading device 7. The document DP is placed in front of the reading head 7.
A halogen lamp 16 is installed to illuminate the area. The reflected light from the original document DP is projected onto the light receiving surface of the photoelectric converter through a focusing lens in the reading head 7, and an analog image signal having a level corresponding to the amount of reflected light is obtained from the photoelectric converter. The recording head 8 is equipped with a multi-stylus for electrostatic recording.
As in the case of reading scanning, an electrostatic latent image is formed on the recording paper (not shown) by applying a high voltage corresponding to the image signal to the multi-swiss while reciprocating the carrier 9. ), the image signal is reproduced as an image by applying toner and then fixing it.

Referring to FIG. 2b, 5 is a gate circuit and 6 is a reading width timing circuit. The reading width timing circuit 6 includes flip-flops FF1 and FF2, AND gates AND1 to AND4, and an OR gate OR1.
The light receiving element PD2 of the photocoupler 11
The mark detection signal is applied to the set end S of flip-flop FF1 and AND gates AND1 and AND4, and the signal representing the A4 size document size is applied to the AND gate AND2, and the signal representing the B size document size is applied to the AND gate AND3. given to.

FIG. 2c shows the output timing of each component of the reading width timing circuit 6. The operation of the reading width timing circuit 6 will be described below with reference to FIG. 2c. Now, assume that the original size is A4, the A4 size designation signal with a high level of "1" is applied to the AND gate AND2, and the B size designation signal applied to the AND gate AND3 has a low level of "0". .

When reading scanning is started in this state, a main scanning synchronizing pulse is output from the light receiving element PD1 due to the movement of the carriage 9. When the carriage 9 moves to a position where the reading head 7 aims at the reference line RL, a pulse (original start edge signal) detecting the start mark MS is outputted from the light receiving element PD2, thereby setting the flip-flop FF1.
When the scanning progresses further and a pulse (A4 size original end signal) is output from the light receiving element PD2 when the end mark MA is detected, an output pulse is generated at the AND gates AND1 and AND2, and this is passed through the OR gate OR1 to the reset end of the flip-flop FF1. is applied to This causes flip-flop
FF1 is reset. The output pulse of the OR gate OR1 is used as a reversal command signal to drive the main scanning motor 13.
This causes the main scanning motor 13 to decelerate and stop, and then to be driven in reverse.
As a result, the light receiving element PD2 moves in the reverse direction toward the end mark MA. When the light receiving element PD2 detects the end mark MA, the flip-flop FF1 is set. The main scanning motor decelerates and stops in response to the reverse command signal, and then rotates forward.
Thereafter, similar main scanning reciprocating movements are repeated. In this way, when scanning an A4 size document, the scanning is done across the width of the document, that is, the start mark MS and the end mark.
Flip-flop FF1 only when between MA
is set, and its output FF1 is applied to the analog gate 5. As a result, in analog gate 5, the reading scan starts at the start mark.
It is turned on (the transistor of the analog gate 5 is turned off) only when it is between MS and the end mark MA, and turned off (the transistor is turned on) in other scanning areas, that is, when scanning outside the document width. Therefore, the amplifier 1 is supplied with the analog image signal of the scanning scan only when the scanning is within the document width, and the peak value held by the capacitor 2 is only that of the analog image signal of the document image. Therefore, the threshold voltage applied from the resistor 3 to the comparator circuit 4 is a set ratio (divided voltage ratio) to the peak value of the analog image signal of the original image, and the desired binary image signal is at a low level "1". When the B size designation signal is at a high level "1", the AND gate AND2 is turned off and the AND gate AND3 is turned on and heated, so the photodetector PD2 detects the start mark MS and then the end mark MB. Flip-flop FF1 is set during the period between detecting the end mark MB and detecting the start mark MS. In other words, upon detection of the start mark MS, flip-flop FF1
is set, flip-flop FF2 is set through AND gates AND1 and AND3 when the next end mark MA is detected, and OR gate OR is set when end mark MB is detected.
1 outputs an inversion command signal, and flip-flops FF1 and FF2 are reset. In the return process of the carriage 9, the end mark
Upon detection of MB, flip-flop FF1 is set, upon detection of end mark MA, flip-flop FF2 is set, and upon detection of start mark MS, an inversion command signal is output from OR gate OR1 and flip-flops FF1 and FF are set.
2 is reset. In this case, the analog gate 5 is turned on (the transistor is turned off) only when scanning is within the document width (B size), that is, between the start mark MS and end mark MB.
Only the analog image signal of the original image is given to the amplifier 1.

Note that the analog gate 5 may be connected to the input end of the capacitor 2 as shown in FIG. 2d. In this case, the capacitor 2 is discharged as soon as the scanning goes outside the document width, and is held at the ground level until the document width is scanned again.

FIG. 3 shows another embodiment of the invention. In this embodiment, the reading width timing circuit 6 is a counter.
COU, AND gate AND2, AND4, AND5,
It is composed of an OR gate OR1 and a flip-flop FF1. In a typical image reading processing device, a sub-scanning synchronizing pulse is emitted before or after one main-scanning line, and a predetermined number of carriage scanning synchronizing pulses are emitted between the sub-scanning synchronizing pulses. Therefore, by counting the carriage scan synchronization pulses based on the sub-scan synchronization pulses,
You can see where the scanning point is. In FIG. 3, the AND gate AND5 is connected to a count output terminal corresponding to the number of carriage scan synchronization pulses from when the sub-scan synchronization pulse is issued until the scanning point reaches the reference line RL, The AND gate AND2 is connected to the count output terminal corresponding to the number of counts until the scanning point reaches the other end of the A4 size document (the side opposite to the reference line RL).
The AND gate AND4 is connected to a count output terminal corresponding to the number of counts until the scanning point reaches the other end of the B-size original (the side opposite to the reference line RL). Therefore, when the scanning point reaches the reference line RL, an output is generated to the AND gate AND5 and flip-flop FF1 is set, and when the scanning point reaches the other end of the origin when there is an A4 size designation signal, The AND gate AND2 generates an output when the scanning point reaches the other end of the document when the B size designation signal is present, and an output is generated from the AND gate AND4 to issue an inversion command signal, and the flip-flop FF1 is reset. In this way,
Only when the scanning line is within the document width, the Q output FF1Q of the flip-flop FF1 becomes low level, the analog gate 5 is turned on (the transistor is turned off), and only the analog image signal of the document image is given to the amplifier 1.

In addition to the shunt circuit 5 shown in the figure, an analog switch circuit or a zero clamp circuit may be used as the analog gate circuit.

As explained above, in the image signal reading and processing device of the present invention, the document width scanning period display signal is generated, and based on this document width scanning period display signal, the analog image signal of only the document image is extracted, and its peak is extracted. Since the binarization threshold voltage is determined based on the value, a desired binarized image signal corresponding to the analog image signal can always be obtained.

[Brief explanation of the drawing]

FIG. 1a is a circuit diagram showing a signal processing circuit section of a conventional image signal reading and processing device, FIG. 1b is a plan view showing the arrangement of an original, and FIGS. 1c and 1e are analogs obtained by scanning the original. A waveform diagram showing the image signal, FIG. 1d, is a graph showing the scanning speed of the reading head. Fig. 2a is a perspective view showing the structure of the mechanism section of an embodiment of the present invention, Fig. 2b is a perspective view showing the structure of the signal processing section, and Fig. 2c is the input/output timing of electrical signals of each part of the signal processing section. This is a time chart showing. FIGS. 2d and 3 are circuit diagrams showing modified examples of the signal processing section, respectively. 1: Amplifier, 2: Capacitor, 3: Variable resistor,
4: Comparison circuit, 5: Analog gate circuit, 6: Reading width timing circuit, 7: Reading head, 8: Recording head, 9: Carriage, 10 ₁ , 10 ₂ : Guide bar, 11: Wire, 12: Guide roller, 1
3: Main scanning drive motor, 14: Photocoupler, 1
5: Slit plate, 15M: Mark, MS, MA,
MB: mark, 16: support rod, RL: reference line.

Claims (1)

[Claims] 1. Project the image of the original onto a photoelectric converter, input the analog image signal obtained from the photoelectric converter to the peak value holding circuit, and set the divided voltage of the peak value holding voltage as the threshold voltage. In an image signal reading and processing device that binarizes an analog image signal using this threshold voltage as a reference voltage: A photoelectric converter is mounted on the carriage; and a reading width timing device that generates an original width scanning period display signal according to the original size An analog gate circuit is connected to the front stage of the peak value holding circuit; the analog gate circuit is controlled by the document width scanning period display signal to provide an analog image signal to the peak value holding circuit only during the document width scanning period. An image signal reading and processing device comprising: 2. The reading width timing device inverts the state of the document width scanning period display signal when the document start edge signal arrives, according to the document size signal and the document start edge signal and document end signal included in the size-corresponding timing signal. The image signal reading and processing device according to claim 1, wherein the image signal reading and processing device is a logic device that inverts the state of the document width scanning period display signal when a document end signal specified by the signal arrives. 3 The reading width timing device starts counting the carriage scanning synchronizing signal every time the sub-scanning synchronizing pulse arrives, and when the count value reaches a predetermined value, it inverts the state of the document width scanning period display signal and continues counting. The image signal reading and processing device according to claim 1, wherein the image signal reading and processing device is a counting device that inverts the state of the document width scanning period display signal when the count value reaches a value associated with the document size.