JPS624865B2 - - Google Patents
Info
- Publication number
- JPS624865B2 JPS624865B2 JP5731377A JP5731377A JPS624865B2 JP S624865 B2 JPS624865 B2 JP S624865B2 JP 5731377 A JP5731377 A JP 5731377A JP 5731377 A JP5731377 A JP 5731377A JP S624865 B2 JPS624865 B2 JP S624865B2
- Authority
- JP
- Japan
- Prior art keywords
- epitaxial layer
- layer
- gate electrode
- epitaxial
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 238000009792 diffusion process Methods 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 230000005669 field effect Effects 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims 1
- 238000000034 method Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明は、縦形構造を有する絶縁ゲート形電界
効果トランジスタに関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect transistor having a vertical structure.
従来の絶縁ゲート形電界効果トランジスタ（以
下MOSTと記す）の構造はたとえば第１図で示
すようにＰ型のシリコン基板１の中に形成された
ｎ型のドレインならびにソース領域２と３との間
に位置するシリコン基板上にゲート酸化膜４を配
し、さらにこの上にゲート電極５を配したいわゆ
る横形構造である。この横形構造のMOSTでは
ゲート酸化膜４の下部に形成されるチヤンネルを
通して基板面と水平な方向に電流が流れることに
なる。ところで、このように電流が基板面と水平
な方向に流れるMOSTでは、大電流を流しえな
いこと、相互コンダクタンスGmが小さいこと、
高い耐圧が得られないこと、さらに大きな出力を
得ることができないことなどの本質的な問題があ
る。 The structure of a conventional insulated gate field effect transistor (hereinafter referred to as MOST) is, for example, as shown in FIG. It has a so-called lateral structure in which a gate oxide film 4 is disposed on a silicon substrate located on a silicon substrate, and a gate electrode 5 is further disposed on this. In this horizontally structured MOST, current flows in a direction parallel to the substrate surface through a channel formed under the gate oxide film 4. By the way, in a MOST where the current flows in a direction parallel to the substrate surface, a large current cannot flow, and the mutual conductance Gm is small.
There are essential problems such as the inability to obtain high breakdown voltage and the inability to obtain large output.
本発明は、かかる従来のMOSTにおける問題
点に鑑みてなされたものである。本発明では
MOSTの構造を縦形で、しかも網目状とするこ
とによつて、電流を基板面に垂直な方向に流すべ
くなし、横形構造のMOSTに存在した上記の問
題点が除かれる。 The present invention was made in view of the problems with the conventional MOST. In the present invention
By making the MOST structure vertical and mesh-like, the current can flow in a direction perpendicular to the substrate surface, eliminating the above-mentioned problems that existed in MOSTs having a horizontal structure.
以下に、本発明のMOSTの構造の一例を示す
第２図を参図して本発明を詳しく説明する。 The present invention will be described in detail below with reference to FIG. 2 showing an example of the structure of the MOST of the present invention.
第２図で示す本発明のMOSTは、図示するよ
うに、N+型シリコン基体層６、同基板上に形成
されたN-型エピタキシヤル層７、さらにこの上
に形成されたｐ型エピタキシヤル層８とからなる
シリコン基板と、同シリコン基板のｐ型エピタキ
シヤル層８の内部へ形成された網目状のN+型拡
散領域９と、N+型拡散領域９の周囲を包囲し、
かつ、ｐ型エピタキシヤル層８を貫通し底部が
N-型エピタキシヤル層７の内部にまで達してい
る網状の溝の内面に形成されたゲート酸化膜１０
と、溝をその底部からN-型エピタキシヤル層７
とｐ型エピタキシヤル層８との境界面を越す高さ
まで埋める絶縁物層１１と、同絶縁物層１１上に
形成され、その側面がゲート酸化膜１０を介して
ｐ型エピタキシヤル層８と対向するゲート電極層
１２と、同ゲート電極層１２上に形成され、溝を
埋める絶縁物層１３と、シリコン基板上の周辺部
に位置する絶縁物層１３の一部に穿設した窓内に
露呈するゲート電極層に電気的に接続されたゲー
ト電極１４と、ゲート電極形成部を除く基板上の
ほぼ全域に形成され、網目状に露呈するN+型拡
散領域９へ電気的に接続されたソース電極１５と
からなつている。なお、１６はp+型のチヤンネ
ルストツパ領域である。 The MOST of the present invention shown in FIG. 2 includes an N + type silicon base layer 6, an N - type epitaxial layer 7 formed on the same substrate, and a p type epitaxial layer formed thereon. a silicon substrate consisting of a layer 8, a mesh-shaped N + type diffusion region 9 formed inside the p-type epitaxial layer 8 of the same silicon substrate, and surrounding the N + type diffusion region 9,
And the bottom part penetrates through the p-type epitaxial layer 8.
Gate oxide film 10 formed on the inner surface of the net-like groove reaching inside the N - type epitaxial layer 7
7. Then, extend the groove from its bottom to the N - type epitaxial layer 7.
an insulating layer 11 buried to a height exceeding the interface between the p-type epitaxial layer 8 and the insulating layer 11; an insulating layer 13 formed on the gate electrode layer 12 to fill the groove; and an insulating layer 13 formed on the gate electrode layer 12 to fill the groove; a gate electrode 14 that is electrically connected to the gate electrode layer, and a source that is electrically connected to the N + type diffusion region 9 that is formed in almost the entire area of the substrate except for the gate electrode formation area and is exposed in a mesh shape. It consists of an electrode 15. Note that 16 is a p + type channel stopper region.
以上の構成からなる本発明のMOSTは、網目
状のp+型拡散領域９をソース領域、N+型シリコ
ン基体６ならびにこの上に形成され、上層部が網
目状となるN-型エピタキシヤル層７とからなる
部分をドレイン領域とし、これらの２領域に挾ま
れた網目状のｐ型エピタキシヤル層８の側面にゲ
ートを有する縦形でしかも網目状の構造となる。
なお、ドレイン電極は、シリコン基板の裏面全域
に形成される。 The MOST of the present invention having the above structure includes a mesh-shaped p + type diffusion region 9 as a source region, an N + type silicon substrate 6, and an N - type epitaxial layer formed on this and having a mesh shape in the upper layer. 7 is used as a drain region, and a mesh-like p-type epitaxial layer 8 sandwiched between these two regions has a gate on the side surface, forming a vertical mesh structure.
Note that the drain electrode is formed over the entire back surface of the silicon substrate.
ところで、本発明のMOSTでは、上記の説明
からも明らかなように、チヤンネルがシリコン基
板面と垂直な方向でしかも網状に形成され、電流
もまたシリコン基板面と垂直な方向に流れる。し
たがつて、MOSTの電流容量は従来の横形構造
のMOSTにくらべて飛躍的に増大し、このこと
により大きな出力を得ることも可能になる。さら
に、本発明のMOSTはN-型エピタキシヤル層７
ならびにｐ型エピタキシヤル層８の厚さと比抵抗
の選定によりその耐圧が決定される構造を具備し
ており、特にN-型エピタキシヤル層７の比抵抗
を十分に高めるとともにその厚さを大きく選定す
ることにより高耐圧化をはかることができる。 By the way, in the MOST of the present invention, as is clear from the above description, the channels are formed in a net shape in a direction perpendicular to the silicon substrate surface, and the current also flows in a direction perpendicular to the silicon substrate surface. Therefore, the current capacity of the MOST is dramatically increased compared to the conventional horizontally structured MOST, and this makes it possible to obtain a large output. Furthermore, the MOST of the present invention has an N - type epitaxial layer 7
In addition, it has a structure in which the withstand voltage is determined by selecting the thickness and specific resistance of the p-type epitaxial layer 8, and in particular, the specific resistance of the N - type epitaxial layer 7 is sufficiently increased and its thickness is selected to be large. By doing so, high voltage resistance can be achieved.
また、従来の横形構造のMOSTにおいて、相
互コンダクタンスを大きくするには、１〜２μｍ
程度の微細なパターン加工を施すことによつてゲ
ート長（チヤンネルの長さ）を短くする必要があ
るが、このような微細なパターン加工を施すに
は、紫外線露光、電子ビーム露光などの比較的困
難を伴う方法を駆使しなければならず、高い加工
歩留りを維持することが困難である。一方、本発
明のMOSTでは、ｐ型エピタキシヤル層８の厚
みとN+型拡散領域９の拡散長の相対的な関係で
ゲート長が定まり、上記の方法を駆使して得られ
る程の短いゲート長も極めて容易にうることがで
きる。したがつて、相互コンダクタンスGmが大
きく、利得の大きなMOSTを高い歩留りで製作
することも可能になる。 In addition, in the conventional horizontal structure MOST, in order to increase the mutual conductance, it is necessary to
It is necessary to shorten the gate length (channel length) by applying a relatively fine pattern processing, but in order to perform such a fine pattern processing, relatively advanced methods such as ultraviolet ray exposure and electron beam exposure are required. This requires the use of difficult methods, making it difficult to maintain a high processing yield. On the other hand, in the MOST of the present invention, the gate length is determined by the relative relationship between the thickness of the p-type epitaxial layer 8 and the diffusion length of the N + type diffusion region 9, and the gate length is determined by the relative relationship between the thickness of the p-type epitaxial layer 8 and the diffusion length of the N + type diffusion region 9, and the gate length is determined by the relative relationship between the thickness of the p-type epitaxial layer 8 and the diffusion length of the N + type diffusion region 9. Long lengths can also be obtained very easily. Therefore, it becomes possible to manufacture a MOST with a large mutual conductance Gm and a large gain at a high yield.
以上説明してきたところから明らかなように、
本発明によれば、従来のMOSTにくらべてはる
かにすぐれた特性を有するMOSTが実現され
る。なお、以上の説明は、Ｎチヤンネル形の
MOSTを例になされたのであるが、図示した各
領域の導電型を逆とし、ｐチヤンネル形としても
よいことは勿論である。 As is clear from what has been explained above,
According to the present invention, a MOST with far superior characteristics compared to conventional MOSTs can be realized. Note that the above explanation applies to N-channel type
Although MOST is used as an example, it goes without saying that the conductivity types of the illustrated regions may be reversed to form a p-channel type.
第１図は従来の絶縁ゲート形電界効果トランジ
スタの構造を示す断面図、第２図は本発明の一実
施例にかかる絶縁ゲート形電界効果トランジスタ
の構造を示す断面図である。
６……N+型シリコン基板、７……N-型エピタ
キシヤル層、８……ｐ型エピタキシヤル層、９…
…N+型拡散領域、１０……ゲート酸化膜、１
１，１３……絶縁物層、１２……ゲート電極層、
１４……ゲート電極、１５……ソース電極。
FIG. 1 is a sectional view showing the structure of a conventional insulated gate field effect transistor, and FIG. 2 is a sectional view showing the structure of an insulated gate field effect transistor according to an embodiment of the present invention. 6... N + type silicon substrate, 7... N - type epitaxial layer, 8... P type epitaxial layer, 9...
...N + type diffusion region, 10 ... Gate oxide film, 1
1, 13... Insulator layer, 12... Gate electrode layer,
14...gate electrode, 15...source electrode.
Claims (1)
成されたこれと同一導電型でこれよりは比抵抗の
高い第１のエピタキシヤル層、同第１のエピタキ
シヤル層上に形成されたこれとは逆導電の第２の
エピタキシヤル層とからなるシリコン基板と、同
シリコン基板の第２のエピタキシヤル層の内部に
形成されたこれとは逆導電型の網目状の拡散領域
と、同拡散領域の周囲を包囲するとともに前記第
２のエピタキシヤル層を貫通して底部が前記第１
のエピタキシヤル層の内部に達している網状のＵ
字溝の内面に形成されたゲート酸化膜と、前記Ｕ
字溝をその底部から第１および第２のエピタキシ
ヤル層との境界面を越す高さまで埋める第１の絶
縁物層と、同第１の絶縁物層上に形成されその側
面が前記ゲート酸化膜を介して第２のエピタキシ
ヤル層と対向するゲート電極層と、同ゲート電極
層上に形成されて前記Ｕ字溝を埋める第２の絶縁
物層と、同第２の絶縁物層の一部に穿設した窓内
に露呈するゲート電極層に電気的に接続されたゲ
ート電極と、ゲート電極形成部を除く基板上のほ
ぼ全域に形成され、網目状に露呈する拡散領域に
電気的に接続されたソース電極とを備え、前記ゲ
ート電極層がＵ字溝の側面に現われた前記第２の
エピタキシヤル層上にのみ位置していることを特
徴とする絶縁ゲート形電界効果トランジスタ。1. A silicon base layer of one conductivity type, a first epitaxial layer of the same conductivity type and higher resistivity formed on the same base layer, and a first epitaxial layer formed on the same first epitaxial layer. A silicon substrate consisting of a second epitaxial layer having a conductivity opposite to that of the second epitaxial layer, a mesh-like diffusion region having a conductivity opposite to that formed inside the second epitaxial layer of the same silicon substrate, and a second epitaxial layer having a conductivity opposite to that of the second epitaxial layer. surrounding the periphery of the region and penetrating the second epitaxial layer, the bottom of which is the first epitaxial layer.
The net-like U reaching inside the epitaxial layer of
The gate oxide film formed on the inner surface of the groove and the
a first insulating layer that fills the groove from its bottom to a height that exceeds the interface between the first and second epitaxial layers; a gate electrode layer that faces the second epitaxial layer through the gate electrode layer, a second insulating layer formed on the gate electrode layer and filling the U-shaped groove, and a part of the second insulating layer. The gate electrode is electrically connected to the gate electrode layer exposed in the window drilled in the window, and the diffusion region is formed in almost the entire area of the substrate except for the gate electrode formation area and is exposed in a mesh pattern. an insulated gate field effect transistor, characterized in that the gate electrode layer is located only on the second epitaxial layer appearing on the side surface of the U-shaped groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5731377A JPS53142189A (en) | 1977-05-17 | 1977-05-17 | Insulating gate type field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5731377A JPS53142189A (en) | 1977-05-17 | 1977-05-17 | Insulating gate type field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS53142189A JPS53142189A (en) | 1978-12-11 |
| JPS624865B2 true JPS624865B2 (en) | 1987-02-02 |
Family
ID=13052066
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5731377A Granted JPS53142189A (en) | 1977-05-17 | 1977-05-17 | Insulating gate type field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS53142189A (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4379305A (en) * | 1980-05-29 | 1983-04-05 | General Instrument Corp. | Mesh gate V-MOS power FET |
| JPS57128966A (en) * | 1981-02-02 | 1982-08-10 | Seiko Epson Corp | Mis type semiconductor device |
| FR2513016A1 (en) * | 1981-09-14 | 1983-03-18 | Radiotechnique Compelec | HIGH VOLTAGE TRANSFORMER V MOS AND METHOD FOR MANUFACTURING THE SAME |
| US4554570A (en) * | 1982-06-24 | 1985-11-19 | Rca Corporation | Vertically integrated IGFET device |
| US4757361A (en) * | 1986-07-23 | 1988-07-12 | International Business Machines Corporation | Amorphous thin film transistor device |
| EP0690513B1 (en) * | 1986-11-19 | 1999-05-06 | Research Development Corporation of Japan | Step-cut insulated gate static induction transistors and method of manufacturing the same |
| JP2570742B2 (en) * | 1987-05-27 | 1997-01-16 | ソニー株式会社 | Semiconductor device |
| US4914058A (en) * | 1987-12-29 | 1990-04-03 | Siliconix Incorporated | Grooved DMOS process with varying gate dielectric thickness |
| US6351009B1 (en) | 1999-03-01 | 2002-02-26 | Fairchild Semiconductor Corporation | MOS-gated device having a buried gate and process for forming same |
-
1977
- 1977-05-17 JP JP5731377A patent/JPS53142189A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS53142189A (en) | 1978-12-11 |
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