JPS6248864B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to logic simulators.

When starting a logic device that uses a large number of integrated circuits of many types, if you find an error after the device is actually wired and tested, it will take a lot of time to correct the circuit, and it will take a lot of development time. The cost will increase. Furthermore, as LSIs and custom ICs have come into widespread use in recent years, it has become necessary to modify integrated circuits, so it is necessary to find logical design errors as soon as possible. Logic simulators are often used to perform equipment testing starting from the previous stage. Logic simulators perform the same operations as the target logic device through simulation, and are often performed using software.

Since the logical simulation is processed sequentially by software, as the logical scale of the target device increases, the processing time increases and one
The drawback is that it takes hundreds of years to simulate a CPU, making it impractical.

SUMMARY OF THE INVENTION An object of the present invention is to provide a logic simulator that eliminates these conventional drawbacks and performs logic simulation of a large-scale logic device at high speed.

According to the logic simulator of the present invention, the integrated circuits constituting the logic device to be simulated are divided by type and number, and the simulation for each integrated circuit is shared between a plurality of processors. A state memory that stores logic states corresponding to input/output pins, an integrated circuit logic operator that performs logic operations for the types of integrated circuits that are assigned, and a wiring table for output pins for the number of integrated circuits that are assigned. It has a connection memory that connects multiple processors and communicates with each other, and the multiple processors retrieve the logic states of input/output pins corresponding to the integrated circuit to be simulated from their respective state memories. ,
The integrated circuit logic arithmetic unit performs calculations to update the state memory, and in response to changes in the output pins, the processor to be wired to is found from the connected memory, and processing is performed simultaneously while transmitting change information via the connection network, so parallel processing is possible. Furthermore, since the state memory, integrated circuit logic arithmetic unit, and connection memory are each separately provided, accesses are not concentrated, and logic simulation can be performed at high speed.
Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a logic simulator showing one embodiment of the present invention. P1, P2, ......
PJ...PN are multiple processors, S1,
S2,......SJ......SN are respective state memories, I1, I2,......IJ......IN are respective integrated circuit logic operators, C1, C2,......CJ...
...CN is each connection memory, and 1 is a connection network.

Each processor PJ retrieves the logic state of the input/output pin corresponding to the integrated circuit to be simulated from the state memory SJ, performs a logic operation on the integrated circuit from the integrated circuit logic operator IJ, updates the state memory SJ, and outputs the output pin. The integrated circuit to be wired is determined from the connection memory CJ according to the change in the connection network 1.
Processors P1, P2, ...... shared through
PJ...Continues to either PN. This operation is performed by each processor P1, P2,...PJ...
...is carried out in parallel in PN, and state memory I
1, I2, ......IJ...IN and connected memory C1, C
2. The memory accesses to CJ......CN are independent, and the integrated circuit logic operation units I1, I2, IJ...IN also perform integrated circuit operations independently. High-speed logic simulation is performed.

FIG. 2 shows a plurality of processors P1 shown in FIG.
FIG. 2 is a block diagram showing a configuration sequence of one processor PJ among P2, . . . PJ PN.

101 is a group of connection lines with connection network 1, 1
02 is a group of access lines to the state memory SJ, 103 is a group of access lines to the integrated circuit logic operation unit IJ, 104
is a group of access lines with connection memory CJ. 11
0 and 118 are a message input line group and a message output line group, respectively, of the connection line group of the coupling network. 10 is a message input control section;
It accepts a status change message for the corresponding integrated circuit from the message input line group 110 and outputs an input message 111. Reference numeral 11 denotes an access control unit for the state memory, which transmits input/output pin information of the integrated circuit corresponding to the input message 111 to the access line group 10.
2 and outputs a pin state 113. Reference numeral 12 denotes an arithmetic control unit, which uses the pin state 113 to access the integrated circuit logic operator IJ from the access line group 103, and outputs a new state 115. The access control device 11 inputs a new state 115 and updates the state memory SJ via the access line group 112. 13 is a comparison section which inputs the new state 115 and pin state 113, checks the output change, and outputs the change 1.
Roll 16. Reference numeral 14 denotes an access control unit for the connection memory, which uses a change output 116 to access the connection memory CJ via the access line group 104 119 to find the integrated circuit to which it is wired and sends a change message 117.
Output. Reference numeral 15 denotes an output control section of the connection network, which inputs the change message 117 and transmits it to the connection network 1 via a group of message output lines 118 to the processor PK that shares the change message.

Figure 3 shows each state memory S shown in Figure 1.
1, S2, ......SJ......SN is a block diagram showing an example of the configuration of one state memory SJ.

Number address access 301 of the integrated circuit to be shared from the access line group 102 from the processor PJ
is given, 31 is the access control unit where the number address access 301 is input and address access 3
Roll out 02. 32 stores the status of the input/output pins of the integrated circuit shared by the status memory cells, and outputs the input/output pin status value 303 if the address access 302 is a read access. If address access 302 is an update access, a new state is written to state memory cell 32.

Fig. 4 shows one of the integrated circuit logical operation units I1, I2, ......IJ......IN shown in Fig. 1.
FIG. 2 is a block diagram showing an example of the configuration of one integrated circuit logic operation unit IJ. A computation request 401 comes from the access line group 103 coming from the processor PJ. 41 is a selector which, when a calculation request 401 comes, determines the type of integrated circuit on which the calculation is to be performed and selects one of the selection output group 402. 42A, 42B, . . . 42M are a group of integrated circuits and share the responsibility. Integrated circuits that are actually used to perform the types of logical operations that are required for integrated circuits;
Alternatively, PLA is used which has the same function as the integrated circuit actually used. The selector 41 selects integrated circuit groups 42A, 42B,...4 according to the type.
One of 2M is selected and a logical operation is performed to obtain a state value 403. A status output device 43 outputs a status value 404 newer than the obtained status value 403 to the access line group 103.

Figure 5 shows each connection memory C shown in Figure 1.
FIG. 1 is a block diagram showing an example of the configuration of one connection memory CJ in CN. 5
1 is a pointer table, and access line group 10
4 inputs a state change 501 consisting of processor PJ, and outputs a pointer 502 of a table containing the names of integrated circuits to which output pins are wired. Reference numeral 53 is a connection table that stores the names of integrated circuits to which wiring is connected corresponding to output pins and the names of processors that share the wiring. Reference numeral 52 denotes an access control unit which, when the pointer 502 is input, outputs a table access 503, accesses the connection table 53, extracts the name of the integrated circuit to which the wiring is connected and the name of the processor to be shared, and sends the name of the wiring destination 504 to the access line group 104. Output.

FIG. 6 is a block diagram showing an example of the configuration of the connection network 1 shown in FIG. 1. _X11 , _X12
...... X _1u , X ₂₁ , _{X 22} , ...... Connected to allow data transfer. A plurality of processors P1, P2,
......PJ...PN are access line groups 601, 602, ......60, each of which is a pair of input/output line groups.
N, and any processor PJ can transmit a message of an output change to any processor PK. Although FIG. 6 shows an example of the configuration of the coupling network 1 using a multi-stage configuration of crossbar switches, it can also be configured using other methods such as a common bus method or a single-stage large crossbar switch.

According to the present invention, a system to be simulated is configured. The simulation of each integrated circuit is divided into types and numbers, and the simulation of each integrated circuit is shared between multiple processors. The logic state of the target integrated circuit is given to each integrated circuit logic operation unit, which performs logic operations for the types of integrated circuits, to perform logic operations, update the state memory, and respond to changes in the output pin. Then, the integrated circuits to be wired are found from each connection memory that stores wiring tables corresponding to the number of output pins to be shared, and the processors are connected. Sharing via a bond network. Since the logic simulation of the target system is performed in parallel by a plurality of processors for each integrated circuit constituting the system while transmitting state changes to the processor, the effect can be achieved at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block example of a logic simulator showing one embodiment of the present invention, and FIGS. 2 to 6 show each of the processor, state memory, integrated circuit logic operation unit, connection memory, and coupling network shown in FIG. FIG. 3 is a block diagram showing a configuration example. 1...Connection network, P1, P2,...
PJ……PN……Processor, S1, S2,……
…SJ…SN…Status memory, I1, I2,…
……IJ……IN……Integrated circuit logic operator, C1,
C2,……CJ……CN……Connection memory, 10
...Message input control section, 11, 14, 31,
52...Access control unit, 12...Arithmetic control unit,
13... Comparison section, 15... Output control section, 32...
State memory cell, 41...Selector, 42A, 42
B...42M...Integrated circuit group, 43...Status output device, 51...Pointer table, 53...Connection table, X11, X12...X1U, X2
1,X22,...X2U...Crossbar switch.

Claims (1)

[Claims] 1. In a logic simulator that simulates a logic device, a plurality of processors divide the integrated circuits constituting the logic device by type and number and perform the simulation, and each of the plurality of processors has a Each state memory stores the logic states of the input/output pins, each integrated circuit logic operator performs logic operations for the types of integrated circuits to be shared, and the output pins for the number of output pins to be shared Each of the plurality of processors has a connection memory that stores a wiring table, and a connection network that connects the plurality of processors and communicates with each other. The state is taken out, the operation is performed by each of the integrated circuit logical arithmetic units, the state memory is updated, and the integrated circuit to be wired is found from each of the connection memories according to the change in the output state, and the integrated circuit is connected via the connection network. A logic simulator characterized in that an output change is transmitted to the processor in charge, and the plurality of processors perform logic simulation in parallel.