JPS6248918B2 - - Google Patents
Info
- Publication number
- JPS6248918B2 JPS6248918B2 JP10968781A JP10968781A JPS6248918B2 JP S6248918 B2 JPS6248918 B2 JP S6248918B2 JP 10968781 A JP10968781 A JP 10968781A JP 10968781 A JP10968781 A JP 10968781A JP S6248918 B2 JPS6248918 B2 JP S6248918B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- inp
- active layer
- ingaasp
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000000903 blocking effect Effects 0.000 claims description 18
- 238000009792 diffusion process Methods 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 16
- 239000012535 impurity Substances 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000010030 laminating Methods 0.000 claims description 2
- 230000010355 oscillation Effects 0.000 description 7
- 238000005253 cladding Methods 0.000 description 5
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000007791 liquid phase Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 125000005997 bromomethyl group Chemical group 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/2054—Methods of obtaining the confinement
- H01S5/2059—Methods of obtaining the confinement by means of particular conductivity zones, e.g. obtained by particle bombardment or diffusion
Landscapes
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
- Semiconductor Lasers (AREA)
Description
【発明の詳細な説明】
本発明は埋め込みヘテロ構造半導体レーザ、特
にInpを基板とするInGaAsP埋め込みヘテロ構造
半導体レーザに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a buried heterostructure semiconductor laser, and particularly to an InGaAsP buried heterostructure semiconductor laser using InP as a substrate.
埋め込みヘテロ構造半導体レーザ(以下BH−
LDと略す。)は低い発振しきい値電流、安定化さ
れた発振横モード、高温動作可能などの優れた特
性を有するため、光フアイバ通信用光源として注
目を集めている。例えば平尾等は1979年12月発行
の電子材料誌第18巻第12号の58ページから61ペー
ジで報告しているように、第1図に示す形状の
InGaAsP BHLDを製作している。ところで、
AlGaAs系のレーザに比べてInGaAsP系のレーザ
では一般に発振しきい値電流の温度依存性が大き
いという欠点がある。すなわちAlGaAs系半導体
レーザでは発振しきい値電流I+hをI+hocexp
(T/Tp)と表わした時の特性温度Tpが120〜
150K程度であるのに対し、InGaAsP系では60〜
70K程度と小さく、発振しきい値電流の温度依存
性が大きい。さらにInGaAsP BH−LDでは、40
℃程度以上で活性層周辺のInPのp−n接合を介
して流れるもれ電流が増加するために第1図にお
いて、p形InP電流ブロツク層106が無い場合
には40℃程度以上で特性温度Tpは30−50Kと減
少する。したがつてもれ電流を防止するために、
第1図において電流ブロツク107とn形クラツ
ド層102との間に、活性層側面につながるp形
InP電流ブロツク層106を設け、メサ側面部を
pnpn多層構造にすることにより、80℃程度まで
特性温度Tpを70K前後に保持することが可能と
なつている。 Buried heterostructure semiconductor laser (BH−
Abbreviated as LD. ) has excellent characteristics such as low oscillation threshold current, stabilized oscillation transverse mode, and ability to operate at high temperatures, so it is attracting attention as a light source for optical fiber communications. For example, Hirao et al. reported on pages 58 to 61 of Electronic Materials Magazine Vol. 18, No. 12, December 1979, that the shape shown in Fig.
We are producing InGaAsP BHLD. by the way,
Compared to AlGaAs-based lasers, InGaAsP-based lasers generally have a drawback in that the oscillation threshold current has greater temperature dependence. In other words, in an AlGaAs semiconductor laser, the oscillation threshold current I +h is I +h ocexp
The characteristic temperature T p expressed as (T/T p ) is 120~
While it is about 150K, it is 60~60K for InGaAsP system.
It is small at around 70K, and the temperature dependence of the oscillation threshold current is large. Furthermore, for InGaAsP BH−LD, 40
Since the leakage current flowing through the p-n junction of InP around the active layer increases at temperatures above about 40°C, the characteristic temperature in FIG. T p decreases to 30-50K. Therefore, to prevent leakage current,
In FIG. 1, between the current block 107 and the n-type cladding layer 102, there is a p-type layer connected to the side surface of the active layer.
An InP current blocking layer 106 is provided to cover the mesa side surface.
By forming the pnpn multilayer structure, it is possible to maintain the characteristic temperature T p at around 70K up to around 80°C.
ところで第1図に示すBH−LDの製造過程にお
いて、p形InP電流ブロツク層106をInGaAsP
活性層103の側面につなげて形成するために
は、逆メサ形状にエツチングする場合のエツチン
グ深さ、およびp形InP電流ブロツク層106の
成長膜厚を精度良く制御する必要があるが、現在
用いられている液相エピタキシヤル成長法、およ
びBrメタノール系エツチング液などを用いたメ
サエツチングの手法では、必ずしも十分な制御性
があるとは言えず、電流ブロツク層106を活性
層側面の所望の位置に再現性よく形成することは
難しい。したがつて第1図に示すInGaAsPBH−
LDの製作歩留りが悪いという結果を招いてい
る。 By the way, in the manufacturing process of the BH-LD shown in FIG. 1, the p-type InP current blocking layer 106 is replaced with InGaAsP.
In order to form a layer connected to the side surface of the active layer 103, it is necessary to precisely control the etching depth when etching into an inverted mesa shape and the growth thickness of the p-type InP current blocking layer 106. The conventional liquid phase epitaxial growth method and the mesa etching method using a Br methanol-based etching solution do not necessarily provide sufficient controllability, and it is difficult to place the current blocking layer 106 at a desired position on the side surface of the active layer. It is difficult to form it with good reproducibility. Therefore, the InGaAsPBH shown in Figure 1
This results in poor LD production yields.
本発明の目的は上記の欠点を除くべく、活性層
以外の部分へのもれ電流が少なく、したがつて温
度特性のすぐれたInGaAsPBH−LDを歩留りよく
製造する方法を提供することにある。 SUMMARY OF THE INVENTION In order to eliminate the above-mentioned drawbacks, an object of the present invention is to provide a method for manufacturing an InGaAsPBH-LD with a high yield, which has low leakage current to portions other than the active layer, and therefore has excellent temperature characteristics.
本発明によれば、面方位が(100)、あるいは
(100)近傍であるn形InP基板に少くとも
In1-xGaxAs1-yPy(0<x<1,0y1)活
性層を含む半導体層を積層させた多層膜構造ウエ
フアの表面に<011>方向に沿つたストライプ状
の拡散保護マスクを形成した後p形不純物を前記
In1-xGaxAs1-yPy活性層よりも深く選択拡散する
工程と、選択拡散されたp形不純物領域の一部あ
るいは全体を前記In1-xGaxAs1-yPy活性層まで化
学エツチングして多層膜構造の<011>方向に平
行なメサストライプを形成する工程と、前記メサ
ストライプの上面のみを除いて、n形
In1-x′Gax′As1-y′Py′(0x′<x,y<y′1
)
電流ブロツク層を積層させた後にp形
In1-x″Gax″As1-y″Py″(0x″<1,0<y″
1)埋め込み層を全面にわたつて連続して積層さ
せるエピタキシヤル成長工程とを含むことを特徴
とする埋め込みヘテロ構造半導体レーザの製法が
得られる。 According to the present invention, at least an n-type InP substrate having a plane orientation of (100) or near (100)
In 1-x Ga x As 1-y P y (0<x<1,0y1) Striped diffusion protection along the <011> direction on the surface of a multilayer structure wafer in which semiconductor layers including an active layer are laminated. After forming the mask, the p-type impurity is
A step of selectively diffusing In 1 -x Ga x As 1-y P y deeper than the active layer , and partially or entirely of the selectively diffused p - type impurity region A process of chemically etching up to the active layer to form mesa stripes parallel to the <011> direction of the multilayer film structure, and an n-type
In 1-x ′Ga x ′As 1-y ′P y ′(0x′<x, y<y′1
)
After laminating the current blocking layer, p-type
In 1-x ″Ga x ″As 1-y ″P y ″(0x″<1,0<y″
1) A method for manufacturing a buried heterostructure semiconductor laser is obtained, which includes the following steps: 1) an epitaxial growth step in which a buried layer is continuously laminated over the entire surface.
実施例を説明する前に面方位が(100)のInP
基板上に形成した<011>方向に沿つたメサスト
ライプを液相エピタキシヤル成長法によりInP層
で埋める場合の積層形状を図を用いて簡単に説明
する。第2図はメサ基板上に成長させたInPの成
長形状をあらわす斜視図を示す。高さ0.5μm,
幅2μmのメサストライプを形成したInP基板2
01上にInPエピタキシヤル層202を成長させ
る場合、筆者らが特願昭55−123261において記載
したように成長条件の違いによつて第2図a,
b,cのように成長させることが可能である。す
なわちInPエピタキシヤル層はメサ側面部と平担
部には途中膜厚が薄くなりながらも連続して成長
するが、メサ上面には積層しない。このような
InPエピタキシヤル層の成長形状は電流とじこめ
型InGaAsP BH−LDの作製に都合のよい形状で
ある。ところでn形InPのメサストライプ以外の
部分をp形不純物拡散によりp+層としておけば
第2図bの成長方法でn−InP層を成長させるこ
とによりこの部分はnpn構造となり、順方向バイ
アスを印加した場合にメサ部分だけに電流を集中
させることができて、もれ電流が少なく、したが
つて温度特性のすぐれたBH−LDの作製に有効で
ある。 Before explaining the examples, we will introduce InP with (100) plane orientation.
The stacked-layer shape when a mesa stripe formed on a substrate along the <011> direction is filled with an InP layer by liquid phase epitaxial growth will be briefly explained using a diagram. FIG. 2 shows a perspective view showing the growth shape of InP grown on a mesa substrate. Height 0.5μm,
InP substrate 2 with mesa stripes 2 μm wide
When growing an InP epitaxial layer 202 on 01, as described by the authors in Japanese Patent Application No. 55-123261, the growth conditions shown in FIG.
It is possible to grow as shown in b and c. That is, the InP epitaxial layer grows continuously on the mesa side surface and the flat surface, although the film thickness becomes thinner in the middle, but it is not laminated on the mesa top surface. like this
The growth shape of the InP epitaxial layer is convenient for fabricating a current confinement type InGaAsP BH-LD. By the way, if the part other than the mesa stripe of n-type InP is made into a p + layer by p-type impurity diffusion, by growing an n-InP layer using the growth method shown in Figure 2b, this part becomes an npn structure, and the forward bias can be applied. When applied, the current can be concentrated only in the mesa portion, resulting in less leakage current, and is therefore effective in producing a BH-LD with excellent temperature characteristics.
第3図は本発明の望ましい実施例の製造方法を
示すための断面図をあらわす。まず第3図1にお
いて、n−InP基板301上にn−InPバツフア
層302(Te ドープ、厚さ5μm)、ノンドー
ブIn0.70Ga0.30As0.65P0.35活性層303(波長1.3
μm 組成、厚さ0.15μm)、p−InP クラツド
層304(Zn ドープ、厚さ0.4μm)を順次積
層させた通常のInGaAsP−InP DH ウエフアに
p形不純物の選択拡散保護マスクとして
SiO2CVD膜を約0.3μm堆積する。通常のフオト
リングラフイの手法により、<011>方向にそつて
幅4μmのフオトレジスト・ストライプを形成し
てこれをマスクとしてフツ酸を用いてエツチング
し、選択拡散保護マスク305を残す。次にp形
不純物としてZnを深さ約1.2μmまで拡散してp
形拡散層306を形成する。このとき図に示すよ
うに選択拡散保護マス305の下部には幅2〜3
μmの拡散されない層が残ることになる。次に第
3図2において選択拡散保護マスク305をこん
どはエツチングマスクとして用い、InPの選択エ
ツチング液である塩酸:H2O=4:1の混合エツ
チング液を用いてp−InPエピタキシヤル層のみ
エツチングする。その後SiC2マスクをとり去つ
てさらにブロムメチルエツチング液を用いて約
0.2〜0.3μmエツチングすることにより図に示す
ようにBH−LDの活性層307を含む高さ0.6μ
mのメサ308を形成する。この段階で図に示す
ようにメサ308部分以外ではn−InP層中にp
形不純物拡散層が形成されている。次に第3図3
において埋め込み成長を行なう。埋め込み成長は
先に述べたように第2図bのような成長条件で行
なう。すなわちn−InP電流ブロツク層309
(Teドープ平担部厚さ0.4μm)メサストライプ
の上面以外に成長させ、その後p−InP埋め込み
層310(Znドープ平担部厚さ1.5μm)を全面
に連続して積層し、n−InGaAsPキヤツプ層3
11(Teドープ、厚さ0.5μm)を積層させて成
長を終える。埋め込み成長に際し、電流ブロツク
層となるp−InP不純物拡散層306とn−InP
電流ブロツク層309のp−n接合はInGaAsP
活性層307のま横に形成されており、
InGaAsPBH−LDのもれ電流の防止、したがつて
温度特性の改善に特に有効である。最後に第3図
4に示すように得られた多層膜ウエフアを通常の
方法により、8μmの幅でp−InP第2クラツド
層310に達する深さまで選択Zn拡散層312
を形成した後p側にAuZnオーミツク電極31
3、n側にAuGeNiオーミツク電極314を形成
し(110)面がフアブリ・ペロー共振器面となる
ようにへき開してInGaAsP BH−LDを作製す
る。 FIG. 3 shows a cross-sectional view showing a method of manufacturing a preferred embodiment of the present invention. First , in FIG. 3, an n-InP buffer layer 302 (Te doped, thickness 5 μm) is formed on an n-InP substrate 301, a non-doped In 0.70 Ga 0.30 As 0.65 P 0.35 active layer 303 ( Wavelength 1.3
As a protective mask for selective diffusion of p-type impurities, a normal InGaAsP-InP DH wafer with a p-InP cladding layer 304 (Zn doped, 0.4 μm thick) was sequentially laminated.
Deposit a SiO 2 CVD film of approximately 0.3 μm. A photoresist stripe with a width of 4 .mu.m is formed along the <011> direction by a conventional photolithography method, and this is used as a mask for etching using hydrofluoric acid, leaving a selective diffusion protection mask 305. Next, Zn is diffused as a p-type impurity to a depth of approximately 1.2 μm to form a p-type impurity.
A shaped diffusion layer 306 is formed. At this time, as shown in the figure, the lower part of the selective diffusion protection mass 305 has a width of 2 to 3 cm.
An undiffused layer of μm will remain. Next, in FIG. 3, using the selective diffusion protective mask 305 as an etching mask, only the p-InP epitaxial layer is etched using a mixed etching solution of hydrochloric acid:H 2 O=4:1, which is a selective etching solution for InP. Etching. After that, the S i C 2 mask was removed and further etching was performed using bromomethyl etching solution.
By etching 0.2 to 0.3 μm, the height including the active layer 307 of BH-LD is 0.6 μm as shown in the figure.
A mesa 308 of m is formed. At this stage, as shown in the figure, there is a p
A type impurity diffusion layer is formed. Next, Figure 3
Embedded growth is performed at As mentioned above, the buried growth is performed under the growth conditions as shown in FIG. 2b. That is, the n-InP current blocking layer 309
(Te doped flat part thickness 0.4 μm) was grown on the area other than the top surface of the mesa stripe, and then a p-InP buried layer 310 (Zn doped flat part thickness 1.5 μm) was continuously laminated on the entire surface, and n-InGaAsP Cap layer 3
11 (Te doped, 0.5 μm thick) is deposited to finish the growth. During buried growth, the p-InP impurity diffusion layer 306 and n-InP which become the current blocking layer are
The p-n junction of the current blocking layer 309 is InGaAsP.
It is formed next to the active layer 307,
It is particularly effective in preventing leakage current in InGaAsPBH-LDs and therefore improving temperature characteristics. Finally, as shown in FIG. 3, the obtained multilayer film wafer is coated with a selected Zn diffusion layer 312 with a width of 8 μm and a depth reaching the p-InP second cladding layer 310.
After forming AuZn ohmic electrode 31 on the p side
3. Form an AuGeNi ohmic electrode 314 on the n-side and cleave it so that the (110) plane becomes the Fabry-Perot cavity plane to fabricate an InGaAsP BH-LD.
第4図はこのようにして製作した本発明の実施
例の斜視図である。n−InP基板401にp−
InP不純物拡散層404があらかじめ設けられて
いる。n−InP電流ブロツク層405は図に示し
たようにメサ上部を除いた部分に成長している。
p形不純物拡散層408をメサ上部のみn−
InGaAsPキヤツプ層407をつきぬけてp−InP
第2クラツド層406に達するように形成するこ
とにより、電流はInGaAsP活性層402部分の
みに有効に流れることになる。電流ブロツク層と
なるp−InP拡散層404とn−InPブロツク層
405のp−n接合はInGaAsP活性層402の
真横に形成されており、これは最初に述べたよう
にInGaAsP BH−LDのもれ電流の防止、すなわ
ち温度特性の改善に特に有効である。この
InGaAsP BH−LDにp側を正、n側を負とする
バイアス電圧を加えるとInGaAsP活性層402
の部分はpn接合の順バイアスであるためこの領
域で発光再結合を生じるが、その他の領域は大部
分がpnpn接合であるため負性抵抗特性を示し、
ターンオン電圧以下では電流がほとんど流れな
い。したがつて電流は活性層402に集中して流
れるため20mA程度の低い発振しきい値電流が得
られた。本発明の製造方法においては活性層40
2よりも深く形成するp形不純物の選択拡散、お
よび選択拡散保護マスクを用いてInGaAsP活性
層までを選択エツチングしてメサ上部以外に電流
ブロツク層を成長させることにより活性層の真横
にnpn逆バイアス層が自動的に形成されるため
BH−LDにおけるもれ電流が低減され、したがつ
て発振しきい値電流の温度特性のすぐれたBH−
LDが歩留り良く得られた。 FIG. 4 is a perspective view of an embodiment of the present invention manufactured in this manner. p- to n-InP substrate 401
An InP impurity diffusion layer 404 is provided in advance. As shown in the figure, the n-InP current blocking layer 405 is grown except for the upper part of the mesa.
The p-type impurity diffusion layer 408 is n-
p-InP passes through the InGaAsP cap layer 407.
By forming it so as to reach the second cladding layer 406, the current effectively flows only through the InGaAsP active layer 402 portion. The p-n junction between the p-InP diffusion layer 404 and the n-InP blocking layer 405, which serve as current blocking layers, is formed right next to the InGaAsP active layer 402, and as mentioned at the beginning, this is also the case with the InGaAsP BH-LD. This is particularly effective in preventing leakage current, that is, improving temperature characteristics. this
When a bias voltage with positive on the p side and negative on the n side is applied to the InGaAsP BH-LD, the InGaAsP active layer 402
Since the region is a forward bias of the pn junction, radiative recombination occurs in this region, but the other regions are mostly pnpn junctions and exhibit negative resistance characteristics.
Almost no current flows below the turn-on voltage. Therefore, since the current flows concentratedly in the active layer 402, a low oscillation threshold current of about 20 mA was obtained. In the manufacturing method of the present invention, the active layer 40
By selectively diffusing p-type impurities to a depth deeper than 2, and by selectively etching up to the InGaAsP active layer using a selective diffusion protection mask and growing a current blocking layer in areas other than the top of the mesa, an npn reverse bias is created right next to the active layer. Because the layers are formed automatically
The leakage current in the BH-LD is reduced, and therefore the BH-LD has excellent temperature characteristics of the oscillation threshold current.
LD was obtained with good yield.
本発明の実施例では活性層として1.3μmの組
成のIn0.70Ga0.30As0.65P0.35を用いているが、これ
に限定されることなくInP基板に格子整合した
In1-xGaxAs1-yPy混晶(0<x<1,0y
1)の発光波長範囲として1.1μmから1.7μmの
間のどの波長の結晶であつてもかまわない。また
電流ブロツク層としてn−InP層(x′=0,y′=
1)を用いたが、この層は活性層に電流を集中さ
せるという機能をもてばよいので活性層よりもエ
ネルギーギヤツプの大きなn−
In1-x′Gax′As1-y′Py′層、すなわち活性層
In1-xGaxAs1-yPyに対して0x′<x,y<y′
1を満たすようなn−In1-x′Gax′As1-y′Py′層、あ
るいは半絶縁性のIn1-x′Gax′As1-y′Py′層であつて
もさしつかえない。p形InP埋め込み層は活性層
のエネルギーギヤツプとは無関係にp形
In1-x″Gax″As1-y″Py″(0x″<1,0<y″
1)層を用いてもさしつかえない。 In the embodiment of the present invention, In 0.70 Ga 0.30 As 0.65 P 0.35 with a composition of 1.3 μm is used as the active layer, but the invention is not limited to this ;
In 1-x Ga x As 1-y P y mixed crystal (0<x<1,0y
As for the emission wavelength range of 1), the crystal may have any wavelength between 1.1 μm and 1.7 μm. In addition, an n-InP layer (x'=0, y'=
1) was used, but this layer only needs to have the function of concentrating current in the active layer, so an n- layer with a larger energy gap than the active layer is used.
In 1-x ′Ga x ′As 1-y ′P y ′ layer, i.e. active layer
In 1-x Ga x As 1-y P 0x′<x, y<y′ for y
1 or a semi-insulating In 1 -x ′Ga x ′ As 1 - y ′P y ′ layer. I can't help it. The p-type InP buried layer is p-type regardless of the energy gap of the active layer.
In 1-x ″Ga x ″As 1-y ″P y ″(0x″<1,0<y″
1) It is okay to use layers.
本発明はInGaAsP BH−LD の温度特性を良
好にするための電流ブロツク層が再現性よく得ら
れる製造方法であり、したがつてInGaAsP BH−
LDの製作歩留りが大幅に向上できるという特徴
を有する。 The present invention is a manufacturing method that can obtain a current blocking layer with good reproducibility to improve the temperature characteristics of InGaAsP BH-LD.
It has the characteristic that the manufacturing yield of LDs can be significantly improved.
第1図は従来例のInGaAsP BH−LDの斜視
図、第2図はメサ状基板をInP層で埋める場合の
成長形状を示す図、第3図は本発明による製造方
法を示すための断面図、第4図は本発明の製造方
法により得られたBH−LDの斜視図である。
図中、101はn−InP基板、102はn−
InPバツフア層、103はInGaAsP活性層、10
4はp−InPクラツド層、105はp−InGaAsP
電極層、106はp−InP電流ブロツク層、10
7はn−InP電流ブロツク層、108はn−
InGaAsP層、109はSiO2膜、110はp形オ
ーミツク電極、111はn形オーミツク電極、2
01は(100)InP基板、202はInPエピタキシ
ヤル成長層、308はメサストライプ、310は
p−InP第2クラツド層、311はn−GaInAsP
層、312はp形不純物選択拡散層、313は
AuZnオーミツク電極、314はAuGe−Niオーミ
ツク電極、402はIn0.70Ga0.30As0.65P0.35活性
層、404はp−InP不純物拡散層、405はn
−InP電流ブロツク層である。
Figure 1 is a perspective view of a conventional InGaAsP BH-LD, Figure 2 is a diagram showing the growth shape when a mesa-shaped substrate is filled with an InP layer, and Figure 3 is a cross-sectional view showing the manufacturing method according to the present invention. , FIG. 4 is a perspective view of a BH-LD obtained by the manufacturing method of the present invention. In the figure, 101 is an n-InP substrate, 102 is an n-
InP buffer layer, 103 is InGaAsP active layer, 10
4 is p-InP cladding layer, 105 is p-InGaAsP
Electrode layer, 106, p-InP current blocking layer, 10
7 is an n-InP current blocking layer, and 108 is an n-InP current blocking layer.
InGaAsP layer, 109 is S i O 2 film, 110 is p-type ohmic electrode, 111 is n-type ohmic electrode, 2
01 is (100) InP substrate, 202 is InP epitaxial growth layer, 308 is mesa stripe, 310 is p-InP second clad layer, 311 is n-GaInAsP
312 is a p-type impurity selective diffusion layer; 313 is a p-type impurity selective diffusion layer;
AuZn ohmic electrode, 314 is AuGe-Ni ohmic electrode, 402 is In 0.70 Ga 0.30 As 0.65 P 0.35 active layer , 404 is p - InP impurity diffusion layer, 405 is n
-InP current blocking layer.
Claims (1)
る第1の導電形のInP基板に少くとも
In1-xGaxAs1-yPy(0<x<1,0y1)活
性層を含む半導体層を積層させた多層膜構造ウエ
フアの表面に<011>方向に沿つたストライプ状
の拡散保護マスクを形成した後第2の導電形不純
物を前記In1-xGaxAs1-yPy活性層よりも深く選択
拡散する工程と、選択拡散されたp形不純物領域
の一部あるいは全体を前記In1-xGaxAs1-yPy活性
層までエツチングして多層膜構造の<011>方向
に平行なメサストライプを形成する工程と、前記
メサストライプの上面のみを除いて、前記第1の
導電形のIn1-x′Gax′As1-y′Py′(0x′<x,y<
y′1)電流ブロツク層を積層させた後にp形
In1-x″Gax″As1-y″Py″(0x″<1,0<y″
1)埋め込み層を全面にわたつて連続して積層さ
せる成長工程とを含むことを特徴とする埋め込み
ヘテロ構造半導体レーザの製造方法。1 At least an InP substrate of the first conductivity type whose plane orientation is (100) or near (100)
In 1-x Ga x As 1-y P y (0<x<1,0y1) Striped diffusion protection along the <011> direction on the surface of a multilayer structure wafer in which semiconductor layers including an active layer are laminated. After forming the mask, a step of selectively diffusing the second conductivity type impurity deeper than the In 1-x Ga x As 1-y P y active layer, and partially or whole of the selectively diffused p-type impurity region are performed. A step of etching up to the In 1-x Ga x As 1-y P y active layer to form a mesa stripe parallel to the <011> direction of the multilayer film structure, and a step of etching the In 1-x Ga x As 1-y P y active layer to form a mesa stripe parallel to the <011> direction of the multilayer film structure; In 1-x ′Ga x ′As 1-y ′P y ′ (0x′<x, y<
y′1) P-type after laminating the current blocking layer
In 1-x ″Ga x ″As 1-y ″P y ″(0x″<1,0<y″
1) A method for manufacturing a buried heterostructure semiconductor laser, comprising the step of: 1) a growth step of continuously stacking a buried layer over the entire surface;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10968781A JPS5810883A (en) | 1981-07-14 | 1981-07-14 | Manufacture of semiconductor laser having embedded heterogeneous structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10968781A JPS5810883A (en) | 1981-07-14 | 1981-07-14 | Manufacture of semiconductor laser having embedded heterogeneous structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5810883A JPS5810883A (en) | 1983-01-21 |
| JPS6248918B2 true JPS6248918B2 (en) | 1987-10-16 |
Family
ID=14516639
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10968781A Granted JPS5810883A (en) | 1981-07-14 | 1981-07-14 | Manufacture of semiconductor laser having embedded heterogeneous structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5810883A (en) |
-
1981
- 1981-07-14 JP JP10968781A patent/JPS5810883A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5810883A (en) | 1983-01-21 |
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