JPS6248927B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal compander, and more particularly to an improved signal compander adapted to be formed as an integrated circuit (IC).

As is well known, compander systems compress the range of motion of an audio signal before transmitting or recording the signal onto a range-limiting medium, and reduce the range of motion of the transmitted or recorded signal during subsequent readings. Stretching to give the signal a greater range of motion than that provided by the transmission or recording medium.

One such compander that has been commercially successful and widely accepted is David E. Blackmer's U.S. patent no.
No. 3,789,143 ``Compander with control signal having a logarithmic relationship to the instantaneous effective value of the input signal''. Typically, this system uses two basic elements: a gain control module, a unit containing a voltage controlled amplifier (VCA), and a signal detector used to generate the voltage control signal to the amplifier. . Voltage controlled amplifier January 30, 1973
Preferably, it is of the type described in David E. Blackmer's US Pat. No. 3,714,462, entitled "Multiplication Circuit." The detector is covered by a U.S. patent issued by David E. Blackmar dated August 1, 1972.
It is desirable to include a circuit arrangement for detecting the instantaneous rms value of the input signal, such as that described in 3681681 ``Rsm value circuit with bipolar logarithmic converter''.

Generally, voltage controlled amplifiers provide a controlled gain to the input signal to compress the dynamic range of the signal as it is transmitted or recorded, or to expand the dynamic range of the signal when read. The amount compressed or expanded (how much signal is compressed or expanded) depends on the preselected compression or expansion factor. In the compander system of US Pat. No. 3,789,143, the control signal is derived from a logarithmic function of the instantaneous rms value of the input signal to provide expansion or compression as a function of the instantaneous rms value of the input signal. Other detection methods such as peak detection or average detection can also be used.

It is a general object of the present invention to provide an improved compander system that is easy and inexpensive to manufacture.

It is also an object of the present invention to provide an improved compander that can be easily manufactured into an IC shape.

It is also an object of the present invention to provide a compandor which is an improvement over the compander described in US Pat. No. 3,789,143.

These and other objects provide a gain control signal to a gain control module to provide an improved pressure control module having an improved gain control module and an improved signal detector for compressing or expanding the information signal according to the amplification setting of the unit. This is accomplished by a stretcher system.

FIG. 1 shows a basic compander system including a gain control module 10 and a detector 12 as described in U.S. Pat. No. 3,789,143. Generally, the gain control module receives an input signal E applied to the voltage input terminal 14.
The gain of _io is adjusted as a function of the control signal provided by detector 12. The gain applied according to the gain setting of module 10 provides gain or attenuation of the input signal to provide output signal E _put at output terminal 16 . To perform the compression, the detector 12 is configured in a feedback configuration (the detector receives the output signal E _pu at the output terminal 16).
_t ) or in a feed-forward configuration (the detector 12 detects the input signal E _io at the voltage input terminal 14
1), both configurations are shown in FIG. A feedforward configuration is typically used to perform the decompression. In either configuration, the detector provides a control signal in response to the detection signal.

In FIG. 2, the gain control module 1 of the embodiment
0 has an input stage 18 whose input is connected to the voltage input terminal 14 and whose output is connected to the VCA cell 20
connected to. The output of cell 20 is connected to system output terminal 16 and is properly biased by bias generator 22.

The illustrated detector 12 is connected to a module 10 in a feedforward configuration, which has a rectifier 24 that detects an input signal at a voltage input terminal 14 and rectifies the input signal. The output of rectifier 24 is connected to a logarithmic section 26 which provides an output signal as a logarithmic function of the output of rectifier 24. Logarithmic waveform generator 28 converts the logarithmic signal output of logarithmic section 26 into a substantially DC signal, which is then passed to buffer amplifier 3.
Added to 0 input. The output of amplifier 30 is
It is connected to the control signal input of the VCA cell 20.

The gain control module shown in FIGS. 3A and 3B includes an input stage 18 (FIG. 3A) and a VCA cell 2.
0 (Figure 3B) and bias generator 22 (Figure 3B).
(Fig. 3A) and a power source 32 (Fig. 3A).

1 and 2, except that, in particular, in FIG. 3A, current input terminal 14A is modified to receive input current I _io as a function of input voltage E _io in a manner well known in the art. This is the same as the voltage input terminal 14 of . Input terminal 14A is input stage 1
8 and to the input of VCA cell 20. The input stage 18 is described in detail in the co-pending application (Attorney's Abstract DBX-46) filed by the applicant of the present invention. In particular, input terminal 14A is connected to the input terminal of stage 18, indicated by junction 40. Junction 40 is connected to the base of buffer transistor 42. The latter has an emitter connected to the input 44 of the differential amplifier, generally indicated at 46, and a current generator that generates a current through transistor 42 to reduce the amount of bias current that stage 18 draws from input terminal 14A. It has a collector connected to it.

In particular, the current generator 48 is a transistor 50,5
2, 54, 56 and 58. The base of transistor 50 is connected through junction 40 to the base of transistor 42, and the bases of transistors 52 and 54 are connected together. The emitter of transistor 54 is connected to the collector of transistor 42, which is connected to the base and collector of diode-connected transistor 58. The collector of transistor 52 is connected to the emitter of transistor 50, which is connected to the collector and base of diode-connected transistor 56. The emitter of transistor 58 and the collector of transistor 50 are grounded together, and the emitter of transistor 52 and the collector and base of transistor 56 are connected to the collector of transistor 60. The base of the latter is connected to the base and collector of transistor 62, and its emitter, along with the emitter of transistor 60, is connected to upper rail voltage terminal 64 (shown in FIG. 3B).

Differential amplifier 46 includes a pair of differential elements made up of transistors 66 and 68. The base of transistor 66 is connected to input 44, the collector is connected through resistor 70 to a current mirror shown generally at 72, and the emitter is connected to ground through capacitor 74 and through resistor 76. via to junction point 78. The base of transistor 68 is grounded at junction 80, the collector is connected to current mirror 72, and the emitter is connected to the collector and base of diode-connected transistor 82. The emitter of transistor 82 is connected to junction 78 through resistor 84. Current mirror 72 is provided by transistors 86 and 88 whose bases are connected together and whose emitters are connected to upper rail voltage terminal 64 through resistors 90 and 92, respectively.
connected to. The collector of transistor 86 is connected to resistor 86 and capacitor 94.
connected to the base via. The collector of transistor 88 is directly coupled to the base and collector of transistor 68. The output of differential amplifier 46 is provided to a junction 96 between the collector of transistor 66 and resistor 70. Junction 96 is connected to the base of transistor 98, the collector is connected to the collector and base of transistor 62 and the base of transistor 60, and the emitter is connected to transistor 100 shown in FIG. 3B. The emitter of transistor 98 and junctions 78 and 44 are suitably connected to power supply 32.

Our related application (Agent docket no. DBX-46)
Transistor 42 and current generator 48 reduce the input bias current drawn from the input current at terminal 14A without affecting the gain-bandwidth product of the stage. In particular, bipolar transistor 42 provides a buffer between terminal 14A and the remainder of stage 18. Current generator 48 generates a current to bipolar transistor 42 to
stage 18 without affecting the gain-bandwidth product of 8.
reduce the amount of bias current flowing into the remainder of the circuit. Furthermore, our related application (Attorney docket no. DBX-46)
As described in , the use of the bipolar transistor 42 allows the circuit technology to be easily adapted to IC implementation. Capacitor 94 and resistor 7
0 is used to supply 0 to the transfer characteristic of stage 18;
(0 defines the value of the complex frequency at which the circuit's transfer function is 0) VCA cell 20 provides an effect on the stability of the circuit by canceling the 90° phase shift caused by the feedback loop of the stage. By connecting the diode 82 to the emitter of the transistor 68 and matching the impedance of the resistor 76 with the combined impedance of the diode 82 and the resistor 84, the power supply 3
2 reduces the noise contribution at the output of junction 96. Finally, the addition of capacitor 74 creates a zero in the transfer characteristics of the amplifier and stage, canceling out the pole caused by the base-emitter parasitic capacitance of transistor 66. (A pole is defined as the complex frequency value for which the circuit's transfer function is infinite.) In FIG. 3B, the collector of transistor 100 is connected to top rail voltage terminal 64;
The emitter is connected to a junction 112 through a resistor 110. The latter forms one bias terminal of cell 20.

Cell 20 is described in detail in a related application (Attorney docket no. DBX-34 CIP) filed by David E. Blackkumar and assigned to the applicant, which is a U.S. Pat. This is a partial continuation of Application No. 131220. Junction 112 is connected through a resistor 114 to the collector of a second order logarithm transistor 116. The emitter of second order logarithm transistor 116 is connected to the emitter of first order logarithm transistor 118.
The collector of transistor 118 is connected to junction 120 and then to input terminal 14 of the module.
Connected to A. Junction 120 is also connected to the collector of primary logarithm transistor 122;
The emitter is connected to the emitter of a second order logarithm transistor 124. The collector of transistor 124 is connected to junction 128 through resistor 126. Junction 128 forms the second bias terminal of cell 20 and thus connects resistor 114 and
The first order logarithm transistor 116, the first order logarithm transistor 118, 122, and the second order logarithm transistor 1
24 and resistor 126 form the circuit load for bias generator 22. Junction 112 is also connected through a resistor 130 to the collector of a secondary inverse transistor 132 whose emitter is connected to the emitter of an inverse transistor 134 . The collector of transistor 134 is connected to junction 136, which in turn is connected to the module's current output terminal 16A. Current output terminal 16A thus provides the module's current output I _put . _Iput can be easily converted into a voltage _Eput using known methods. Junction 136 is also connected to the collector of a primary inverse transistor 138 and its emitter is connected to the emitter of a secondary inverse transistor 140. The collector of secondary transistor 140 is connected to junction 128 through resistor 142. resistor 130, secondary inverse transistor 132, and primary inverse transistor 134,1
38, a second-order inverse transistor 140, and a resistor 142 form another circuit for bias generator 22 between junctions 112 and 128. 1
The base of the first-order logarithmic transistor 122 is connected to the control signal terminal 144 along with the base of the first-order antilogarithm transistor 134, and is connected to the control signal terminal 144 in FIGS. 4A and 4B.
A control signal is received from the terminal of the detector shown in the figure.
The bases of transistors 118 and 138 may be connected to terminals 146 and 148, respectively, to receive and adjust current between positive and negative input signals to ensure gain symmetry as described below. Each secondary transistor 116 and 13
The bases of each secondary transistor 124, 146 are cross-connected to the respective collectors of the other transistors 124, 146.
The bases of each are cross-connected to other collectors.

Application by David E. Blackkumar (Representative)
Each primary logarithm transistor 118 and 122
are the second-order logarithm transistors 116 and 124
are connected to form two compound logarithm units and are placed in separate feedback paths between the input and output of the husbandry stage 18. Primary transistor 118 is PNP
The primary transistor 122 is a transistor.
Each transistor 11 is an NPN transistor.
8 and 122 are connected to secondary transistors of opposite conductivity. They thus operate as "compound logarithmic transistors", each providing a logarithmic signal as a logarithmic function of the corresponding one of the two polarities of the input signal at terminal 14A.

As will be described below, the control signal at terminal 144 is a logarithmic function of the instantaneous effective value of the input signal at terminal 14A. Primary transistors 122 and 13
A control signal is added to the logarithmic signal via the base of 4. 1 each primary reciprocal transistor of opposite conductivity
34 and 138 are connected to second order reciprocal transistors 132 and 140, respectively, of opposite conductivity;
Each forms two composite counters for different polarities of the input signal. transistor 13
2, 134, 138, and 140 act as "inverse transistors" to provide inverse signals as an inverse function of the sum of the corresponding log signal and control signal. Logarithmic transistors 116, 118 and inverse transistors 132, 134 thus form one log-inverse transmission path for unipolarity of the input signal, and logarithmic transistors 122, 12
4 and inverse transistors 138, 140 provide a second log-inverse transmission path for input signals of the other polarity.

It is desirable that the V _be /I _C transfer characteristics of all NPN transistors be matched, as described in a related application by David E. Blackmar (attorney docket no. DBX-34 CIP). It is also desirable that all PNP transistors are matched to each other. The secondary transistor provides a signal modification device that is placed in the log-inverse path to reduce distortion due to the base and emitter resistivity of the log and inverse transistors. Corrections are made by comparing the input and output (inverse) currents from each log-inverse path. In particular, the correction signal is derived from the voltage difference that develops between the collector voltages of the crossed secondary transistors of each log-inverse path. The modification signal reduces distortion due to the base and emitter inherent parasitic resistances of the transistors of cell 20 at output terminal 16A. each composite transistor pair 116,
118; 122, 124; 132, 134; 13
8,140 and the emitter resistance mismatch can be easily compensated for by adjusting each resistor 114, 126, 130, and 142 individually.

Bias generator 22 connects resistance points 112 and 12
8 and properly connected to transistor 11
A bias signal is provided to a circuit load including transistors 6, 118, 122, and 124 and a circuit load including transistors 132, 134, 140, and 142. Generator 22 is described in detail in the co-pending application (Attorney's Abstract no. DBX-45) filed by the applicant of the present invention. Generator 22 is designed to provide a bias voltage across junctions 112 and 128 of cell 20 and is programmed by an input current to generator 22 from supply source 32 to determine the resulting logarithmic transistor bias current and The bias currents of the opposite transistors are equal or proportional to track the input current regardless of temperature.

In particular, generator 22 includes a first resistor 150, one end of which is connected to junction 112 and the other end of which is connected to junction 1.
54. Resistor 152 is at junction 1
54 and 128 to resistor 150. Junction 112 is an NPN transistor 156
It is also connected to the collector, and the emitter is PNP
Connected to the emitter of transistor 158. The V _be /I _C transfer characteristics of the NPN transistor 156 are as follows:
and 138, transistor 1
Similarly, 58 is the PNP transistor 11 of the cell 20.
8, 124, 134 and 140. The base of transistor 158 is at junction 154
The collector of the transistor 160 is connected to the base of the transistor 160. The emitter of transistor 160 is connected to the base of transistor 162. The collectors of transistors 160 and 162 are connected together to the base and collector of transistor 156 and to junction 112. The emitter of transistor 162 is connected to junction 128. The base of transistor 158 is connected to the anode of diode 164 and the cathode is connected to the base of transistor 160. The base of transistor 160 is connected to a constant current source provided by power supply 32 .

Our simultaneous application (agent's abstract no. DBX-
45), from the power supply 32 to the collector of the transistor 158 and the transistor 16.
The current into the 0 base junction is the programming input current to the generator. The collector current of transistor 158 (ignoring the base current of transistor 158) is the same as that of both transistors 156 and 15.
The current flowing through the base-emitter junction of 8 is equally dependent on it. transistors 160 and 16
2 forms a +1 follower with a voltage gain of 1 and a very high current gain.

Operationally, the current from power supply 32 to the base of transistor 60 is constant, and junctions 112 and 12
Establish the bias voltage value applied to 8. The amount of current flowing through the emitters of transistors 156 and 158 establishes a temperature dependent voltage across resistor 150. The collector current of transistor 158 is approximately equal to the emitter current of transistor 158 and equal to the input current of generator 22, so the error current input to the base of transistor 160 is approximately zero. transistors 156 and 158
If the emitter current of transistor 160 changes,
and 162 are compensated to adjust for errors. In particular, as the emitter currents of transistors 156 and 158 increase, the voltage across resistor 150 increases. The collector current of transistor 158 then increases. The constant input current from power supply 32 creates an error current equal to the difference between the collector current of transistor 158 and the input current, and the voltage value on the base of transistor 160 decreases relative to the voltage value at junction 112. This causes resistor 152
and 150 decreases, reducing the voltage across the base-emitter junctions of transistors 156 and 158, causing the collector current of transistor 158 to equal the input current from power supply 32 and the base current of transistor 160 to zero. The emitter currents of transistors 156 and 158 decrease until .

Conversely, if the emitter currents of transistors 156 and 158 decrease, the voltage across resistor 150 decreases, and the collector current of transistor 150 decreases, an error current equal to the difference between the collector current of transistor 158 and the input current flows through transistor 16.
Added to base of 0. This increases the voltage level at the base relative to junction 112. This increases the current flowing through resistors 152 and 150 and the voltage across the base-emitter junctions of transistors 156 and 158. This makes the collector current of transistor 158 equal to the input current from power supply 32 and transistor 16
transistor 156 until the error current of 0 becomes 0.
and 158 emitter current increases.

A temperature dependent voltage is therefore developed across resistor 150, which is the sum of the voltage drops across the base-emitter junctions of transistors 156 and 158. The temperature voltage drop across each circuit load between junctions 112 and 128 of cell 20 is the sum of the voltages across the base-emitter junctions of the two matched NPN and PNP transistors 156 and 158, respectively. varies as a function of

Therefore, in order to match the voltage-current-temperature characteristics of generator 22 to the voltage-current-temperature characteristics of each circuit load between junctions 112 and 128, it is necessary to multiply the voltage developed across resistor 150 by a scalar 2. . This changes the resistance value of resistor 152 to resistor 150
The current generated in resistor 150 is sent to resistor 152 in response to the voltage generated by transistors 156 and 158 (ignoring the base current of transistor 158), generating the same voltage. It will be done. Resistors 150 and 1
The voltage across cell 20 is applied to each other.
A bias signal is provided across each circuit load between junctions 112 and 128 of the circuit. As the gain control module is subjected to ambient temperature changes, changes in the base-emitter voltage drops of transistors 156 and 158 will affect each PNP and NPN in each circuit load.
Match the same change in the base-emitter voltage drop of the transistor pair.

In FIG. 3A, current source 32 is transistor 1
70, the collector of which is connected to the bias generator 22
is connected to the base of transistor 160. The emitter of transistor 170 is resistor 17
2 to junction 174. Transistor 170 is cascaded with transistors 176 and 178 by connecting their bases together. The collector of transistor 176 is connected to the emitter of transistor 177. The base of transistor 177 is grounded, and the collector is connected to the emitter of transistor 98.
The collector of transistor 178 is connected to junction 78 of stage 18. The emitters of transistors 176 and 178 are coupled directly to junction 174. transistors 170, 176 and 178
The base of transistor 1 is connected to transistor 1 through resistor 180.
82 and the collector of transistor 184. The collector of transistor 182 is coupled directly to junction 44 of stage 18. The emitter of transistor 182 is transistor 17
It is connected to the emitter of 0. transistor 1
The base of 70, 176 and 178 is resistor 18
6 to the base of transistor 184. The base of transistor 184 is suitably connected two diode drops below ground by connecting the bases through diode-connected transistors 188 and 190. Junction point 1
74 is connected to the base of transistor 192;
It is also connected to a terminal 196 via a resistor 194 . The emitter of transistor 192 is also terminal 1.
96 , the collector of which is connected to junction 128 of cell 20 through resistor 198 . Terminal 196 is connected to voltage source 20 via external resistor 200.
2 can be properly connected. The nature of the power supply 32 is such that a constant current is always supplied to the collector of the transistor 170, and the bias generator 22 operates in accordance with the teachings of our co-pending application (Attorney's Abstract no. DBX-45).

Details of the detector 12 are shown in FIGS. 4A and 4B. In particular, rectifier 24 (Figures 4A and 4B)
In addition to the logarithmic section 26 (FIGS. 4A and 4B), the logarithmic waveform generator 28 (FIG. 4B), and the buffer amplifier 30 (FIG. 4B), the detector also includes a current source 30 (FIG. 4B).
0,302 (shown in FIGS. 4A and 4B, respectively) and voltage source 304 (FIG. 4A).

In FIG. 4A, voltage input terminal 14 is connected through capacitor 310 to resistor 312, which in turn is connected to current input terminal 14B (which receives current input signal _Iio ). Current input terminal 14B is connected to the input of rectifier 24.

Rectifier 24 includes an operational amplifier stage 320 and a bias generator 324. Rectifier 24 is constructed in accordance with the teachings of the David R. Welland co-pending application patented to the assignee of the present invention.

In particular, the current input terminal 14B is the terminal 33 of the stage 320.
0 input junction. Junction point 330
is connected to the base of a transistor 332, whose collector is grounded and whose emitter is connected to the collector of a transistor 334. Junction 330 is transistor 33
6, the emitter of transistor 336 is connected to junction 338 and the collector is connected to the emitter of transistor 340.
The base of transistor 340 is transistor 33
4, and its collector is connected to the emitter of transistor 342. The base of transistor 342 is connected to voltage source 304 along with the emitter of transistor 334, and the collector of transistor 342 is connected to the collector of transistor 344 and the base of transistor 346. The base of transistor 344 is connected to the base and collector of transistor 348;
The emitter, along with the emitter of transistor 348, is connected to a positive voltage rail shown at 350. The collector of transistor 348 is connected to the base of transistor 346 via capacitor 352. The collector of transistor 348 is also connected to the collector of transistor 354, with its base connected to ground at 355 and its emitter connected to junction 338. transistor 34
The collector of transistor 6 is connected to the positive voltage rail 350 and the emitter is connected to the base of transistor 356 and directly to current source 302. The collector of transistor 356 is connected to the positive voltage rail 350, the emitter is connected to the anode of a first diode 358, and the cathode is connected to the anode of a second diode 360. The cathode of diode 360 is connected to stage 32 connected to rectifier cell 322.
0 output, and the cell is connected to the concurrent application of David R. Welland (Attorney's Abstract no. DBX-
44) in the feedback path of the amplifier stage 320 shown in FIG.

Cell 322 has three transistors 380, 38
2 and 384. transistor 38
0 is a diode connected NPN transistor whose base is connected to the collector via a resistor 386 to form the input 388 of the cell 322. Input 388 is connected to the input of amplifier stage 320 at junction 330. Transistor 382 is also an NPN transistor with a collector connected to the cathode of diode 398 and an anode connected to output 400 of cell 388. The emitter of transistor 382 is connected to the emitter of transistor 380, and its base is grounded via resistor 390. transistor 3
The base of 82 is also connected to terminal 392 and then through resistor 394 to potentiometer 396. potentiometer 39
6 supplies a variable current to the base of transistor 382 and on the other hand transistors 380 and 382 as described in the patent application (DBX-44).
On the other hand, transistor 384 ensures gain symmetry between the current paths provided. Finally, the emitters of transistor 384 and the NPN transistor are connected to the input 388 of the cell, the bases are connected to the cathode of diode 360 of stage 320, and the collectors are connected to the output 400 of the cell. The loop transmission of stage 320 through the path containing transistor 380 and the path containing transistor 384 as described in the patent application (DBX-44) limits to unity gain and rectifiers as disclosed in U.S. Pat. No. 4,097,767. Eliminates the stability problems associated with unlimited loop transmission in rectifying positive input signals by.

A bias generator 324 provides a bias voltage between the base of transistor 384 and the combined emitters of transistors 380 and 382, as described in the patent application (DBX-44). Generator 324 includes a signal generating device that generates a bias voltage between points 410 and 412. A bias signal is applied across a first impedance load having a first resistive device in the form of resistor 440 . Resistor 440 is connected to a second resistor device, resistor 442, which forms part of a second impedance load connected between the base of transistor 384 and the combined emitters of transistors 380 and 382. are doing. Resistors 440 and 442 as described below.
By setting the same resistance value, the transistor 38
A bias voltage is applied between the bases of transistors 380 and 382 and the combined emitters of transistors 380 and 382.

In particular, the signal generator includes a first current source including transistors 414 and 416 that provide a reference current IB, and a transistor 418 that provides a reference current IA.
a second current source including a pair of reference transistors 4;
20 and 422 and a second pair of reference transistors 424 and 426. The emitter of transistor 414 is connected to the emitter of transistor 416, and the emitter of transistor 418 is grounded. The collector and base of transistor 414 are connected to current source 302 and the bases of transistors 416 and 418.
The collector of transistor 416 is transistor 4
34 and the collector is connected to the logarithmic part 26
The emitter is connected to the base and collector of a diode-connected transistor 436. The latter emitter is connected to point 412. The collector of transistor 416 is also connected to the collector of transistor 420, its base is connected to point 410, and its emitter is connected to the collector and base of diode-connected transistor 422. The emitter of transistor 422 is connected to negative voltage rail 450 and resistor 428. The collector of transistor 418 is connected to the base and collector of diode-connected transistor 432, and the collector is connected to point 410. Point 410 is diode-connected transistor 4
24 and its emitter is connected to the base and collector of diode-connected transistor 426. The emitter of transistor 426 is connected to resistors 428 and 43.
0 common junction. Next, resistor 4
30 is connected to point 412.

The base of transistor 432 is transistor 4
38 and its emitter is connected to point 412 through a resistor 440. The collector of transistor 438 is connected to the base and collector of diode-connected transistor 444 .
The emitter of is connected to resistor 442 and in turn to the base of transistor 384 of cell 322. The collector and base of transistor 444 are connected to the base of transistor 446, and the emitter is connected to transistors 380 and 38.
2 and the collector is connected to the negative voltage rail 450 of current source 302. Patent application (agent's abstract no.
DBX-44), transistors 420, 422, 424 and 426 are all
It is an NPN transistor, and its V _be /I _C characteristic is NPN transistor 380, 3 of rectifier cell 322.
It matches the V _be /I _C characteristics of 82 and 384. Similarly, transistors 432 and 438 are of the same conductivity type and have matching V _be /I _C characteristics, and transistors 444 and 446 are of the same conductivity type and have matching V _be /I _C characteristics.

Rectifier 24 operates as described in the co-pending application of David E. Welland (Attorney's Abstract no. DBX-44). Generally, when the input current at junction 14A is negative, diode 36 of stage 320
The output signal at the cathode of 6 is positive. This provides negative feedback to the base-emitter junction of transistor 384 of cell 322. This causes current to flow from the output of rectifier terminal 400 through the collector-base junction of transistor 384 to input terminal 330 of stage 320. Transistors 380 and 382 are substantially non-conducting because their base-emitter junctions are reverse biased.

For a positive input current at terminal 14B, the output of stage 320 is negative and the base-emitter junction of transistor 380 is forward biased and current flows through the junction. Substantially the same mirror current flows through the collector of transistor 382, providing an inverted signal at output 400 for input signals of this polarity.

Base of transistor 384 and transistor 3
The combined emitters of 80 and 382 are biased by bias generator 324 to reduce the rotational requirements of amplifier 320 for a given performance value.

As stated in the patent application (attorney's abstract no. DBX-44), the bias voltage generated between points 410 and 412 is equal to the base-emitter voltage drop of transistor 424 plus transistor 42.
The base-emitter voltage drop of 6 is equal to the voltage drop across resistor 430. Reference current typically flowing through transistors 420 and 422
If IB is n times the reference current IA flowing through transistors 424 and 426, then the voltage across resistor 428 will be matched by subtracting it from the reference diode string (e.g., supplied by transistors 420 and 422). Such that the current flowing through the string is reduced by a factor n. The voltage across resistor 430 then subtracts it from the voltage across the reference diode string of transistors 424 and 426, and the current through the matched string is reduced by a Kth increased factor n. (Here K is the resistance ratio of resistor 430 and resistor 428.) Point 4
The voltage across 10 and 412 is the voltage drop across the diode string consisting of diode-connected transistors 424 and 426 minus the voltage drop across resistor 430, and is the voltage drop across resistor 430 and U.S. Patent Application No. 137,427, filed April 4, 1980. Transistors 424 and 426 are transistors 42 and 426 as described in (Agent's summary no. DBX-44).
0 and 422, the circulating current supplied to transistors 384 and 380 (current circulating between the base and emitter of transistor 384 and the collector and emitter of transistor 380) is less than the reference current flowing through transistors 424 and 426. The smaller the Kth value, the higher the coefficient n. Therefore, the bias voltage varies with temperature and the circulating current does not vary with such temperature changes, and the currents IA, the ratio of IB to IA and the resistor 42
Transistor 3 by setting the ratio of 8 and 430
80 collector and emitter and transistor 3
The maximum circulating current generated in the base-emitter junction of 84 is set, and the output due to this circulating current is 400
The maximum error is set.

The bias voltage across points 410 and 412 is thus equal to the desired bias voltage. The voltage developed across these points is across transistor 432.
and a first impedance load having a base-emitter junction of 438 and a resistor 440. The base of transistor 438
Forward bias the emitter junction to make it conductive. The bias voltage applied across resistor 440 thus produces a current in resistor 440 and transistor 438 causes current to flow into resistor 442 and diode-connected transistor 444. The current through the emitter of transistor 446 is set to be the same as the current IA through transistor 432, matching transistor 444 to transistor 446 and matching transistor 432 to transistor 43.
8, the mismatching of the voltage drops across each transistor 432 due to the mismatching of the currents flowing through the collectors of these transistors is offset by a similar mismatching of the voltage drops across transistors 444 and 446 due to the redundant current mismatching. . The current flowing through resistor 442 develops a bias voltage across a second impedance load consisting of resistor 442 and the base-emitter junctions of transistors 444 and 446.

Thus resistor 442 and transistor 44
The voltage across transistors 4 and 446 is equal to the required bias voltage, which is the voltage across transistors 380 and 384.
changes with temperature without affecting the circulating current of

By applying an appropriate bias voltage to the base of transistor 384 and the common emitter of transistors 380 and 382, transistor 384
base-emitter path of transistor 38
The circulating error current delivered to output 400 due to the circulating current flowing through the collector-emitter path of 0 is independent of temperature, and the maximum allowable circulating error current value at output 400 is determined by the ratio of the resistances of resistors 428 and 430, the generator Bias currents IA and IB flowing to transistors 424 and 426 of 324 and
Determined by the IA current ratio.

The current output signal of rectifier 24 at output 400 is therefore a full wave rectification of the input current at terminal 14B. Output 400 is connected to logarithm section 26.

Logarithmic part 26 (shown in Figures 4A and 4B)
includes an operational amplifier stage 451 and a logarithmic element 452. Stage 451 includes an input 454 connected to the output 400 of cell 322 of rectifier 24 . Input 454 is connected to transistors 456 and 45
It forms the connection between the bases of 8. The collector of transistor 456 and the emitter of transistor 458 are grounded. transistor 456
The emitter of is connected to the collector of transistor 458, and the emitter is connected to voltage source 304 and current source 300. transistor 45
The emitter of 8 is also connected to the base and collector of transistor 460 and the anode of diode 461. The collector of transistor 460 is connected to current source 300 and the cathode of diode 461. The emitter of transistor 460 is connected to the collector of transistor 462, its base is connected to the base of transistor 458, and the emitter is connected to resistor 464.
(shown in Figure 4B) via transistor 458.
is connected to the collector of transistor 46
The collector of 0 is connected to ground through capacitor 468 and to the base of transistor 466. The collector of transistor 466 is current source 3
Connected to 00. The emitter of transistor 466 is connected to the base of transistor 470, the collector is connected to current source 300, and the emitter is connected to the output of logarithmic element 452.

Logarithmic element 452 is connected to two diode-connected transistors 47 in a feedback loop between the input and output of stage 451.
8 and 480, and the input and output are connected to the emitter of transistor 470 and input 4, respectively.
54. In operation, the rectified current signal at input 454 always flows to rectifier 24 so that transistors 480 and 482 of logarithmic element 452 are always forward biased. Step 4
The properties of 51 and logarithmic element 452 transform the rectified signal into a signal that is a function of the square of its input signal, or more precisely, a function of the logarithm of the input signal times two. Thus, the output of terminal 476 of stage 451 is the current input terminal 14B.
represents the logarithm of the square of the current input signal.

The output of the emitter of transistor 470 of stage 451 is connected to the input of logarithmic waveform generator 28 (FIG. 4B). Logarithmic wave generator used in logarithmic domain is 1979
Patent Application No. 97901 to Robert, D'Avreux and Adams, filed November 28, 2013, to Assignee of the Invention.
listed in the number. In particular, wave generator 28 includes at least one diode-connected transistor 490. The output of the logarithmic part 26 is the transistor 490
The emitter of the transistor forms the output of the wave generator.
The output of the wave generator is properly biased by current source 302 and connected to external resistor 4 via external capacitor 492.
94 and then grounded.

As described in U.S. Patent Application No. 97901, since the output of logarithmic section 26 is a logarithmic signal, wave generator 28 operates as a low-pass wave generator and the output of the wave generator is primarily a DC signal. This DC signal is supplied to the input of buffer amplifier 30.

Amplifier 30 has a transistor 500 whose base is connected to the output of wave generator 28. The emitter of transistor 500 is connected to the base and collector of diode-connected transistor 502, and the emitter of transistor 500 is connected to the base and collector of diode-connected transistor 502.
4 base and collector. The emitter of transistor 504 is connected to junction 506 and in turn to current source 302 . The collector of the transistor 500 is the transistor 50
The emitter of transistor 508 is connected to the positive voltage rail 350 through a resistor 510. The base and collector of transistor 508 are also connected to the base of transistor 512, and the emitter is connected to current source 300 through resistor 514. The collector of transistor 512 is connected to the base of transistor 516 and the collector of transistor 518. The collector of transistor 516 is connected to positive rail 350 and the emitter is connected to current source 302 and the base of transistor 520. The collector of transistor 520 is connected to the collector and base of transistor 522, and the collector and base are connected to current source 3.
00 and the emitter is connected to rail 350. The emitter of transistor 520 is connected to the base of transistor 518, and the emitter is connected to junction 506. transistor 5
The base of 18 and the emitter of transistor 520 together form the output of detector 12. Output terminal 524 is properly biased by current source 302 and connected to terminal 144 of cell 20 of the control module shown in FIG.

Current sources 300, 302 and voltage source 304 provide the necessary bias currents and voltages to rectifier 24, logarithmic section 26, logarithmic waveform 28, and buffer amplifier 30. In particular, in FIGS. 4A and 4B, current source 300 includes four PNP transistors 60.
0, 602, 604, and 606, all of whose emitters are connected to the positive voltage rail 350. The collector of the transistor 600 is the rectifier 24
to the combined emitters of transistors 380 and 382 of rectifier cell 322. The base of transistor 600 is connected to the bases of transistors 602 and 604.
The collector of transistor 602 is connected to the collector of transistor 460 and the base of transistor 466 of logarithmic section 26 . The collector and base of transistor 604 are connected to current source 302. Finally, the base of transistor 606 is connected to the base and collector of transistor 522 of amplifier 30, with the collector connected to the logarithmic part 2
It is connected to the base of transistor 460 of No. 6.

In FIG. 4A, current source 302 includes a diode-connected transistor 620 whose collector and base form an output terminal 622. In FIG. Terminal 622 is grounded via external resistor 624. The emitter of diode-connected transistor 620 is connected to the base and collector of diode-connected transistor 622, and the emitter is connected to the collector of transistor 624. The emitter of transistor 624 is connected to negative voltage rail 450. The base and collector of transistor 622 (two diode drops above negative voltage rail 450) are connected to the base of transistor 626 and the base of transistor 628. The emitter of transistor 626 is connected to the base and collector of transistor 624. Similarly, the emitter of transistor 628 (one diode drop above negative voltage rail 450) is connected to the collector and base of transistor 624. The collector and base of transistor 624 are then connected to transistors 630 and 6.
32, 634, 636, 638, and 640 and the base of transistor 642, the emitter of transistor 642 is connected to negative voltage rail 450. transistor 62
The common base connection of 6 and 628 is connected to the bases of transistors 630, 632, 634, 636, 638 and 640. The collector of transistor 630 is connected to the emitter of transistor 644 and the base is connected to the base of transistor 646. The emitter of transistor 646 is connected to the collector of transistor 632. The collector of transistor 626 is stage 3
20 to junction 338 of transistor 6
The collector of 28 is connected to the base and collector of transistor 414 of bias generator 324 . The collector of transistor 644 is connected to the emitter of transistor 346 and the base of transistor 356 of amplifier stage 320.
The collector of transistor 646 is connected to the emitter of transistor 466 and the base of transistor 470 of logarithmic section 26 . The collector of transistor 634 is connected to the common collector and base of transistor 604 and to current source 300. The collector of the transistor 636 is the wave generator 2
8 and the collector of transistor 638 is connected to junction 506 of buffer amplifier 30. The collector of transistor 640 is connected to the base of transistor 520 and the emitter of transistor 516 of buffer amplifier 30, and the collector of transistor 642 is connected to detector output terminal 524.

Voltage source 304 includes three diode-connected transistors 700, 702 and 704.
The collector and base of transistor 700 are connected to the emitter of transistor 458 and the base of transistor 460 of logarithmic section 26 three diode drops above ground. The emitter of transistor 700 is connected to the collector and base of transistor 702 and is
It forms a current source above the diode drop.
The collector and base of transistor 702 are connected to stage 32.
0 to the emitter of transistor 334 and the base of transistor 342. Finally, the emitter of transistor 702 is grounded via diode-connected transistor 704.

In operation, the system is properly biased so that the gain control module source 32 and the detector current sources 300, 302 provide the necessary bias current. When an input voltage signal is applied to input terminal 14, it is converted into a current and is applied to terminals 14A and 14B.
added to. Thus terminals 14A and 14B
current signals are simultaneously present in the gain control module 10 and the detector 12.

The detector receives the signal at junction 330 and rectifier 2
4. In particular, the negative signal at input 330 becomes the positive output of amplifier stage 320. This causes transistor 384 to be forward biased, allowing current to flow from the output 400 of cell 322 through the collector-emitter path of transistor 384 of rectifying cell 322 . In this way, the input terminal 4 of the logarithmic part 26
A current flows from 54. Transistors 380 and 382 of cell 322 remain reverse biased and non-conducting. A positive current signal at input 330 causes a negative output of amplifier stage 320. This causes transistor 380 to be forward biased and transistor 384 to be reverse biased. Transistor 380 thus conducts current, which is mirrored through the collector-emitter path of transistor 382. transistors 380 and 382
The emitter current sinks through the bias generator to the negative voltage rail 450. Thus, current flows from input terminal 454 of logarithmic section 26 to cell 322 for a negative input signal. Full-wave rectification is therefore performed. The current signal provided to input terminal 454 of logarithmic section 26 is converted to a logarithmic signal and multiplied by a factor of two by the feedback paths of diode-connected transistors 480 and 482. This produces a logarithmic output signal, which represents the logarithm of the square of the instantaneous input current at terminal 14B. The signal at the output of logarithm section 26 is transmitted to low pass filter 28 which provides a control signal through amplifier 30 to terminal 524.
Terminal 524 is connected to terminal 144 so that a control signal can be applied to the log signal within the module's VCA cell 20.

The input signals at terminals 14A and 14B are also transmitted to module 10, where a gain is applied to the current signal as a function of the control signal. terminal 14
Feedback occurs through logarithmic transistors 116 and 118 of VCA cell 20 for the negative input signal of A. The voltage signal across the first and second order logarithmic transistors 116 and 118 is a logarithmic function of the input signal due to the presence of the transistors in the feedback path of stage 18. The control signal at terminal 144 is arithmetic added to the logarithmic signal before inverse transistors 132 and 134 convert the algebraic sum of the two signals to an inverse signal as a function of the inverse of the sum of the two signals. Feedback occurs through logarithmic transistors 122 and 124 of VCA cell 20 for the positive input signal at terminal 14A. The logarithmic signal provided by logarithmic transistors 122 and 124 is also a logarithmic function of the input signal due to the transistors in the feedback path of stage 18. The control signal at terminal 144 is added to the logarithmic signal before inverse transistors 138 and 140 convert the algebraic sum of the two signals to an inverse signal that is an inverse function of the sum of the two signals.

Stage 18, in particular transistor 42 and current generator 4
8 allows a smaller bias current to be drawn from the stage at terminal 14A without affecting the gain-bandwidth product of the stage.

Additionally, capacitor 94 and resistor 70 are used to provide a zero within the transfer characteristic of amplifier 18 to
The 90° phase shift that occurs in the return path through cell 20 can be canceled out. By connecting diode 82 to the emitter of transistor 68 and matching the impedance of resistor 76 to the combined impedance of diode 82 and resistor 84, the noise contribution from source 32 can be reduced. Finally, the addition of capacitor 84 creates a zero in the transfer characteristic of the stage to cancel the pole caused by the base-emitter parasitic capacitance of transistor 66.

VCA cell 20 using bias generator 22
A bias voltage is provided between junctions 112 and 128 of. The bias voltage is determined by the input current from source 32, which produces a temperature independent bias current through the cell.

Log and inverse transistors 118, 122, 134 and 1 of cell 20 using secondary transistors 116, 124, 132 and 140 and resistors 114, 126, 130 and 142.
38 to reduce distortion due to parasitic base and emitter resistance.

The performance of the detector can be improved by using the rectifying cell 322 of the detector 12 to provide a maximum limit on the unity loop gain, particularly in both return paths around the amplifier stage 320. Finally, the bias generator 324 converts most of the generator into the transistor 384.
from the base of transistor 30 and the common emitter of transistor 30 while simultaneously providing the desired bias voltage therebetween.

From the foregoing, an improved compandor is provided which can be used as a compressor or expander of the signals applied to input terminals 14A and 14B. This compander can be easily manufactured as an IC circuit, reducing manufacturing costs. module 1
If 0 and detector 12 are fabricated as separate integrated circuit chips, they will consume substantially the same amount of power. In particular, the output of the detector 12 is a function of the input signal and the effective value of the operating temperature. The detector gain is a function of the control signal and temperature. Therefore, the design ensures that the temperature variations in the rms output match the temperature variations in the VCA gain, and the compression or expansion coefficients are independent of temperature as long as the module and detector operate at the same temperature.

Modifications may be made to the apparatus within the scope of the invention, and the foregoing description and accompanying figures are intended to be illustrative only and not limiting.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the most basic elements of a compander system, FIG. 2 is a block diagram of essential elements of an embodiment of the compander system of the present invention, and FIGS. 3A and 3B are diagrams of the present invention. Figures 4A and 4B are circuit diagrams of embodiments of the detector of the present invention. Explanation of symbols 10...gain controller, 12...detector, 18...input stage, 20...VCA cell, 2
2... Bias generator, 24... Rectifier, 26...
...logarithmic part, 28...logarithmic wave generator, 30...buffer amplifier.

Claims (1)

[Claims] 1. (A) A gain control module for varying the gain applied to an input signal as a function of a control signal, the module comprising: (i) an input terminal and an output terminal connected to receive the input signal; (ii) a corresponding one of the two arranged in each of the two return paths connecting the input terminal and the output terminal of the amplifier stage and representing the input signal; a first logarithmic conversion device that provides a logarithmic signal as a logarithmic function; (iii) a device that adds the control signal to each of the logarithmic signals; and (iv) a first logarithmic conversion device connected to each logarithmic conversion device that provides a corresponding logarithmic signal and the control signal. a reciprocal converter for providing an inverse signal as an inverse function of the sum of the signals; and (v) a first bias generator for generating a bias current flowing through the logarithmic converter and the inverse converter in both return paths. It is a device,
(B) a control signal generating device that detects the input signal and generates the control signal in response thereto; (i) an operational rectifier device that provides a rectified signal that is substantially rectified of the input signal and has an input terminal adapted to receive the input signal and an output terminal adapted to provide the rectified signal; (a) a second operational amplifier stage having an input terminal and an output terminal connected to an input terminal of the rectifier arrangement; and (b) a second operational amplifier stage responsive to an output of the second operational amplifier stage. a first current conducting device defining a transmission path between input and output terminals of the device and substantially conducting one of the input signals between the input and output terminals of the rectifier; (c) the second operational amplifier stage; defining a second transmission path between the input and output terminals of the second operational amplifier stage in response to the output of the second operational amplifier stage; (d) a signal generating device that generates an inverse signal of the other input signal in response to the input signal when the second transmission path is substantially conductive; (ii) biasing the first and second current conducting devices and the signal generating device connected to the output of the second operational amplifier stage; a second bias generator for relaxing rotational speed conditions for a given performance value; and (iii) a second logarithmic transform connected to the output of the operational rectifier device to provide a second logarithmic signal as a logarithmic function of the rectified signal. (iv) a low pass filter connected to the output of the second logarithmic conversion device to provide the control signal substantially as a function of the DC value of the second logarithmic signal; A compander characterized in that it has: the control signal generating device comprising; 2. The compander of claim 1, wherein the first operational amplifier stage includes a device for reducing the input bias current drawn from the input signal without affecting the gain-bandwidth product of the stage. A compander characterized by: 3. A compander according to claim 2, wherein the device for reducing the input bias current is a bipolar amplifier located at the input terminal of the first operational amplifier stage and buffering the input terminal from the remainder of the stage. A compander comprising a transistor device and a second signal generating device for generating a current to the bipolar transistor device to reduce the amount of bias current drawn from the remainder of the stage. 4. In the compandor according to claim 1, the first logarithm conversion device and the inverse conversion device connected to the compandor each define a log-inverse transmission path, and the gain control The module further includes a signal modification device disposed in each log-opposite path for modifying the input signal and the reciprocal signal in accordance with a modification signal to reduce distortion of the reciprocal signal. Stretcher. 5. In the compander according to claim 4, the first logarithm conversion and the reciprocal conversion device for each logarithm-inverse transmission include transistors of the same conductivity type, and the transistors in one path are A compander characterized in that each transistor in the other path is of an opposite conductivity type. 6. The compandor of claim 5, wherein the signal modification device includes a transistor connected to each of the first logarithmic conversion devices and each inverse conversion device of each log-to-inverse transmission path. A compandor characterized in that the transistors of each pair are of opposite conductivity type. 7. In the compander according to claim 6, all the transistors of each conductivity type have their V
A compander characterized in that _be /I _C transfer characteristics are matched. 8. The compander of claim 7, wherein the emitters of each transistor pair are connected together and the signal modification device generates a modification signal to each transistor pair to reduce the parasitic base and emitter resistance of the transistor pair. A compander characterized in that it includes a device for correcting. 9. The compander according to claim 8, wherein the correction signal generating device includes a device for detecting a difference between a corresponding inverse signal of each path and each of the input signals. vessel. 10. The compander according to claim 9, wherein the device for detecting the difference includes a resistor device connected to the collector of each transistor of each signal modification device and a transistor of the signal modification device in each path. A compander characterized in that it includes a device for measuring the voltage difference between the collectors of the compander. 11. The compander of claim 10, wherein the measuring device connects the base of each transistor of the signal modification device in each log-inverse transmission path to the base of each transistor in the signal modification device in the same log-inverse transmission path. A compander characterized in that it includes a device for cross-connecting to the collector of a transistor. 12. The compander of claim 11, wherein each resistor device is adjustable to correct for parasitic base and emitter resistance mismatch of the transistor pair. 13. The compandor of claim 5, wherein the device for applying the control signal is connected to the base of a transistor of a first log conversion device of one log-inverse transmission path and the other log-inverse transmission path. Companding device characterized in that it includes a connection device for applying a control signal to the base of a transistor of the inverse conversion device of the conversion device. 14. The compander according to claim 1, wherein the first bias generating device includes a reference device for supplying a first voltage as a function of temperature;
, and a scalar device configured to generate the bias current by supplying a bias voltage across the logarithmic conversion device and the inverse conversion device in the feedback path. 15. A compander according to claim 14, characterized in that the reference device includes a base-emitter junction of at least one transistor and the scalar device includes a ratio of two resistors. Companding machine. 16. The compandor of claim 1, wherein the first and second current conducting devices each have a maximum loop transmission of unity gain. 17. The compander of claim 1, wherein the first current conducting device of the operational rectifier device includes a transistor whose collector and emitter connect from the output terminal of the operational rectifier device to the input of the operational rectifier device. the second current conducting device of the operational rectifier device includes a second transistor whose base-emitter junction connects the input terminal of the operational rectifier device to the second operational amplifier terminal; the signal generating device of the operational rectifier device includes a third transistor whose collector and emitter are connected to conduct current through the base-emitter junction of the second transistor; a compander connected to conduct current from an output terminal of said operational rectifier to an output terminal of said first operational amplifier stage in response to said compander. 18. A compander according to claim 17, further comprising a device for providing gain symmetry between the second and third transistors on the one hand and the first transistor on the other hand. Stretcher. 19. The compander of claim 1, wherein the second bias generator of the operational rectifier device includes a circulating current generator flowing through the first and second rectifier devices, and is responsive to the circulating current. A companding device characterized in that the current error generated at the output terminal of the operational rectifier device is independent of temperature. 20. The compander according to claim 19, wherein the circulating current generating device includes the device for preselecting the maximum allowable value of the current error, and the device for preselecting the maximum allowable value of the current error, and the device for preselecting the maximum allowable value of the current error. A compander characterized by comprising: 21. The compander according to claim 1, wherein the second bias generating device of the operational rectifier device is connected to a first resistor device and the first and second current carrying devices, and the second bias generating device of the operational rectifier device is a second impedance load including a second resistance device connected to the resistance device; and generating a voltage across the first impedance load to generate a current in the first resistance device; generating a current in the second resistive device in response to the current in the resistive device;
an apparatus for generating a bias voltage across an impedance load, the bias voltage varying with temperature such that the bias currents generated in the first and second current state devices are independent of temperature. Companding machine. 22. The compandor according to claim 1, wherein the second logarithmic signal is a logarithmic function of the square of the instantaneous value of the input signal. 23. The compander of claim 22, wherein the second logarithmic conversion device comprises a third operational amplifier stage having an input terminal for receiving the rectified signal and an output terminal for supplying the second logarithmic signal. and a pair of diode devices connected between the input and output terminals of the third operational amplifier stage. 24. A compandor as claimed in claim 1, wherein the low frequency waver includes at least one diode device connected between an input and an output of the waver.