JPS6248932B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a pulse counting circuit having a function of outputting a count value in response to an external request.

For example, a scintillation counter for measuring gamma rays generates pulses corresponding to the amount of gamma rays, so the amount of gamma rays can be measured by counting these pulses.

Then, the counted value is outputted as appropriate in response to an external request.

To prevent such a count value from operating during an output request and causing the output count value to become undefined, conventionally the output request signal OP was used as shown in Figure 1.
While the input pulse P is output, the input pulse P is prevented from being input to the counter 2 by the blocking circuit 1, or a buffer register 3 exclusively for output is provided as shown in Fig. 2, and the output request signal OP is output. During this period, the rewrite inhibiting circuit 4 inhibits the output of the timing circuit 5 to inhibit rewriting of the buffer register 3. In FIG. 2, 6 is a delay circuit, which is provided to obtain a counting output after the operation of the buffer register 3 is stabilized.

However, in the configuration shown in Figure 1, input pulses cannot be counted during an output request, so in the case of rapidly repeating pulses, the error from the true value becomes large, and the second
The circuit shown in the figure has the disadvantage that it requires a buffer register of the same capacity as the counter, a timing circuit, and a rewriting circuit. Note that AND in FIGS. 1 and 2 is an AND gate.

Further, FIG. 3 shows a circuit proposed to solve the above problem, and FIG. 4 is a time chart of FIG. 3. In the figure, COT1 to COT3 are counters, CON is a comparator, OSC is an oscillator, AND, AND
1 is an AND gate, DEL is a delay circuit, and the waveforms at points a to h in FIG. 3 are shown using the same symbols in FIG.

When the pulse shown in FIG. 4a is input to the counter COT1, the counter COT1 counts it. This count output is input to the comparator CON.

On the other hand, counter COT2 and counter COT3 are oscillators.
Count the pulses from OSC, which are generated in response to the output from comparator CON.

That is, in the comparator CON, the counter COT1 and
The count values b and c of COT2 are compared, and if they do not match, a pulse is output from the comparator CON.

Furthermore, if the output request signal f is not output at this time, the pulse d is output from the AND gate AND. This pulse d drives the oscillator OSC to output a pulse e, which is counted by the counters COT2 and COT3. As a result, when the count values of the counter COT1 and the counter COT2 match, no pulse is output from the comparator CON.

In the manner described above, the counter COT3 accumulates input pulses.

On the other hand, the counters COT1 and COT2 overflow every fixed value.

These counters COT1 and COT2 have M>T _OUT /T
It is an M-adic counter that satisfies _IN . Note that T _OUT is the maximum value of the required output time, and T _IN is the minimum period of the input pulse.

To explain the above in detail with reference to FIG. 4, when the input pulse a is input at time _T1 , the counter COT1 counts at the falling edge of the input pulse a, and the count value b becomes "1".

At this point, the count value of the counter COT2 is "0", so a pulse is output from the comparator CON.

Since this output request signal f is at a low level, it is inverted to a high level by an inverter and an AND gate is applied.
is input to AND, and this AND gate AND
The pulse d is input to the oscillator OSC via.
As a result, the oscillator OSC outputs a pulse e, which is counted by the counters COT2 and COT3.

At this point, the count values b and c of counters COT1 and COT2 are both "1", so the comparator CON
There is no output from.

By repeating the above operations, the count values of the counter COT1 and the counter COT2 become the same, so that the number of input pulses a can be accurately counted in the counter COT3.

When the output request signal f becomes high level at time _T2 , the AND gate AND
Since the input to is low level, the AND gate
Output of AND is prohibited. Therefore, the oscillator OSC
From then on, pulse e is no longer output.

In this state, the count value g of counter COT3
is output via the AND gate AND1.

Similar to the circuit shown in FIG. 2, the delay circuit DEL is provided to obtain a counting output after the counting operation of the counter COT3 is stabilized.

While the output of the AND gate AND is prohibited, the input pulse a is counted by the counter COT1, but the counter COT2 stops its counting operation.
Therefore, as shown in Figure 4, at time _T2 , the counter
COT1 count value b is "7", but counter COT2
The count value c has become "4".

When the output request signal f becomes a low level at time _T3 , the inhibition of the AND gate AND is released.
Therefore, the pulse d is input to the oscillator OSC via the AND gate AND, and the counter COT is input as described above.
Oscillator OSC until count value of 1 and COT2 match
A pulse e is output from.

In this way, the count value is corrected.

Although the above configuration makes it possible to eliminate errors in the counted values and eliminates the need for a buffer memory, the following problems may occur.

That is, as shown in FIG. 5, when the input pulse a falls at time _T4 and an output request is made immediately after the counter COT1 operates, a thin pulse corresponding to the time difference between the two is output from the oscillator OSC. , if this pulse width is narrower than the guaranteed operation range of counters COT2, COT3, counters COT2, COT3
There is no guarantee that COT3 will operate reliably.
If both counters do not perform counting, there is no particular problem as correction will be made later, but
If COT2 operates and counter COT3 does not operate, or vice versa, correction cannot be made, and if this happens repeatedly, the error between the true value and the counted value will increase. There is a problem.

The present invention was made with the aim of solving this problem, and in the circuit configuration shown in FIG. 3, a multivibrator is provided at the output section of the oscillator.

Embodiments of the present invention will be described below with reference to FIGS. 6 and 7.

In FIG. 6, parts indicated by the same reference numerals as in FIG. 3 above represent the same structure as in FIG.

In the configuration shown in FIG. 6, a monostable multivibrator MM is inserted in the output stage of the oscillator OSC.

That is, here, the pulse e from the oscillator OSC is input to the monostable multivibrator MM and shaped into a pulse e' having a constant width. Therefore, even if the input pulse and the output request signal are close to each other at time _T4 as shown in FIG.
The operations of COT1 and counter COT2 are no longer different. In other words, the output of the oscillator OSC becomes thinner,
If the multivibrator MM does not operate, no output from the multivibrator MM can be obtained, so that neither the counters COT2 nor COT3 perform a counting operation. On the other hand, even if the output of the oscillator OSC becomes thin, as long as the multivibrator MM is within the operating range, the multivibrator MM
Since an output having a more constant pulse width can be obtained, both counters COT2 and COT3 perform counting operations. Therefore, it is possible to prevent errors in the counted value due to only one of them operating.

As described above, according to the present invention, even when a thin pulse is output from the oscillator OSC, such as when an output request is made immediately after the input pulse falls and the counter COT1 operates, it is possible to A reliable counting operation can be performed.

[Brief explanation of the drawing]

Figures 1 and 2 are diagrams showing an example of a conventional pulse counting circuit, Figure 3 is a diagram showing a circuit configuration that solves the problems of the circuits shown in Figures 1 and 2, and Figure 4 is a diagram showing an example of a conventional pulse counting circuit. 3 is a time chart, FIG. 5 is a diagram for explaining problems that occur in the circuit configuration shown in FIG. 3, FIG. 6 is a diagram showing an embodiment of the present invention, and FIG. 2 is a time chart of the circuit shown in the figure. In the figure, COT1 to COT3 are counters, CON is a comparator, OSC is an oscillator, and MM is a monostable multivibrator.

Claims (1)

[Claims] 1 First counter COT1 that counts input pulses
a multivibrator MM that holds pulses from the oscillator OSC for a certain period of time; and second and third counters COT2 that count the pulses received from the oscillator OSC via the multivibrator MM.
COT3, and a comparator CON that compares the count values of the first counter COT1 and the second counter COT2 and outputs pulses from the oscillator OSC until the count values match. third counter
The third counter is activated by the request to output the count value of COT3.
Outputs the count value of COT3 and the comparator
The drive of the oscillator OSC by CON is stopped, and after the output of the count value is completed, the first counter COT1 and the second counter
A pulse counting circuit characterized in that the oscillator OSC generates pulses until the counted values of the counter COT2 become equal.