JPS6249595B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention provides a
The present invention relates to a CPU type electronic watch that uses a CPU (Central Processing Unit) to perform timekeeping operations etc. according to a program, and particularly relates to a CPU type electronic watch with a lamp that illuminates a liquid crystal display device.

Conventionally, a clock operates as shown in Figure 1.
A battery 2 is used as a power source for the CPU 1, and a common battery 2 is also used as a power source for a lamp 3 for illuminating the liquid crystal display device. In such an electronic watch, when the switch 4 for lighting the lamp 3 is closed, as shown in FIG.
A rush current 5 flows, and the terminal voltage 6 of the battery 2 temporarily decreases. Due to this decrease in terminal voltage 6,
There was a fear that CPU1 would malfunction.

The present invention has been made in view of the above-mentioned points, and it is an object of the present invention to provide a CPU type electronic timepiece that prevents malfunction by stopping the system clock of the CPU for a certain period of time immediately after the lamp is turned on. Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 3 is a block diagram showing an embodiment of the present invention, where 7 is an oscillation circuit that generates a reference signal, and 8 is an oscillation circuit that divides the reference signal of the oscillation circuit 7 into a predetermined frequency-divided signal φ ₃ , for example, a 1Hz signal. The frequency divider circuit 9 is a CPU, and based on the frequency division signal _φ3 of the frequency divider circuit 8, the time
Clock means 10 for creating time data such as minutes and seconds
, a lamp control means 12 that detects the opening and closing of a switch 11 connected to the outside and outputs a lamp lighting pulse and a lamp extinction pulse, and a counter control means 13, and these clock means 10 and lamp control means 12, and the counter control means 13,
It is realized by a program written in a ROM (not shown) provided in the CPU 9. 14
is an FF (flip-flop) that controls the transistor 16 that drives the lamp 15, a lamp lighting pulse is applied to the set terminal S, and a lamp extinguishing pulse is applied to the reset terminal R. 17
is a counter that counts the frequency-divided output _φ2 of the frequency dividing circuit 8, and the setting of the count value and the start of counting are controlled by the counter control means 13 of the CPU 9. 18 is a system clock circuit to which the frequency divided output _φ1 of the frequency dividing circuit 8 is applied via the AND gate ₁₉ , and creates a timing signal for operating the CPU 9 based on the frequency divided output φ1; 20 is a FF ( The output of the counter 17 is applied to the set terminal S, the lamp lighting pulse of the lamp control means 12 is applied to the reset terminal R, and the output Q is applied to the AND gate 19.

In FIG. 3, the FF 20 is normally in a set state, and its output Q is at the level "1", making the AND gate 19 conductive. Therefore, the system clock circuit 18 has a divided output φ.
₁ is applied, and the CPU 9 executes the program according to the timing signal generated by the system clock circuit 18. The clock means 10 is realized by a program, and every time the frequency-divided signal _φ3 is output, it reads seconds, minutes, hours, etc. stored in an internal memory circuit (RAM) (not shown). Performs addition processing and carry processing to data. Since the program clock means 10 is well known, detailed explanation will be omitted.

Further, the lamp control means 12 and the counter control means 13 are also means realized by a program, and these means will be explained with reference to FIG. 4.

FIG. 4 is a flowchart showing a program for the lamp control means 12 and counter control means 13, and this program is executed by periodic interrupt processing or interrupt processing performed when an external switch is operated. First, the data of the terminal to which the switch 11 is connected is taken into the CPU, and whether the switch 11 is closed or opened is determined by whether the data is a logic "1" or "0". switch 1
1 is closed, first the counter 17 is filled with 2~
A value of about 3 msec is set to start operation, and then a lamp lighting pulse is output. The output of the lamp lighting pulse puts the FF 14 into a set state, and its output Q goes to the "1" level, so the transistor 16 turns on and the lamp 15 lights up.
On the other hand, the FF 20 is simultaneously reset by the lamp lighting pulse and its output Q is set to the "0" level, so the AND gate 19 is cut off and the divided output _φ1 is no longer applied to the system clock circuit 18. The system clock circuit 18 is the CPU
The generation of the timing signal for executing the operation in step 9 is stopped. Therefore, the operation of the CPU 9 is fixed, and the progress of the program is stopped. In this state, due to the lash current flowing through the lamp 15,
Even if the power supply voltage drops, the CPU 9 remains fixed and will not malfunction. On the other hand, the counter 17 continues to count the frequency divided output φ2 of the frequency dividing circuit 8, and the counter 17 continues to count the frequency divided output _φ2 of the frequency dividing circuit 8, and the counter 17 continues counting the frequency divided output φ2 of the frequency dividing circuit 8.
When ~3 msec has elapsed, the counter 17 outputs an output, the FF 20 is set, and its output Q becomes "1". Therefore, the AND gate 19 becomes conductive again and the divided output _φ1 is applied to the system clock circuit 18, so that the operation of the CPU 9 is restarted. Since the lash current that flows when the lamp 15 is turned on is less than 1 msec, 2 seconds immediately after the lamp 15 is turned on.
When ~3msec has passed, the power supply voltage is
The voltage has increased to a level that will not cause malfunction.

When the switch 11 is opened, a lamp extinguishing pulse is output, the FF 14 is reset, the transistor 16 is turned off, and the lamp 15 is extinguished.

As described above, according to the present invention, the system clock is stopped for a certain period of time immediately after the lamp is turned on, and the CPU
By stopping the operation of the CPU 9, it is possible to prevent the CPU 9 from malfunctioning due to a drop in power supply voltage due to the rush current when the lamp is turned on.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a conventional example, Fig. 2 is a characteristic diagram showing the relationship between current and power supply voltage, Fig. 3 is a block diagram showing an embodiment of the present invention, and Fig. 4 is a flow diagram showing the operation. be. 7...Oscillation circuit, 8...Divide circuit, 9...
CPU, 10...Clock means, 11...Switch,
12...Lamp control means, 13...Counter control means, 15...Lamp, 16...Transistor,
14, 20...FF, 17...Counter, 18...
...System clock circuit, 19...AND gate.

Claims (1)

[Claims] 1. An oscillator that generates a reference signal, a frequency dividing circuit that divides the reference signal of the oscillator into a predetermined frequency, a clock means that performs a timekeeping operation based on the predetermined frequency-divided signal of the frequency dividing circuit, and detects the opening and closing of an external switch. A lamp control means for controlling the blinking of an externally connected lamp inputs the divided output of the frequency dividing circuit to a CPU (central processing unit) configured by a program, and controls the output of the CPU. A CPU-type electronic timepiece equipped with a system clock circuit that generates a timing signal to perform an operation, a counter control means configured in the CPU and operated according to instructions from the lamp control means;
A counter that is controlled by the counter control means and counts the frequency-divided output of the frequency divider circuit, and is set and reset by the output of the counter and a lamp lighting pulse output from the lamp control means. A flip-flop (FF) and a gate circuit to which the output of the flip-flop is applied and interposed between the frequency divider circuit and the system clock circuit are provided, and the gate circuit is provided between the generation of the lamp lighting pulse and the time of generation of the output of the counter. A CPU-type electronic timepiece, characterized in that the operation of the system clock circuit is stopped by bringing the flip-flop into a predetermined state.