JPS6249767B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a tracking correction device for obtaining optimal tuning between a high frequency signal tuning circuit and a local oscillation circuit in a superheterodyne receiver. In the superheterodyne system, the tuning frequency s (which is equal to the received signal frequency) of the high-frequency signal tuning (hereinafter referred to as signal tuning) circuit and the oscillation frequency o of the local oscillation tuning circuit must always differ by an intermediate frequency i. Must be. Therefore, the highest of s in the receiving band
The ratio of smax to the lowest smin is o
The ratio between the highest omax and the lowest omin is different. omax/omin=smax+i/smi
n+i≠smax/smin, i≠0... (1) For this reason, when tuning the signal tuning circuit and the oscillation circuit using a variable capacitor with the same variable coefficient or a variable cap with the same capacity, the relationship o=s+i is established throughout the broadcast band. It cannot be established in . Therefore, as shown in Fig. 1a and b, by providing a trimmer capacitor C _T etc. in the local oscillation circuit, three frequencies ₁ ,
At present, o=s+i holds true only at frequencies ₂ and ₃ , and other frequencies are also designed not to differ much from this relationship. Note that maintaining the relationship between o and s in this way is called tracking. Like an FM receiver, when s is 76 to 90 MHz (for domestic bands) and 88 to 108 MHz (for international bands), i = 10.7 MHz, so omax/omin = smax/smin,
Since s≫i, the tracking error is small and can be ignored. In particular, in AM receivers, s is 530~
In the case of 1605 KHz and i=455 KHz, as shown in FIG. 2, a tracking error of about 4 KHz at maximum theoretically occurs. That is, a phenomenon occurs in which the sensitivity of the signal tuning circuit decreases. This phenomenon poses a problem when designing a tuner with high sensitivity by increasing the Q of the coil of the signal tuning circuit. As shown in Figure 3, for example, the receiving frequency
For 800KHz, the local oscillation frequency is correctly 800KHz
Even if you tune to +455KHz, the tuning frequency of the signal tuning circuit will deviate from the receiving frequency by about 4KHz, resulting in a decrease in sensitivity. In addition, differences in characteristics may occur due to deviations or variations in the interlocking relationship between the variable capacitance element of the signal tuning circuit and that of the local oscillation circuit, and in such cases,
Even if the local oscillation frequency is tuned to be correct, the tuning frequency may deviate from the reception frequency, resulting in a decrease in sensitivity. The present invention aims to provide a tracking correction device that corrects the tuning frequency of a signal tuning circuit to be closer to the receiving frequency. In order to perform optimal tuning of the high frequency tuning circuit, a means is provided that allows the tuning frequency of the high frequency tuning circuit to be varied near the tuning point, and the optimal tuning point is recognized by determining the magnitude of the intermediate frequency output when this variation is made. An example in which optimum tuning (tracking correction) is performed by providing means for obtaining separate outputs and controlling the tuning frequency of the high frequency tuning circuit using the outputs will be described below. FIG. 4 shows a block diagram of a PLL synthesizer type AM tuner which is an embodiment of the present invention. 1 is an AM front end, which includes a signal tuning circuit A, a local oscillation circuit B, and a mixing and frequency conversion circuit C.
It consists of etc. The output from the AM front end 1 is introduced into a detection circuit 3 through an intermediate frequency amplification circuit 2, where the detected signal is amplified and input to a speaker. 4 is a PLL synthesizer section, which includes a frequency divider D for the crystal oscillation circuit, a programmable frequency divider E for the local oscillation signal from the local oscillation circuit B, a latch circuit F that is a buffer for data given to the frequency divider E, and a phase It is composed of a comparator G and a low pass filter H. 6 is a 1-chip microcomputer (hereinafter referred to as
It is called CPU. ), which consists of ROM, RAM, their address buses, data buses, accumulators, I/O ports, etc. A display section 7 displays the frequency at the time of reception of the signal from the CPU 6. 8 is the keyboard, 0-9
It has a number key and a set key, allowing you to input the desired receiving frequency. Enter the desired receiving frequency from keyboard 8.
When an AM broadcast is received, the signal from the antenna is amplified by the signal tuning circuit A, mixed with the local oscillation signal of the local oscillation circuit B, and frequency-converted by the frequency conversion circuit C, resulting in a 455KHz intermediate frequency signal. Become. This intermediate frequency signal is amplified by an intermediate frequency amplification circuit 2 and detected by a detection circuit 3. Here, the local oscillation signal of the local oscillation circuit B is supplied to the programmable frequency divider E, and the local oscillation signal of the local oscillation circuit B is supplied to the programmable frequency divider E.
Since the data from the CPU 6 is latched by the latch circuit F and fed therefrom to the program frequency divider E, the local oscillation signal is frequency-divided by 1/N. In addition, if the reception frequency is 800KHz, N
=800+455=1255, and if the reception frequency is generally KHz, then N=+455. This frequency-divided output is compared with a signal with a reference frequency of 1KHz obtained by dividing the oscillation output of the crystal oscillator by a frequency divider D in a phase comparator G, and after the comparison output passes through a low-pass filter H, the local oscillator Circuit B
The voltage is applied as a voltage to the variable capacitance element for controlling the local oscillation frequency of the signal tuning circuit A, and is also applied as a voltage to the variable capacitance element for controlling the tuning frequency of the signal tuning circuit A. Such a loop is a so-called PLL synthesizer loop, but since this itself is not the gist of the invention, a detailed explanation will be omitted. In this way, the local oscillation frequency is (+
455) KHz = 800 is controlled to be maintained at 1255KHz, and the signal tuning frequency is controlled by the output of the low-pass filter H, so if the tuner is well designed, the signal tuning frequency will be approximately 800KHz. get. However, as mentioned above, a tracking error occurs, which reaches about 4KHz as in the above example, and due to the variation in the variable capacitance element.
It gets even bigger. The present invention corrects such tracking errors to obtain optimal tuning, and an example will be described below. The comparator circuit 5 is a hysteresis comparator for comparing the magnitude of the output of the intermediate frequency amplification circuit 2 with the variable reference voltage V, and is a hysteresis comparator for comparing the magnitude of the output of the intermediate frequency amplification circuit 2 with the variable reference voltage V. A comparison is made with the extraction reference voltage V. That is, if the voltage is higher than the reference voltage V, the output of the comparator circuit 5 is HIGH.
(1), if smaller, it becomes LOW (0). The output of this comparator 5 is read by the CPU 6. Also, a 4-bit signal is obtained as the output of the CPU 6, and this signal is input to the D/A converter 9, where it is converted into an analog voltage in response to the 4-bit signal and output. This is applied to the tracking correction variable cap _CTR of the signal tuning circuit A. FIG. 5 shows a configuration diagram of the signal tuning circuit A. Here, a tuning circuit is formed by a variable cap C to which a voltage from a low-pass filter H is applied and a tuning coil L, and a minute capacitor is connected in parallel with this tuning circuit. This minute capacitance is made by connecting a varicap _CTR in series with a capacitor of about 10pF. Here, the digital signal from CPU6 is
When the output of the D/A converter 9 is increased from 0001 [V] sequentially from 0001 to 0010, 0011, ......1111, the capacitance of the varicap C _TR increases as shown in Fig. 6. Go down one by one. Therefore, the tuning frequency of the signal tuning circuit A gradually increases in accordance with the digital signal, as shown in FIG. For example, if the tracking error is 4KHz when 800KHz is received, and the voltage applied to the variable cap _CTR is an analog voltage corresponding to digital signal 1000, it will correspond to 804KHz and digital signals 0001 and 1111, respectively. 790K
Hz, the tuning frequency is 818KHz. Note that an example is described in which the tuning frequency of 2 KHz changes with each rise of "1" in the digital signal. The output of the intermediate frequency amplification circuit 2 and the comparison output of the comparison circuit 5 in this example are shown in FIG. Here, the reference voltage V of the comparator 5 is set to an appropriate value, for example, a value greater than the noise level when there is no signal. The comparator 5 has a hysteresis characteristic to prevent the output from being reversed due to slight fluctuations in the output of the intermediate frequency amplification circuit 2. Therefore, when receiving 800KHz, a predetermined voltage is applied to the variable cap _CTR , for example, a digital signal "1000".
When a voltage corresponding to the PLL synthesizer is applied, the local oscillation frequency becomes 455 + 800KHz as shown above, but the tuning frequency becomes 804KHz according to the tracking error, and the tuning becomes impossible. However, it is possible to obtain a point at which the intermediate frequency amplification circuit 2 is at its maximum by varying the tuning frequency, for example, to obtain a digital signal where the intermediate frequency amplification circuit 2 exceeds the reference voltage. A tuning frequency of 800 KHz can be achieved by finding the middle value 0110 of the period 0011 to 1001 and applying an analog voltage corresponding to this to the variable cap _CTR . Focusing on this point, the CPU 6 uses a means for supplying a signal for varying the tuning frequency near the tuning point and a signal responsive to whether the output from the intermediate frequency amplification circuit 2 is higher than the reference voltage V. and means for obtaining a signal for correcting the tuning frequency to the optimum tuning side, and has the following functional units. Regarding the functional parts of this CPU6, please refer to section 9 below.
This will be understood from the explanation of the operation with reference to FIGS. 11 to 11. Note that FIGS. 9 to 11 show flowcharts for explaining the operation of the above embodiment. First, by turning on the power, it becomes START, and the initial value setting operation begins. At this time, registers to be used later, for example, X register, Y register,
The T _R register etc. are cleared and the output of the detection circuit 3 is muted so that no sound is produced. In this initial value setting, a preset broadcasting station frequency, for example 530, is input into the display register X, and the contents of the X register, X=530, are displayed on the display section 7. next,

According to the routine of [Equation], "8" is input to the register _TR as the voltage data to be applied to the variable cap C _TR , and the contents of the register _TR are output. As a result, a digital signal of 1000 is input from the CPU 6 to the D/A converter 9,
From there, an analog voltage corresponding to the digital signal 1000 is obtained and applied to the variable cap _CTR . next,

According to the routine of [formula], the data stored in register X, that is, X = 530
455 is added to the register Y, and the result is input to the register Y, and then outputted and applied to the PLL synthesizer section 4, that is, the latch circuit F. The PLL synthesizer section 4 operates according to the output from the latch circuit F, receives the broadcast, and outputs an intermediate frequency signal to the intermediate frequency amplification circuit 2. The output _S1 that the comparator circuit 5 obtains by comparing this intermediate frequency signal with the reference voltage V becomes LOW (0) level when there is no broadcast of the preset station, and HIGH (1) when there is broadcast. This is the level

[Formula] Loaded into CPU6 by routine and recorded. given to register A. Then the routine

According to [Formula], it is determined whether the contents of register A is 1 or not, and when A≠1, that is, when _S1 is LOW (0), until the next command to receive another broadcast is issued.

[Formula] In the routine, wait for a key to be pressed on keyboard 8, and if the pressed key is a numeric key, register the pressed number N (corresponding to the frequency of the station you wish to receive). X and displayed on the display section 7, indicating that the pressed key is

In the case of [formula]

[Formula] Returning to the routine, the PLL synthesizer section is operated to receive the broadcast of frequency N displayed on the display section 8. Then, when it is determined that S ₁ =1 and A=1, the optimal tracking operation state is reached according to the optimal tracking routine as described later, and then the above-mentioned

[expression] is introduced into the routine. Therefore, even when there is a preset broadcast, the frequency N of the desired broadcast can be given by key input on the keyboard 8, and the PLL synthesizer section 4 operates accordingly. In this way, if there is a broadcast, either a preset broadcast or a broadcast desired by the user by inputting on the keyboard 8,

When a YES determination is obtained in the routine of [Formula], the optimum tracking routine is introduced. FIG. 10 shows an example of an optimal tracking routine. This optimal tracking routine detects the optimal tracking point as follows, inputs and outputs the data to the register _TR , and thus sets the variable cap C _TR to the optimal capacity. As the voltage data applied to the variable cap C _TR , 0 is input to the register _TR of the CPU 6, and the contents of the register _TR are output, that is, a digital signal.
0000 is input to the D/A converter 9, and the analog signal obtained by D/A conversion is applied to the varicap _CTR . Then, the output of the intermediate frequency amplifier 2 at this time is compared with the comparator circuit 5, and the obtained output _S1 is sent to the register A.
, and determine whether it is 1 or not, and A≠1
Otherwise, when S ₁ = 0, add 1 to the contents of register T _R , i.e.

[Formula] When T _R ≠ 16 after executing the routine

[Expression] Return to routine. In this way, sequential register T _R while A≠1
Add the contents one by one one by one, and eventually A = 1, that is, S ₁ = 1.

[Formula] According to the routine, the contents of the register _TR are stored in the memory _M1 of the CPU 6. after that,

[Formula] After adding 1 to register T _R according to the routine

[Formula] In the routine, output the contents of register T _R as a digital signal and convert the corresponding analog voltage to varicap C.
to _TR , and S ₁ to accumulator A

【formula】 Enter according to the routine and

[Formula] When A=1, that is YES in the routine, if T _R ≠ 16, then again

[Expression] Return to routine. In this way, the value of register T _R when S ₁ = 0 immediately becomes A≠1 can be calculated as follows:

[Formula] Stored in the memory _M2 of the CPU 6 according to the routine. Then, the intermediate point M ₁ + M ₂ /2 between the value of memory M ₁ and that of memory M ₂ is set as the optimum tuning point and is transferred to register T _R.

[Formula] Enter according to the routine and set the value of the register T _R to

[Equation] According to the routine, it is output as a digital signal to the D/A converter 9, and then applied to the variable cap _CTR as an optimum tuning voltage to determine the capacitance. Note that if N=800, referring to FIG. 8, the digital signal 0110 is D/
It will be output to the A converter 9. Here, if

[Formula] The judgment result of the routine is YES, that is, A=1.

[Formula] If the judgment result of the routine is YES

[Formula] Store 15 in memory _M2 of CPU6 according to the routine.

[Formula] Enter the routine, do the same as above, and set the register T at this time.
Depending on the value of _R , a voltage is applied to the variable cap _CTR . Since the digital signal is 4 bits and the memory _M2 is also 4 bits, 15 is stored in the memory _M2 . As a result, although the voltage applied to the varicap C _TR may not necessarily give the optimum tracking point, it can reduce the tracking error sufficiently for practical purposes. It will be understood that if the number of these bits were made even larger, inputting 15 to the memory _M2 as described above could be avoided. If we increase the number of bits like this, we get

[Formula] Although it is possible in principle to prevent A=1 from continuing until the end in a routine, it is unavoidable that the number of bits is limited in practice. Also, even if register T _R is incremented from 0 to 15,

[Formula] In the routine, A≠1, that is NO It continues to be judged that and after that

[Formula] Assuming that the routine determines that T _R = 16, that is, YES,

[Formula] After 8 is input into register T _R according to the routine

[Formula] The routine is reached and a digital signal 1000 is output from the CPU 6. This is clear from the flowchart shown in Figure 8.

Returns to the operation in which an analog voltage is applied to the variable cap C _TR in the same manner as in [Formula]. Therefore,

The [Formula] routine leads to an auxiliary routine when the contents of register A do not change when register T _R is incremented, and there is almost no introduction to such an auxiliary routine. Detection of the optimal tracking point can also be realized by selecting the center as described above in relation to the section in which the output of the intermediate frequency amplification circuit 2 is greater than the reference voltage; It is also possible to select such a value, and this example will be explained with reference to FIG. 11. In place of the comparison circuit 5, an A/D converter 5' is used to convert the output of the intermediate frequency amplification circuit 2 into a digital signal according to its magnitude, and this digital signal is read out by the CPU 6. As in the case of Figure 10,

[Formula] Luci hmm,

[Formula] According to the routine, the digital signal 0000 is converted into an analog voltage by the D/A converter 9 and then applied to the varicap _CTR . The output of A/D converter 5' at this time is read into register A of CPU 6, and

[Formula] According to the routine, the value of register A is compared with the previously read value M in the comparison section of the CPU 6, and if the currently read value A is larger than the previously read value, that is, YES
When , the value of register A is stored in memory M, and register T _R is incremented by 1. Note that if the contents of register T _R are 0, the previously read value M may be, for example, an appropriate value (other than 0 |
x|). That is, in Figure 9,

[Formula] Routine,

[Formula] Luci each

[Formula] Routine,

[Formula] has been changed to routine, and M= |x| next

[Formula] According to the routine, NO is And

[Formula] Returning to the routine, the currently read value A and the previously read value M are compared in this way, and eventually

[Formula] For setting the optimal tracking point at the point where NO in the routine is considered to be the maximum point of the intermediate frequency signal.

[Formula] _D /
Output to A converter 9. Here, despite the increment of register T _R

[expression] routine continues YES

[Formula] If the routine determines YES, 16 is input to the register T _R and the value is output to the D/A converter 9 as the optimum tracking point. According to the present invention described above, the high frequency tuning circuit is set to a tuning frequency that causes no tracking error, so that the AM broadcast receiver can be made highly sensitive.

[Brief explanation of the drawing]

Figures 1a and b are circuit diagrams of general examples of signal tuning circuits and local oscillation circuits, Figure 2 is an explanatory diagram of the tracking error characteristics of the same as above, and Figure 3 is an explanatory diagram of the response characteristics of the signal tuning circuit. 4 is a block diagram of an embodiment of the tracking correction device for an AM broadcast receiver of the present invention, FIG. 5 is a signal tuning circuit of the same as above, and FIG. 6 is a capacitance characteristic of the variable cap with respect to applied voltage. 7 shows the characteristics of the tuning frequency with respect to the applied voltage, FIG. 8 shows the explanatory diagram explaining the operating principle of the above, and FIG.
FIGS. 11 to 11 each show a flowchart for explaining the above operation. 1: AM front end, 2: Intermediate frequency amplification circuit, 4: PLL synthesizer section, 5: Comparison circuit, 6: CPU, 8: Keyboard, 9: D/A converter, A: Signal tuning circuit, B: Local oscillation circuit,
F: latch circuit, G: phase comparator, C and C _TR :
Varicap.

Claims (1)

[Claims] 1. Optimum tuning of a high frequency tuning circuit for a local oscillation circuit in a superheterodyne broadcast receiver whose oscillation frequency is controlled according to the phase difference between the output frequency of a programmable frequency divider and a reference frequency during broadcast reception. The above-mentioned device is provided with a tuning frequency variable means for varying the tuning frequency of the high-frequency tuning circuit near the tuning point so that the tuning frequency can be adjusted in the vicinity of the tuning point, and a control circuit for setting the division ratio of the programmable frequency divider based on keyboard operations. A comparator is provided that compares the intermediate frequency output obtained when the frequency is varied with a reference voltage and outputs the comparison output, and the control circuit processes the output obtained from the comparator and inputs it as a control input to the tuning frequency variable means. 1. A tracking correction device for a broadcast receiver, characterized in that the device executes tracking correction of a high frequency tuning circuit.