JPS6249788B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a vertical synchronization device, more specifically, for example, a television receiver, etc., in which a vertical synchronization signal synchronized from a composite synchronization signal and a clock signal synchronized with a horizontal synchronization signal are frequency-divided. This invention relates to a synchronization device that synchronizes the obtained frequency-divided output.

FIG. 1 is a block diagram showing an example of this type of synchronization device that has been proposed in the past, and FIG. 2 is a specific example of a frequency divider 4 used in the example shown in FIG.

In FIG. 1, reference number 1 is an input terminal into which a clock signal with twice the frequency of the horizontal synchronization signal is input; 4 is an input terminal whose repetition frequency is equal to the vertical synchronization signal based on the clock signal input to input terminal 1; and a frequency divider configured to obtain a vertical scan output having a pulse width of a predetermined portion of the clock signal, eg, 512 bits to 525 bits.
Reference numeral 2 indicates an input terminal to which a composite synchronization signal is input, and reference numeral 5 indicates a vertical synchronization separation circuit connected to the input terminal 2. Reference numeral 6 indicates a phase comparator, and the phase comparator 6 compares the phases of the vertical synchronization signal obtained by vertical synchronization separation and the divided output of the frequency divider 4, and outputs a vertical synchronization output only when the phases do not match. Its input is connected to the output of the vertical synchronization separation circuit 5 and the output of the frequency divider 4, and its output is connected to the output of the frequency divider 4.
connected to the reset terminal of the 3 indicates an output terminal that outputs a vertical scanning signal.

In FIG. 2, flip-flops 9 to 18 are connected in series, and the clock signal applied to terminal 1 is internally reset by a NAND gate 19 so that it becomes equal to the repetition frequency of the vertical synchronizing signal, and the frequency divider 4 Configure. Further, 21 indicates a forced reset signal input terminal of the T-type flip-flops 9 to 18, the reset terminal 21 is connected to the output of the phase comparator 6, and the output terminal 3 is connected to the input terminal of the flip-flop 18.
connected to the non-inverting output of

A conventionally proposed synchronizing device having such a configuration performs the following operations to synchronize and maintain synchronization between the divided output of the frequency divider 4 and the vertical synchronizing signal.

That is, in FIG. 1, for example, if the vertical synchronizing signal from the separation circuit 5 and the frequency-divided output of the frequency divider 4 are in an asynchronous state, the phase comparator 6 synchronizes the vertical synchronizing signal with the frequency-divided output. detects a phase mismatch between the
This resets the frequency divider 4. As a result, the frequency divider 4 reset by the phase comparator 6 outputs a frequency divided output synchronized with the vertical synchronization signal, so the phase comparator 6 detects phase coincidence between the frequency division output and the vertical synchronization signal. However, the reset signal is not generated, the frequency divider 4 is not reset by the vertical synchronization signal, and the frequency divider 4 outputs a divided output synchronized with the vertical synchronization signal. After such operation, the frequency divider 4:
Synchronization pull-in is performed so that a frequency-divided output synchronized with the vertical synchronization signal is output to the output terminal 3.

However, when disturbances such as noise are mixed in the synchronization separation output of the vertical synchronization separation circuit 5 together with the vertical synchronization signal, the phase comparator 6 compares the phase of the disturbance in the synchronization separation output with the frequency-divided output. Even in this case, since there is a phase mismatch, the frequency divider 4 is reset by the disturbance. Therefore, the frequency divider 4 may be reset not only by the vertical synchronizing signal but also by disturbance. In this way, if one or more disturbance noises are present during the vertical period, the frequency divider 4 will be reset before outputting the vertical scanning output necessary to drive the next stage vertical deflection system. be done. Therefore, in the prior art, the vertical deflection system was not driven by resetting the frequency divider, and the reproduced screen had the disadvantage that it became a single horizontal character.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to provide a new vertical synchronization method that prevents the playback screen from becoming one horizontal character even when disturbances occur during the vertical period. The goal is to provide equipment.

The above object of the present invention is to provide an arbitrary N of horizontal synchronization signals.
(N is a positive integer) times the frequency is input to the clock input terminal of a frequency divider that obtains a divided output whose repetition frequency is equal to the vertical synchronization signal, and the vertical synchronization signal that obtains a vertical scanning output is input to the output of the frequency divider. The apparatus is characterized in that it has a pulse signal generator that outputs a pulse signal having a pulse width arbitrary P (P is a positive number) times the reset signal in synchronization with the reset signal of the frequency divider. This is accomplished by a synchronizer.

The present invention will be described below with reference to FIGS. 3 to 5 with respect to a preferred embodiment thereof.

FIG. 3 is a block diagram showing an embodiment of the vertical synchronization device according to the present invention, FIG. 4 is a diagram showing an example of a specific configuration of the frequency divider 8 shown in FIG. 3, and FIG. FIG. 2 is a diagram showing a specific example of a pulse signal generator that is a main part of the vertical synchronization device according to the invention. In addition, in FIGS. 3 and 4, the previously explained FIGS.
Portions corresponding to those in the figures are given the same reference numerals, and detailed description thereof will be omitted.

That is, in one embodiment of the vertical synchronization device according to the present invention shown in FIG. 3, a clock signal having twice the frequency of the horizontal synchronization signal obtains a divided output whose repetition frequency is equal to that of the vertical synchronization signal. It is input to the clock input terminal 1 of the frequency divider 8, synchronized with the reset signal of the frequency divider 8, and has an arbitrary P times the pulse width of the reset signal (pulse width required to drive the next stage vertical deflection system). In the embodiment, the input terminal of the pulse signal generator 7 outputs a signal with a time width of about 13 bits (525-512) of a clock signal with twice the frequency of the horizontal synchronizing signal, which corresponds to the blanking time. It is connected to the output terminal of the frequency divider 8. Pulse signal generator 7
The output of the phase comparator 6 is output as a vertical scanning output to the terminal 3, and is also input to the phase comparator 6 together with the vertical synchronization output obtained by performing composite synchronization separation by the vertical synchronization separation circuit 5. It is connected to an external reset terminal 21 (see FIG. 4) of the frequency generator 8.

In FIG. 4 showing a specific example of the frequency divider 8, the frequency divider 8 connects the reset signal terminal 22 to the frequency divider 4 in FIG.
and an inverting output terminal 23 of the flip-flop 13.

FIG. 5 shows a specific example of the pulse signal generator 7 composed of a flip-flop 24 and an inverter 26. In FIG. Terminal 22 and reset input terminal 27 are connected to terminal 23 of frequency divider 8, respectively.

The synchronizing device configured as described above performs the following operations to synchronize and maintain synchronization between the output of the pulse signal generator 7 and the vertical synchronizing signal.

That is, in FIG. 3, assuming that the vertical synchronizing signal and the output of the pulse signal generator 7 are in an asynchronous state, the phase comparator 6 detects a phase mismatch between the vertical synchronizing signal and the output of the pulse signal generator 7. death,
The frequency divider 8 is reset by the vertical synchronization signal output from the phase comparator 6.

The frequency divider 8 reset by the phase comparator 6 outputs a frequency divided output synchronized with the vertical synchronization signal, and
Since the pulse signal generator 7 connected to the reset terminal 22 of the frequency divider 8 also outputs an output synchronized with the vertical synchronization signal, the phase comparator 6
The frequency divider 8 detects the phase match between the output of the vertical synchronizing signal and the vertical synchronizing signal, and does not output the vertical synchronizing signal as a reset signal, so that the frequency divider 8 is not reset by the vertical synchronizing signal. Further, the pulse signal generator 7 outputs an output synchronized with the internal reset signal of the frequency divider 8 to the terminal 3.

Through this operation, the pulse signal generator 7 is synchronously pulled in so that it outputs an output synchronized with the vertical synchronization signal to the terminal 3.

Here, if the vertical synchronization signal and disturbance are mixed in the synchronization separation output of the vertical synchronization separation circuit 5,
A phase comparator 6 detects phase mismatch due to disturbance. Therefore, since the frequency divider 8 is reset by the disturbance noise, the frequency divider 8 is reset by the disturbance before completing a predetermined count (for example, 525 bits). However, in the present invention, since the pulse signal generator 7 is provided which generates pulses in synchronization with the reset signal of the frequency divider 8, the pulse signal generator 7
synchronizes with the reset signal of the frequency divider 8 and outputs a scanning output to the terminal 3 for driving the next stage vertical deflection system. As a result, even if the frequency divider 8 is reset due to a disturbance, the reset signal generator 7 will not stop outputting the vertical scanning output to the terminal 3.

Furthermore, when the synchronization device of the present invention is used, the playback screen does not become a single horizontal character even when synchronization is pulled in, and the above-mentioned drawbacks of the conventional example are solved.

Although the present invention has been described above with respect to one preferred embodiment thereof, this is merely an illustrative example, and it goes without saying that the present invention is not limited only to the embodiment described herein. for example,
In one embodiment of the invention, the pulse signal generator 7
is composed of a flip-flop 24 and an inverter 26, and is synchronized with a reset signal.
Any circuit may be used as long as it generates a signal with a pulse width necessary to drive the vertical deflection system; for example, a monostable multivibrator having a time constant of the pulse width may be used instead. Further, although the inverting output terminal 23 of the frequency divider 8 is connected to the inverting output of the flip-flop 13, the inverting output of the flip-flop 12 or 14 may be used instead.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventionally proposed synchronization device, FIG. 2 is a diagram showing a specific example of the frequency divider shown in FIG. 1, and FIG. 3 is a vertical synchronization system according to the present invention. A block configuration diagram showing one embodiment of the device,
4 is a diagram showing a specific example of the frequency divider shown in FIG. 3, and FIG. 5 is a diagram showing a specific example of the pulse signal generator shown in FIG. 3. 1...Clock signal input terminal with N times the horizontal frequency, 2...Composite synchronization signal input terminal, 3...Vertical scanning signal output terminal, 4...The repetition frequency of the signal input to terminal 1 becomes the vertical synchronization signal. Frequency divider that divides the frequency to be equal, 5... Vertical synchronization separation circuit, 6
...A phase comparator configured to compare the phases of the frequency-divided output and the vertical synchronization signal and output a vertical synchronization signal if the phases do not match, 7...Pulse signal generator,
8... In the frequency divider 4, frequency dividers 9 to 18 each have an output necessary to drive the pulse signal generator.
...T-type flip-flop, 19,20...
NAND gate, 21...External reset signal input terminal of frequency dividers 4 and 8, 22...Reset signal output terminal of frequency divider 8, 23...T-type flip-flop 1
3 inverted output terminal, 24...R-S flip-flop, 26...inverter, CL...clear terminal, CK...clock terminal, Q...non-inverted output,
...Inverted output of Q.

Claims (1)

[Claims] 1. Frequency dividing means that has a plurality of frequency dividers and receives a frequency signal that is an integral multiple of a horizontal synchronization signal and divides the frequency thereof;
a first gate circuit that generates a first reset signal at intervals equal to the period of the vertical synchronization signal in response to the output of a predetermined one of the plurality of frequency dividers; and a pulse signal that is supplied to the vertical deflection circuit. a pulse signal generator that generates a pulse signal having a pulse width necessary to obtain a vertical deflection signal in synchronization with the generation of a trigger signal; and a pulse signal generator that generates a pulse signal having a pulse width necessary to obtain a vertical deflection signal; a phase comparator that compares and generates a second reset signal when the phases do not match; and a phase comparator that is coupled to the first gate circuit and the phase comparator and is responsive to both the first and second reset signals. a second gate circuit that resets each frequency divider of the frequency dividing means and generates the trigger signal.