JPS6249797B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-tube imaging device including a plurality of imaging means such as a three-tube type (R, G, B) or a two-tube type (luminance and chroma), and in particular, to An error signal of the image center position of each image pickup means is obtained, and the image center positions of each imaging means are matched based on this error signal.

In a multi-tube type television camera, if the center positions of the images of each image pickup tube are not accurately aligned, color shift will occur.
Conventionally, alignment of the center of the image has been manually performed while viewing the composite image obtained from each image pickup tube, but the operation is complicated and accurate alignment is difficult. Further, it is necessary to have a special subject for adjustment, or to have a reference subject for adjustment built into the imaging device.

SUMMARY OF THE INVENTION An object of the present invention is to obtain a relative error signal of the image center position from the output signal of each image pickup tube, and to align the image center based on this error signal.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an image center alignment circuit in a three-tube television camera to which the present invention is applied, and FIG. 2 is a waveform diagram of FIG. 1. This television camera is equipped with green, red, and blue image pickup tubes 1, 2, and 3. The alignment of the center of the image is performed using the green image pickup tube 1 as a reference. The deflection coil of this image pickup tube 1 is given a bias of 1H in the vertical direction of the image and T/2 (H≫T, H: horizontal scanning period) in the horizontal direction, and the deflection coil of the other image pickup tubes 2 and 3 is The video output G' (FIG. 2a) whose phase is ahead of the outputs Ro and Bo by 1H+T/2 is obtained. Note that the high level portion of the signal G′ corresponds to the white portion of the image.

The video output G' is supplied to a 1H delay line 4, and the output G'' of this delay line 4 is supplied to a delay line 11 whose delay time T is sufficiently shorter than 1H.
From the center tap (T/2) of the camera, a video signal Go (FIG. 2e) which is approximately in phase with the video outputs Ro and Bo of the other image pickup tubes 2 and 3 is obtained. This signal is used as a comparison reference signal (main line signal).

The output of the 1H delay line 4 is further supplied to a 1H delay line 5, from which a signal DLG' (FIG. 2b) which is delayed by 2H from the original signal G' is obtained. The signals G' and DLG' are supplied to a differential amplifier 6,
From this, an edge signal EDG indicating the vertical edge of the image of the object as shown in FIG. 2c is obtained. This edge signal is a signal that has positive polarity when the video signal G' rises and negative polarity when it falls. After the edge signal is phase-matched with the main signal Go by the T/2 delay line 7, it is supplied to the multiplier 9 through the V (vertical) contact of the changeover switch 7 and the capacitor C2. Note that in the capacitor C2, the DC component in the edge signal is removed. The edge signal is also supplied to a gate signal generator 10, which generates a sampling gate signal SG corresponding to the position of the edge signal as shown in FIG. 2d.

On the other hand, video output Ro or Bo of image pickup tubes 2 and 3
(FIG. 2f) is supplied to the differential amplifier 15 through the selection switch 14. The other input of the differential amplifier 15 is supplied with the T/2 output Go (main line signal) of the T delay line 11. Therefore, a positional deviation signal REG as shown in FIG. 2g is obtained from the output of the differential amplifier 15. This positional deviation signal includes information regarding the amount and direction of deviation in the vertical and horizontal directions of the center position between the reference image of the green image pickup tube 1 and the output images of the other red or blue image pickup tubes 2 and 3. It is.

Since the AC component of the output of the differential amplifier 15 is supplied to the multiplier 9 through the capacitor C1,
Here, the edge signal EDG is multiplied by the positional deviation signal REG, and the error signal ER (second Figure h) is detected. Note that the edge signal EDG and positional deviation signal
Since multiplication with REG is performed, the direction of deviation can be detected, and since the output level of multiplier 9 is proportional to the level of the input edge signal, the multiplication output becomes zero in areas other than the edge area. , Therefore, only the necessary error signal can be extracted. Furthermore, the level of the edge signal increases as the edges of the object become clearer, so the error signal output from the multiplier 9 is weighted in proportion to the clarity of the edges of the object, improving detection accuracy.

The output of multiplier 9 is connected to capacitor C3 and resistor R.
gate circuit 1 through a high-pass filter consisting of
3. This gate circuit 13 is supplied with the already described sampling gate signal SG (FIG. 2 d) from the gate signal generation circuit 10, and the error signal ER is transmitted to the output of the gate circuit 13 only in the period of this gate signal.

As a result, the average voltage of the error signal ER in the gate section is held in the hold capacitor C4 connected to the output of the gate circuit 13. Therefore, a DC sample and hold voltage SH (FIG. 2i) corresponding to the error signal is obtained from the hold capacitor C4. The level of this sample-and-hold voltage corresponds to the amount of shift in the image center position, and its polarity corresponds to the direction of shift.

Note that it is also possible to simply integrate the error signal obtained from the output of the multiplier 9 to obtain the DC error signal. However, as shown in Fig. 1, if the sample and hold voltage is obtained by the gate circuit 13 and the hold capacitor C4, the integrated output can be increased, and noise and unnecessary signals outside the edge region can be increased. Since there is little influence, the accuracy of error detection can be improved.

FIG. 2j shows the case where the output Ro or Bo of the image pickup tube 2 or 3 is more advanced than Go (FIG. 2e) in the vertical direction. In this case, the signal shown in FIG. 2k is obtained as the positional deviation signal REG,
By multiplying this signal REG and the edge signal EDG, the error signal ER shown in FIG. 2I is obtained. Therefore, by sampling and holding this error signal, a negative polarity DC error signal shown in FIG. 2m can be obtained.

Figure 2n shows the output Ro or Bo of the image pickup tubes 2 and 3.
This shows a case where the phases of the signal Go and the reference signal Go match (the center positions match). In this case, if the white balance of each tube is not maintained or if a colored subject is imaged,
The levels of Go and Ro (or Bo) are different, and the positional deviation signal REG obtained from the differential amplifier 15 is
As shown in Figure 2 o, it does not reach the zero level. However, the error signal ER (Fig. 2 p) obtained by multiplying this signal REG and the edge signal EDG appears with opposite polarity at the rising and falling edges of the video signal, so they cancel each other out. Therefore, it does not appear in the sample and hold voltage. Therefore, deviations in white balance between the image pickup tubes or differences in video levels due to colored objects do not affect detection.

The sampled and held error signal SH is supplied to a control circuit 16, and the bias amount of the deflection coil of the image pickup tube 2 or 3 is changed by the output of the control circuit 16. As a result, the image center positions of the image pickup tubes 2 and 3 change in the vertical direction, and an error signal of the center position corresponding to this change is detected again by the detection circuit shown in FIG. In this manner, the control loop of FIG. 1 operates until the error signal becomes zero, and the image is centered in the vertical direction.

Horizontal centering is performed according to the same principles as the vertical direction described above. That is, the input and output of the T delay line 11 in FIG. 1 are supplied to the differential amplifier 17, where the horizontal edge signal EDG of the image is
is detected. This edge signal is supplied to the multiplier 9 through the contact H of the switch 8, where it is multiplied by the positional deviation signal REG in the same manner as described above.
From the output of the multiplier 9, an error signal containing information about the amount and direction of horizontal displacement of the image center is obtained, and this signal is sampled and held as a DC signal to determine the horizontal direction of each image pickup tube 2, 3. The center of the image is aligned.

FIG. 3 shows a specific circuit of the main part of FIG. 1. In this circuit, a differentiation circuit 18 is used as means for detecting the edge signal EDG in the horizontal direction of the image. This differentiating circuit 18 has the same function as the differential amplifier 17 that subtracts the input and output of the T delay line 11 in FIG. That is, the first
Output G'' of 1H delay circuit 4 in the figure (Figure 4a)
is connected to the resistor 1 through the transistor T1 in FIG.
9, a coil L, and a capacitor C5, and an edge signal EDG as shown in FIG. 4b is obtained from this differentiator circuit. Furthermore, the signal
The main line signal Go (FIG. 4c) obtained by delaying G'' by T/2 by the delay circuit 11 in FIG. 1 has almost the same phase as the center position of the edge signal.

Horizontal edge signal is buffer transistor T2
The signal is supplied to the changeover switch 8 via. Further, the output G' of the image pickup tube 1 at the edge and the signal DLG' delayed by 2H (output of the 1H delay line 5 in FIG. 1) are supplied to a differential amplifier 6 consisting of transistors T3 and T4. A vertical edge signal is obtained from its output. This edge signal passes through a buffer transistor T5 and a T/2 delay line 7 to a changeover switch 8.
supplied to

The changeover switch 8 is controlled by the output of a program counter (not shown) that controls this system. A horizontal or vertical edge signal EDG as shown in FIG. 5a is obtained from switch 8, and this edge signal is supplied to multiplier 9 through capacitor C2. The edge signal is also supplied to the gate signal generation circuit 10. This gate signal generation circuit 10 includes a pair of comparators 37,
The circuit is constructed with 38 window comparators, and detects only high-level edge signals outside the window indicated by diagonal lines in FIG. 5a, and forms the sampling gate signal SG shown in FIG. 5b. There is. If such a gate signal is used, the error signal output from the multiplier 9 will not be sampled, even with low-level edge signals and noise, so that the detection accuracy of the error signal can be extremely improved.

The gate signals are supplied to a blanking gate 39, where, for example, only gate signals within a circular or rectangular area at the center of the screen are extracted, and gate signals outside the area are blanked. This prevents color shift components due to poor beam deflection linearity at the periphery of the screen from being sampled by the gate signal and being mixed into the error detection signal at the center of the screen, and the accuracy of the error signal does not deteriorate. That's what I do.

On the other hand, the outputs Ro and Bo of the image pickup tubes 2 and 3 to be adjusted
are supplied to the selection switch 14, and one of these outputs is selected as the output of the program counter. The selected signal is supplied to one transistor T6 of the differential amplifier 15, and the other transistor T7 is supplied with the reference main line signal Go.
(a signal delayed by 1H+T/2 from the output G' of the image pickup tube 1) is supplied. Therefore, the differential amplifier 15
The above-described positional deviation signal REG is obtained from the output of , and this signal is supplied to the multiplier 9 via the buffer transistor T8 and the capacitor C1.

The multiplier 9 provides an error signal ER regarding the amount and direction of the shift in the horizontal or vertical direction of the image center position of the image pickup tube 2 or 3 with respect to the image pickup tube 1. Error signal is capacitor C3 and amplifier 4
0 to the gate transistor T9. Since the gate transistor T9 is turned on and off by the sampling gate signal output from the blanking gate 39, the DC error signal SH is stored in the sample and hold capacitor C4. This error signal is supplied to control circuit 16 of FIG.

Next, the control circuit 16 shown in FIG. 1 will be explained.
The control circuit 16 configured a control loop so that the deflection bias of the image pickup tubes 2 and 3 was adjusted according to the output of the positional deviation error detection circuit 32 shown in FIG. 3, and the output of the error detection circuit 32 became zero. It can be something. The control method may be an analog type in which the error signal is directly used as a control signal, or may be a control method via a digital control circuit.

FIG. 6 is a flowchart showing an example of the functions of the control circuit in the case of the latter digital method. First, the mode of the control system is set by starting (processing P1). Next, it is determined whether there is a shift in the image center position (semi-fixed J1), and if there is a shift (H), the contents of the system memory are updated (U/
D) Load into the counter (process P2). Note that the deflection bias of the image pickup tubes 2 and 3 to be adjusted is determined by the output of this U/D counter. Loading the U/D counter with an initial value is effective in accelerating the convergence speed of the system.

Further, along with process P2, the number of sampling gate signals SG output from the gate signal generator 10 of FIGS. 1 and 3 is counted for a certain period, for example, a 4V period (V: vertical period) (process P3). When this count value n is greater than or equal to the predetermined number K, it is determined that sufficient sampling data can be obtained (determination J2), and the count of the U/D counter is increased or decreased (process P4).
When n<K, the system program counter is incremented by one (processing P5). Note that a vertical synchronizing signal, for example, is used as the clock for the U/D counter, and its up/down is controlled based on the polarity of the detected error signal. Since the output of the U/D counter changes the deflection bias of the image pickup tube 2 or 3, the center position of the image changes.

When the center position of the image of the image pickup tube to be adjusted passes the center position of the reference image pickup tube 1, the polarity of the error signal is reversed, so the counting direction (increase/decrease) of the U/D counter is reversed. The number m of reversals is counted (process P6), and when m=8, for example, it is determined that the control loop has converged (determination J3). Also U/D
When the counter exceeds its maximum count value and a carry output occurs, this carry output is counted (process P7). When the carry count value c reaches, for example, 2, it is determined that the control system has malfunctioned (judgment J4), the program counter is incremented by one, and the next step is executed.

When it is determined in determination J3 that the control loop has converged, the data of the U/D counter is written to the memory (processing P8). At the same time, the number of memory writes is counted (processing P9), the program counter is incremented by one, and the program proceeds to the next step. Note that the program counter has 8 steps, and these steps correspond to the control mode of the 4-time alignment of the image pickup tube 2 (vertical V→horizontal H→V→H) and the similar 4-time alignment of the image pickup tube 3. There is. The output of the program counter is supplied to the selector switch 8 and selection switch 14 shown in FIGS. 1 and 3, and these switches are sequentially switched so that the eight control modes described above are carried out.

The reason why vertical and horizontal alignment is performed twice for each image pickup tube is because the center of the image is generally shifted in the diagonal direction, so if you perform horizontal alignment after vertical alignment, This is because the vertical center position changes as a result. Therefore, if each step is repeated twice in the order of V→H→V→H, the center positions will almost completely match.

When the count value N of the program counter does not reach 8 (determination J5), the above control modes are performed one after another. When N=8, it is then determined in determination J6 whether the number of times w of writing to the memory has reached 8. w<8 means that one or more of the measured values (data) of the U/D counter obtained by the above eight control modes are missing. In other words, in the state of w<8, it is determined in judgment J2 or J4 that either the count value n of the gate signal has not reached the specified number, or the count value c of the carry output of the U/D counter has reached 2. In this case, it is displayed that the operation of the control system has been erroneous (process P10), and the operation of the system is restarted from the beginning.

When w=8 in J6, it is determined that the image center positions of each image pickup tube are coincident, and the system operation is terminated (stop).

Next, FIG. 7 is a circuit diagram showing an example of the control circuit 16 of FIG. 1. Although FIG. 7 does not include the program counter and U/D counter loading circuits shown in the flowchart of FIG. 6, it is clear that these means could be added to the circuit.

In FIG. 7, the video outputs of image pickup tubes 2 and 3
Ro and Bo are supplied to the error detection circuit 32 shown in FIGS. 1 and 3, where they are compared with the output G' of the reference image pickup tube 1 as described above to determine the amount of deviation in the center position. and an error signal ER representative of the direction. The error signal is compared with the ground potential (OV) in the comparator 22, and outputs of high level and low level as shown in FIG. 8b are obtained from the comparator 22 depending on the polarity of the error signal. Note that when the image center positions of image pickup tubes 1 and 2 (or 3) match, the error signal becomes OV.

The output of the comparator 22 is supplied to the U/D control terminal of an up-down counter 23, and the increase and decrease of the count of this counter 23 is controlled. The output of the counter 23 is supplied to a D/A converter 24 via a random access memory (RAM) 41, where it is converted into an analog voltage. The output of the D/A converter 24 is set to 4 by a selector 42 controlled by the output of a program counter (not shown).
via amplifiers 25a to 25d,
The bias current is supplied to each of the vertical deflection coil 26V and horizontal deflection coil 26H of the image pickup tube 2 and the vertical deflection coil 27V and horizontal deflection coil 27H of the image pickup tube 3 to be adjusted.

Therefore, the center position of the output image of the image pickup tube 2 or 3 is changed at a predetermined speed in accordance with the output of the counter 23 in the opposite direction to the direction in which the image is being shifted, as shown in FIG. 8a. The rate of change is determined by the clock pulse of the counter 23, and in this embodiment the vertical synchronizing signal VD is used as the clock pulse.

Further, the counting operation of the counter 23 is started when the output of the gate signal counter 28 becomes high level. A sampling gate signal SG output from the gate signal generator 10 shown in FIG. 1 is supplied to the gate signal counter 28 as a clock pulse. The K-bit output QK of the counter 28 is supplied to the D terminal of a D flip-flop 43, and the clock terminal CK of this flip-flop 43 receives the output of a 4V counter 44 that counts four vertical synchronizing signals VD (FIG. 9A a) as a clock pulse. It is supplied as. Therefore the start pulse ST of the system
When the K bit output of the gate signal counter 28 is at a high level as shown in FIG. 9A d during the 4V period after the occurrence of (FIG. 9A b), the output of the 4V counter 44 (FIG. 9A c) With this, the D flip-flop 43 is set, and its output (9th
Figure A (e) is the low level. This output is passed through the NOR gate 29 to the enable terminal of the U/D counter 23 as a high level signal shown in FIG. 9Ah.
Since it is added to EN, the counter 23 starts operating. That is, when there are more than a predetermined number of gate pulses SG (for example, 128), it is determined that a highly accurate error signal has been obtained with sufficient sampling data, and the image center position adjustment operation is started.

In addition to counting the number of gate signals to determine the quality of the data, it is also possible to count the number of horizontal lines with gate signals, or obtain the analog integral value of the gate signal and compare this integral value with the standard. The level may also be compared.

When the error signal has negative polarity, the output of the comparator 22 becomes a low level as shown in FIG. Bias current decreases. Therefore, the image center position of the image pickup tube 2 or 3 is moved, for example, downward, as shown in FIG. 8a.

When it passes the position where the center coincides with the image pickup tube 1, the error signal is inverted to positive polarity, and the output of the comparator 22 is also inverted to a high level as shown in FIG. 8b. Therefore, the count value of the counter 23 increases and the bias current of the deflection coil increases, so that the image center position is moved upward as shown in FIG. 8a. Thereafter, such operations are repeated.

Since the output of the comparator 22 is supplied to the clock terminal CK of the stop counter 30,
The counter 30 counts the number of times the comparator 22 is inverted. When the number of inversions exceeds, for example, eight times, the Q3 output of the stop counter 30 becomes high level as shown in FIG. 9A, f. Since this Q3 output is applied to the NOR gate 29, the EN terminal of the U/D counter 23 becomes a low level as shown in FIG. 9A h, and the operation of the counter 23 is stopped. That is,
When the image center of the image pickup tube 2 or 3 has passed through the center matching position with the image pickup tube 1 eight times as shown in FIG. 8a, it is assumed that the center matching position has been converged, and the adjustment operation is terminated.

Note that when the U/D counter 23 is operating, the high level output of the NOR gate 29 (h in FIG. 9A) is supplied to the memory bypass terminal MB of the RAM 41, so the change in the count value of the counter 23 is
It passes through the RAM 41 and is directly supplied to the D/A converter 24. When the image center positions match and the output of the stop counter 30 becomes high level,
The write command terminal W of the RAM 41 becomes high level, and the contents of the U/D counter 23 at this time are
It is stored in RAM41. RAM41 includes horizontal and vertical deflection coils 26H, 26V of image pickup tubes 2 and 3,
It consists of four memory sections corresponding to 27H and 27V, respectively, and selection of these memory sections is performed by the output of an address generator 46 controlled by the output of a program counter.

Figure 9B shows that the sampling gate signal is a predetermined number K.
In this case, the 9th voltage is applied during the 4V period.
As shown in Figure B, the output QK of the gate signal counter 28 does not reach a high level. Therefore, the output of the flip-flop 43 is held at a high level, so the output of the NOR gate 29 remains at a low level.
U/D counter 23 does not operate. Since the output of the stop counter 30 remains at a low level as shown in FIG. 9B, the previous data is retained in the RAM 41 and the process proceeds to the next step.

During the counting operation of the U/D counter 23, the number of gate signals may decrease and sample data may become inappropriate. This state is thought to occur, for example, when the camera loses focus during the process, when the camera shakes significantly, or when the subject disappears. In such a case, the gate signal becomes smaller, the time for charging the sample-and-hold capacitor C4 in FIGS. 1 and 3 becomes shorter, and the sample-and-hold voltage drops significantly. As a result, the input bias current of the comparator 22 shown in FIG. 7 cannot be covered, and the output of the comparator 22 is fixed at either a high level or a low level.

Therefore, the U/D counter 23 becomes a one-way counter, and a carry output as shown in FIG. 9C CY is generated from its carry terminal CY. This carry output is supplied to the clock terminal CK of the 2-bit carry counter 45, so when the carry output occurs twice, the Q1 output of the carry counter 45 becomes a high level as shown in Figure 9C (g). . Since the output of the carry counter 45 is supplied to the NOR gate 29, the output of the NOR gate 29 becomes a low level as shown in FIG. 9C, h, and the counting operation of the U/D counter 23 is stopped. Furthermore, since the output Q3 of the stop counter 30 remains at a low level as shown in FIG. 9C, f, no data is written to the RAM 41, and the process proceeds to the next step with the previous data unchanged.

In this way, for the image pickup tube 2, V→H→V→
H image center alignment is performed, and then the image pickup tube 3
A similar operation is performed for . Image tube 2 and 3
Data for aligning the center position of the camera in the horizontal and vertical directions with the image pickup tube 1 is stored in four memory sections of the RAM 41. The RAM 41 can be constructed with, for example, a non-luminescent memory, so that once a centering operation is performed, the television camera can be used in a centered state at any time thereafter.

Since the present invention is configured as described above, it is possible to detect the error signal of the image center position between the image pickup means with extremely high precision, and it is possible to perform automatic centering using this error signal. Therefore, compared to the conventional method of adjusting while looking at the output image,
Very accurate centering can be achieved, and adjustments can be made using normal objects with relatively clear image edges, without the need for special objects for adjustment. Also, since the magnitude of the error signal is converted to the count value of the up-down counter,
Data handling is easy. Furthermore, since the polarity of the error signal controls the increase/decrease in the count of the up-down counter, it is possible to know the number of times the coincident point of the image center position has passed by counting the number of inversions of the count increase/decrease. Therefore, when the number of passes reaches a predetermined number, it can be easily determined that the mutual center positions of the image means have substantially coincided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an image center alignment circuit in a three-tube television camera to which the present invention is applied;
Figure 2 is a waveform diagram of Figure 1, Figure 3 is a circuit diagram of the main part of Figure 1, Figures 4 and 5 are waveform diagrams of Figure 3,
FIG. 6 is a flowchart showing an example of the control function of the image center alignment circuit shown in FIG. 1, and FIG.
8 and 9A to 9C are waveform diagrams of FIG. 7. Regarding the symbols used in the drawings, 1,
2, 3... Image pickup tube, 4, 5... 1H delay line, 6...
... Differential amplifier, 9 ... Multiplier, 10 ... Gate signal generator, 13 ... Gate circuit, 15 ... Differential amplifier, 22 ... Comparator, 23 ... Up-down counter, 30 ... ...stop counter,
G', Ro, Bo...Video output, EDG...Edge signal, REG...Position shift signal, ER...Error signal,
SG...Gate signal.

Claims (1)

[Claims] 1 A circuit for detecting an edge signal of a subject image from an output signal of a first imaging means, a circuit for obtaining a difference signal between output signals of the first imaging means and a second imaging means, and a circuit for obtaining an edge signal of a subject image from an output signal of the first imaging means and a second imaging means a circuit for obtaining a product signal with a difference signal; a circuit for obtaining an error signal of the image center position of each of the first and second imaging means from the product signal; and an up-down counter for converting into A multi-tube imaging device configured to count the number of inversions of an up-down counter and, when the number of inversions reaches a predetermined number, to determine that image center positions of the first and second imaging means substantially coincide.