JPS6249938B2 - - Google Patents
Info
- Publication number
- JPS6249938B2 JPS6249938B2 JP1275280A JP1275280A JPS6249938B2 JP S6249938 B2 JPS6249938 B2 JP S6249938B2 JP 1275280 A JP1275280 A JP 1275280A JP 1275280 A JP1275280 A JP 1275280A JP S6249938 B2 JPS6249938 B2 JP S6249938B2
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- section
- fluctuation
- reference period
- periodic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000000737 periodic effect Effects 0.000 claims description 33
- 230000000630 rising effect Effects 0.000 claims description 14
- 238000001514 detection method Methods 0.000 claims description 9
- 238000003708 edge detection Methods 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 2
- 230000032683 aging Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
- G01R23/15—Indicating that frequency of pulses is either above or below a predetermined value or within or outside a predetermined range of values, by making use of non-linear or digital elements (indicating that pulse width is above or below a certain limit)
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Manipulation Of Pulses (AREA)
Description
【発明の詳細な説明】
本発明は周期パルスの周期変動を１パルスごと
に連続的に検出する周期変動検出回路に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a periodic fluctuation detection circuit that continuously detects periodic fluctuations of periodic pulses on a pulse-by-pulse basis.
従来この種の回路は、一般に周期パルスの立上
りにより単安定マルチバイブレータをトリガして
回路を構成していた。従つて単安定回路で抵抗コ
ンデンサを使用するため経年変化等により時定数
が不安定となり、高精度で信頼性の高い周期変動
検出ができない上、周期パルスの周期および許容
周期変動を任意に設定する場合、単安定の時定数
を再調整しなければならず、簡単に設定できない
という欠点があつた。 Conventionally, this type of circuit has generally been constructed by triggering a monostable multivibrator by the rising edge of a periodic pulse. Therefore, since a resistive capacitor is used in a monostable circuit, the time constant becomes unstable due to aging, etc., making it impossible to detect periodic fluctuations with high accuracy and reliability.In addition, the period of the periodic pulse and the allowable periodic fluctuation must be set arbitrarily. In this case, the monostable time constant must be readjusted, which has the disadvantage that it cannot be easily set.
本発明はこれらの欠点を除去するため、全回路
をICロジツクにより構成するとともに、高速、
高精度のクロツクパルスにより基準周期カウンタ
部および許容変動カウンタ部を動作させ、かつ周
期および許容周期変動の設定を簡単にできるよう
にしたことを特徴とし、任意の周期パルスの周期
変動を１パルスごとに高精度高信頼性で検出する
周期変動検出回路を提供するものである。 In order to eliminate these drawbacks, the present invention configures the entire circuit with IC logic, and also provides high-speed,
The standard cycle counter section and the allowable variation counter section are operated by a high-precision clock pulse, and the cycle and allowable cycle variation can be easily set. The present invention provides a periodic variation detection circuit that detects with high accuracy and reliability.
本発明によれば、周期パルスの立上りを検出す
る立上り検出部と、その立上り検出部より出力さ
れたパルス信号を入力し、２相パルスに変換する
２相パルス発生部と、その２相パルスによりセツ
トされ基準周期カウント後リセツトされる２個の
フリツプフロツプと、基準周期をカウントする２
組の基準周期カウンタ部と、この基準周期カウン
タに基準カウント値を入力する基準周期設定部
と、前記２個のフリツプフロツプＱ出力のエクス
クルシブ オア（EX―CLUSIVE OR）を計算す
るエクスクルシブ オアゲートと、そのエクスク
ルシブ オアゲート出力より得られる変動パルス
のパルス幅を測定する周期変動カウンタ部と、そ
の周期変動カウンタ部に許容変動値をセツトする
許容変動設定部と、前記基準周期カウンタ部と周
期変動カウンタ部にクロツクパルスを送出するク
ロツクパルス発生部とで構成した周期変動検出回
路が得られる。 According to the present invention, there is provided a rise detection section that detects the rise of a periodic pulse, a two-phase pulse generation section that inputs the pulse signal output from the rise detection section and converts it into a two-phase pulse, and a two-phase pulse that detects the rise of a periodic pulse. Two flip-flops that are set and reset after counting the reference period, and two flip-flops that count the reference period.
a reference period counter section, a reference period setting section for inputting a reference count value into the reference period counter, an exclusive OR gate for calculating the exclusive OR (EX-CLUSIVE OR) of the two flip-flop Q outputs, and the exclusive OR gate for calculating the exclusive OR of the two flip-flop Q outputs; A periodic fluctuation counter section that measures the pulse width of the fluctuation pulse obtained from the OR gate output, an allowable fluctuation setting section that sets an allowable fluctuation value in the periodic fluctuation counter section, and a clock pulse that is set in the reference period counter section and the periodic fluctuation counter section. A period fluctuation detection circuit is obtained, which is composed of a clock pulse generating section and a clock pulse generating section.
以下本発明について図を参照して詳細に説明す
る。第１図は本発明の一実施例の構成を示すブロ
ツク図である。立上り検出部１１は被測定周期パ
ルスＰ１の立上り検出を行い、立上り検出パルス
Ｐ２を送出する。２相パルス発生部２１は立上り
検出パルスＰ２を入力し、これを２相パルス信号
であるセツトパルスＳ１，Ｓ２に変換して出力す
る。フリツプフロツプ３１，３２はそれぞれセツ
トパルスＳ１，Ｓ２によりセツトされリセツトパ
ルスＲ１，Ｒ２によりリセツトされる。エクスク
ルシブ オアゲート３３はフリツプフロツプ３
１，３２、Ｑ出力Ｑ１，Ｑ２のエクスクルシブ
オア値として得られる変動パルスＱ３を出力す
る。基準周期カウンタ部４１，４２はそれぞれフ
リツプフロツプＱ出力が論理値“１”のときカウ
ント動作を実行し、基準周期設定部４３によつて
定められた基準周期値Ｔをカウント後、リセツト
パルスＲ１，Ｒ２を出力する。また基準周期カウ
ンタ部４１，４２はカウントクロツクとしてクロ
ツク発生部６１よりクロツクＣ１を入力する。周
期変動カウンタ部５１は変動パルスＱ３が論理値
“１”の状態でカウント動作を実行し、許容変動
設定部５２によつて定められた許容変動値T0以
上のカウントに達したとき周期変動エラー信号Ｅ
を出力する。また周期変動カウンタ部５１はクロ
ツク発生部６１からクロツクＣ２をカウントクロ
ツクとして入力する。第２図は本発明の一実施例
を説明する各信号のタイムチヤートである。 The present invention will be explained in detail below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. The rising edge detection section 11 detects the rising edge of the periodic pulse P1 to be measured, and sends out a rising edge detection pulse P2. The two-phase pulse generator 21 inputs the rising edge detection pulse P2, converts it into set pulses S1 and S2, which are two-phase pulse signals, and outputs the set pulses S1 and S2. Flip-flops 31 and 32 are set by set pulses S1 and S2 and reset by reset pulses R1 and R2, respectively. Exclusive or gate 33 is flip flop 3
1, 32, Q output Q1, Q2 exclusive
A fluctuating pulse Q3 obtained as an OR value is output. The reference period counter sections 41 and 42 each execute a counting operation when the flip-flop Q output is a logical value "1", and after counting the reference period value T determined by the reference period setting section 43, reset pulses R1 and R2 are output. Output. The reference period counter sections 41 and 42 also receive the clock C1 from the clock generation section 61 as a count clock. The periodic fluctuation counter section 51 executes a counting operation when the fluctuation pulse Q3 is at the logical value "1", and when the count reaches the allowable fluctuation value T 0 or more determined by the allowable fluctuation setting section 52, a periodic fluctuation error occurs. Signal E
Output. Further, the period fluctuation counter section 51 receives the clock C2 from the clock generation section 61 as a count clock. FIG. 2 is a time chart of each signal explaining one embodiment of the present invention.
以下本発明について第１図および第２図を参照
して詳細に説明する。まず被測定周期パルスＰ１
の基準周期値Ｔを基準周期設定部４３にセツト
し、許容変動値T0を許容変動設定部５２にセツ
トしておく。今、第２図に示すように被測定周期
パルスのある瞬時における周期の変化をTn，Ｔo
＋１，Ｔo+2…（ｎ：整数）として立上り検出部１
１に入力し、立上り検出パルスＰ２を得る。ここ
で立上り検出パルスＰ２のパルス幅は基準周期Ｔ
より充分小さいものとする。２相パルス発生部２
１は、入力された立上り検出パルスＰ２を第２図
に示すような２相パルスであるセツトパルスＳ
１，Ｓ２に変換して出力する。セツトパルスＳ１
はフリツプフロツプ３１をセツトし、出力Ｑ１を
論理値“１”にする。フリツプフロツプ出力Ｑ１
が論理値“１”になると基準周期カウンタ部４１
は基準周期Ｔのカウントを開始し、カウントが終
了すればリセツトパルスＲ１を出力する。リセツ
トパルスＲ１はフリツプフロツプ３１をリセツト
し、出力Ｑ１を論理値“０”にしてカウントを停
止させる。一方セツトパルスＳ２は被測定周期パ
ルスＰ１の周期Tn後、フリツプフロツプ３２を
セツトし、出力Ｑ２を論理値“１”にする。この
とき、基準周期Ｔと被測定パルスの周期Tnの誤
差は、出力Ｑ１が論理値“０”になるときと、出
力Ｑ２が論理値“１”になるときの時間差で表わ
せる。このときの周期変動は、フリツプフロツプ
出力Ｑ１とＱ２のエクスクルシブ オア値で表わ
すことができる。従つてエクスクルシブ オアゲ
ート３３の出力Ｑ３は周期変動を表わす変動パル
スとなる。この変動パルスＱ３のパルス幅が実際
の周期変動値になる。 The present invention will be explained in detail below with reference to FIGS. 1 and 2. First, the periodic pulse to be measured P1
A reference period value T of 1 is set in the reference period setting section 43, and a permissible fluctuation value T0 is set in the permissible fluctuation setting section 52. Now, as shown in Figure 2, the change in period at a certain instant of the periodic pulse to be measured is Tn,T o
+1 , T o+2 ... (n: integer) as the rising edge detection unit 1
1 to obtain the rising edge detection pulse P2. Here, the pulse width of the rising detection pulse P2 is the reference period T.
It shall be sufficiently smaller. 2-phase pulse generator 2
1 converts the input rising edge detection pulse P2 into a set pulse S, which is a two-phase pulse as shown in FIG.
1, S2 and output. Set pulse S1
sets the flip-flop 31 and makes the output Q1 a logical value "1". Flip-flop output Q1
When becomes the logical value “1”, the reference period counter section 41
starts counting the reference period T, and outputs a reset pulse R1 when the counting ends. The reset pulse R1 resets the flip-flop 31, causing the output Q1 to go to logic "0" and stop counting. On the other hand, the set pulse S2 sets the flip-flop 32 after the period Tn of the period pulse P1 to be measured, and makes the output Q2 a logic value "1". At this time, the error between the reference period T and the period Tn of the pulse to be measured can be expressed as the time difference between when the output Q1 becomes a logic value "0" and when the output Q2 becomes a logic value "1". The periodic fluctuation at this time can be expressed by the exclusive OR value of flip-flop outputs Q1 and Q2. Therefore, the output Q3 of the exclusive OR gate 33 becomes a fluctuating pulse representing periodic fluctuations. The pulse width of this fluctuation pulse Q3 becomes the actual periodic fluctuation value.
次に出力Ｑ２が論理値“１”になれば同様に基
準周期カウンタ部４２は基準周期Ｔのカウントを
開始し、カウントが終了すればリセツトパルスＲ
２を出力する。リセツトパルスＲ２はフリツプフ
ロツプ３２をリセツトし出力Ｑ２を論理値“０”
にしてカウントを停止させる。他方セツトパルス
Ｓ１は被測定周期パルスの周期Ｔo+1後フリツプ
フロツプ３１をセツトし、出力Ｑ１を論理値
“１”にする。このときの周期誤差は出力Ｑ２が
論理値“０”になるときと、出力Ｑ１が論理値
“１”になるときの時間差で表わせる。このとき
のフリツプフロツプ出力Ｑ１とＱ２のエクスクル
シブオア値も変動パルスＱ３になる。以下、前記
の動作をセツトパルスＳ１，Ｓ２により同様に繰
り返す。 Next, when the output Q2 becomes the logical value "1", the reference period counter section 42 similarly starts counting the reference period T, and when the counting is completed, the reset pulse R is output.
Outputs 2. The reset pulse R2 resets the flip-flop 32 and sets the output Q2 to the logical value "0".
to stop the count. On the other hand, the set pulse S1 sets the flip-flop 31 after the period To +1 of the periodic pulse to be measured, and makes the output Q1 a logic value "1". The periodic error at this time can be expressed as the time difference between when the output Q2 becomes a logical value "0" and when the output Q1 becomes a logical value "1". At this time, the exclusive OR value of flip-flop outputs Q1 and Q2 also becomes a fluctuation pulse Q3. Thereafter, the above operation is repeated in the same manner using set pulses S1 and S2.
以上のように変動パルスＱ３が論理値“１”の
ときのパルス幅は１パルスごとの周期変動を与え
る。よつて周期変動カウンタ部５１は変動パルス
Ｑ３が論理値“１”のときカウントを実行する。
このカウント値が許容変動値T0より大きくなれ
ば周期カウンタ部５１はエラー信号Ｅを出力す
る。このようにして任意の周期パルスに対して基
準周期値Ｔおよび許容変動値T0を設定すれば周
期変動を１パルスごとに連続的に検出する周期変
動検出回路を構成できる。 As described above, the pulse width when the fluctuation pulse Q3 has the logical value "1" gives a periodic fluctuation for each pulse. Therefore, the period fluctuation counter section 51 performs counting when the fluctuation pulse Q3 has a logical value of "1".
If this count value becomes larger than the allowable fluctuation value T 0 , the period counter section 51 outputs an error signal E. By setting the reference period value T and allowable fluctuation value T 0 for any periodic pulse in this manner, it is possible to configure a periodic fluctuation detection circuit that continuously detects periodic fluctuations for each pulse.
以上説明したように本発明では、全回路をIC
ロジツクにより構成し、高速高精度のクロツクパ
ルスにより基準周期カウンタ部および周期変動カ
ウンタ部を動作させるとともに基準周期値および
許容変動値を任意に設定できるため、任意の周期
パルスの周期変動を高精度高信頼性で検出する回
路に適用でき大きな効果を奏する。 As explained above, in the present invention, the entire circuit is integrated into an IC
Constructed with logic, the reference period counter section and period fluctuation counter section are operated by high-speed, high-precision clock pulses, and the reference period value and allowable fluctuation value can be set arbitrarily, so period fluctuations of any periodic pulse can be detected with high accuracy and reliability. This method can be applied to circuits that detect signals based on their characteristics, and has great effects.
第１図は本発明の一実施例を示すブロツク図で
あり、１１は立上り検出部、２１は２相パルス発
生部、３１および３２はフリツプフロツプ、３３
はエクスクルシブ オアゲート、４１および４２
は基準周期カウンタ部、４３は基準周期設定部、
５１は周期変動カウンタ部、５２は許容変動設定
部、６１はクロツク発生部である。
第２図は第１図で示す各信号のタイムチヤート
であり、Ｐ１は被測定周期パルス、Ｐ２は立上り
検出パルス、Ｓ１およびＳ２はセツトパルス、Ｑ
１およびＱ２はフリツプフロツプのＱ出力、Ｒ１
およびＲ２はリセツトパルス、Ｑ３は変動パルス
である。
FIG. 1 is a block diagram showing one embodiment of the present invention, in which 11 is a rise detection section, 21 is a two-phase pulse generation section, 31 and 32 are flip-flops, and 33
is exclusive or gate, 41 and 42
43 is a reference period counter section, 43 is a reference period setting section,
51 is a periodic variation counter section, 52 is an allowable variation setting section, and 61 is a clock generation section. Figure 2 is a time chart of each signal shown in Figure 1, where P1 is the periodic pulse to be measured, P2 is the rising edge detection pulse, S1 and S2 are the set pulses, and Q
1 and Q2 are the Q outputs of the flip-flop, R1
and R2 is a reset pulse, and Q3 is a fluctuation pulse.
Claims (1)
と、その立上り検出部より出力された立上りパル
ス信号を入力し２相パルスに変換する２相パルス
発生部と、その２相パルスによりセツトされ基準
周期カウント後リセツトされる２個のフリツプフ
ロツプと、基準周期をカウントする２組の基準周
期カウンタ部と、その基準周期カウンタに基準カ
ウント値を入力する基準周期設定部と、前記２個
のフリツプフロツプＱ出力のエクスクルシブオア
を計算するエクスクルシブオアゲートと、そのゲ
ート出力より得られる変動パルスのパルス幅を測
定する周期変動カウンタ部と、その周期変動カウ
ンタ部に許容変動値をセツトする許容変動設定部
と、前記基準周期カウンタ部と周基変動カウンタ
部にクロツクパルスを送出するクロツクパルス発
生部とで構成したことを特徴とする周期変動検出
回路。1. A rising edge detection section that detects the rising edge of a periodic pulse, a two-phase pulse generation section that inputs the rising pulse signal output from the rising edge detection section and converts it into a two-phase pulse, and a reference period count that is set by the two-phase pulse. Two flip-flops that are subsequently reset, two sets of reference period counter sections that count the reference period, a reference period setting section that inputs a reference count value to the reference period counters, and an exponent of the Q output of the two flip-flops. an exclusive OR gate that calculates the exclusive OR, a periodic fluctuation counter section that measures the pulse width of the fluctuation pulse obtained from the gate output, and an allowable fluctuation setting section that sets a permissible fluctuation value in the periodic fluctuation counter section; A period fluctuation detection circuit comprising the reference period counter section and a clock pulse generation section that sends clock pulses to the frequency base fluctuation counter section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1275280A JPS56110057A (en) | 1980-02-05 | 1980-02-05 | Detecting circuit for periodic fluctuation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1275280A JPS56110057A (en) | 1980-02-05 | 1980-02-05 | Detecting circuit for periodic fluctuation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56110057A JPS56110057A (en) | 1981-09-01 |
| JPS6249938B2 true JPS6249938B2 (en) | 1987-10-22 |
Family
ID=11814137
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1275280A Granted JPS56110057A (en) | 1980-02-05 | 1980-02-05 | Detecting circuit for periodic fluctuation |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56110057A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7085668B2 (en) * | 2004-08-20 | 2006-08-01 | Teradyne, Inc. | Time measurement method using quadrature sine waves |
| JP2007040742A (en) * | 2005-08-01 | 2007-02-15 | Yokogawa Electric Corp | Jitter measuring device |
-
1980
- 1980-02-05 JP JP1275280A patent/JPS56110057A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56110057A (en) | 1981-09-01 |
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