JPS6249990B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a substrate bias voltage generation circuit incorporated into a semiconductor integrated circuit.

Conventionally, this type of substrate bias voltage generation circuit has used two n-channel MOS FETs as charge pumping MOS diodes. A detailed explanation of this can be found in the publication EIectronics, published August 4, 1977.
It is described in the paper by Richard PashIey and others published on pages 103 to 107.

The substrate bias voltage has a negative polarity, and in consideration of reducing junction capacitance and reducing the substrate voltage effect on gate threshold voltage, etc., it is desirable that it be larger to some extent. For example, a random
For access memory, it is desirable to be able to apply a substrate bias voltage of about -3V to -5V. However, the conventional substrate bias voltage generation circuit has a drawback in that it can only apply a substrate bias voltage of -2.7V at most when the power supply voltage is 5V.

The object of the present invention is to provide a
To provide a substrate bias voltage generation circuit capable of generating a sufficiently high substrate bias voltage by using a DSA MOS diode with a low forward threshold voltage and a high reverse threshold voltage as a MOS diode. be.

According to the present invention, an oscillation circuit, a source electrode and a gate electrode are connected to a silicon substrate of a first conductivity type, for example, a P type, and a drain electrode is connected to a first conductivity type silicon substrate of a capacitor.
a first DSA MOS transistor having a channel of a second conductivity type, for example n-type, connected to a terminal of the second conductivity type DSA MOS transistor; a second second conduction type channel having a second terminal connected to the output terminal of the oscillation circuit, and a second second conduction type channel having a source electrode and a gate electrode connected to the first terminal of the capacitor and having a drain electrode grounded.
A substrate bias voltage generation circuit including a DSA MOS transistor can be obtained.

Next, the present invention will be explained with reference to the figures.

FIG. 1 is a circuit diagram of a conventional substrate bias voltage generation circuit. The output voltage of the pulse oscillator 1 is applied between one end 7 of the coupling capacitor 2 and ground. The other end of the coupling capacitor 2 is connected to the node 6,
Grounded via MOS FET4. Therefore,
If the gate threshold voltage of MOS FET4 is V _T4 ,
When a voltage of V _DD ' is output to node 7, node 7
The potential difference V ₇₆ between and node 6 is expressed as follows.

V ₇₆ = V _D ′ _D −V _T4 (1) That is, if the capacitance of capacitor 2 is C ₂ , the charge Qc ₂ stored in capacitor 2 is Qc ₂ = (V _DD ′−V _T4 )・C ₂ ( 2) is expressed as Next, when the potential at node 7 becomes zero, a negative charge of -(V _DD '-V _T4 )C ₂ appears at node 6, and this charge is applied to capacitor 2, the parasitic capacitance between node 6 and substrate 5, and the substrate. The negative potential of the node 6 and the substrate 5 is determined by redistribution to the parasitic capacitance 100 between the node 6 and the ground. Initially, the accumulated charge of the parasitic capacitance 100 is zero, so the initial redistribution of negative charge
Although the negative potential does not become very low, almost the final substrate potential can be obtained after several tens of cycles of the output waveform of the pulse oscillator 1. The final substrate potential is expressed as:

_{V 5 = V T4 + V _ _}
This is the smaller barrier voltage of the MOS FET 3 or the parasitic diode 9. Now, as can be seen from equation (3), in order to obtain a sufficiently large V ₅ , assuming that C ₂ is sufficiently large, either increase V _DD ' or increase V _T4
and to reduce _VX . V _DD ' is essentially a power supply voltage, and since V _DD ' is a value determined by other circuits, it is assumed to be constant, and only V _T4 and V _X are variables whose values can be reduced. normal n channel
In a MOS transistor, the gate threshold voltage does not change depending on the direction of current between the source and drain. Therefore, if V _T4 and _V
Conventional substrate bias voltage generators using MOS transistors cannot reduce V _{T4 and V} It was hot.

FIG. 2 shows a schematic diagram of a substrate bias voltage generation circuit according to the present invention. Pulse oscillator 1
0, a pulse voltage that oscillates between V _DD ' and 0V is output to the output terminal 16. By this pulse voltage, the coupling capacitor 11, the MOS diode 12, and the MOS diode 13, the circuit board 1
4 is applied with a negative voltage. In this circuit
to MOS diode 12 and MOS diode 13
DSA MOS transistors are used. D.S.A.
In a MOS transistor, the gate threshold voltage is generally 1.0V when the drain potential is higher than the source potential.
(Volt) If the source potential is higher than the drain potential, the gate threshold voltage will be 0V.
(Bolt) It has the property of being formed nearby. This circuit utilizes this property. The gate threshold voltage of the MOS diode 13 in the direction from the node 15 to the ground is approximately 0V (volt), and the gate threshold voltage in the direction from the ground to the node 15 is
Since it is about 1V (volt), the threshold voltage is
MOS with low reverse leakage current at 0V (volts)
A diode is used as the MOS diode 13. Similarly, MOS diode 12 has a threshold voltage of 0V (volts) and has low reverse leakage current.
It has become a MOS diode. Therefore _, since V _{T4 and V} In FIG. 2, the black circles of MOS diodes 12 and 13 represent source electrodes.

Above, if the first conductivity type is P type and the second conductivity type is n
Although it has been explained as a type, there is no problem even if it is the other way around.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a conventional substrate bias voltage generation circuit, in which 1 is a pulse oscillator, 2 is a coupling capacitor, 3 is a MOS diode, 4 is a MOS diode, 9 is a parasitic diode by a PN junction, 8
is the parasitic capacitance due to the PN junction, and 100 is the substrate capacitance. FIG. 2 is a schematic diagram of a substrate bias voltage generation circuit according to the present invention, in which 10 is a pulse oscillator, 11 is a coupling capacitor, 12 is a MOS diode using a DSA MOS transistor, and 13 is also a DSA MOS transistor.
MOS diode by MOS transistor, 14
is the substrate.

Claims (1)

[Claims] 1 an oscillation circuit, a first second conductivity type channel DSA MOS transistor whose source electrode and gate electrode are connected to a first conductivity type silicon substrate and whose drain electrode is connected to a first terminal of a capacitor;
a first terminal is connected to said first second conduction type channel;
a capacitor connected to the drain electrode of the DSA MOS transistor and having a second terminal connected to the output terminal of the oscillation circuit; a second capacitor having a source electrode and a gate electrode connected to the first terminal of the capacitor and having a drain electrode grounded; a second conduction type channel DSA MOS transistor; and a substrate bias voltage generation circuit.