JPS6250985B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a complementary MOS circuit that prevents the latch-up phenomenon from occurring.

Generally CMOS type IC (complementary MOS type integrated circuit)
When a noise pulse is applied to the input and output sections, an abnormally large current of several mA to several + mA begins to flow between the power supply terminals. This phenomenon is called latch-up and is a serious problem in CMOS ICs. The above latches can be used to lower the power supply voltage or
It won't stop unless you turn off the current, and if you leave it alone
The IC will be destroyed.

FIG. 1 is a CMOS inverter circuit, FIG. 2 is a schematic cross-sectional view showing the IC configuration of the inverter, and FIG. 3 is an equivalent circuit of parasitic elements of the same configuration. In these figures, 1 is a P-channel MOS
Transistors, 2 is an N-channel MOS transistor, 3 is a signal input terminal, 4 is an output terminal, 5 is a power supply V _DD supply terminal, Tr ₁ to _{Tr 4} are N-type layers of Nsub (N-type substrate) 6, P-type Rnsub is a parasitic resistance formed in the substrate 6, and Rpwell is a parasitic resistance formed in the P-well layer 7.

In the equivalent circuit shown in Figure 3, the following conditions are generally required for the latch-up to hold true:
is raised.

Transistor Tr ₁ and configuring the thyristor
Tr ₂ operates as a transistor.

Since a constant current (due to latch-up) flows, the product of the common emitter current amplification factors β _pop1 and β _opo2 of transistors Tr ₁ and Tr ₂ is β _pop1 · β _opo2
Condition 1 is satisfied.

Presence of abnormal noise current.

Conventional methods for eliminating these problems include the following. That is, by performing dielectric separation, transistors Tr ₁ and Tr ₂ are not formed. However, this method complicates the manufacturing process, resulting in high costs and is not practical. Another method is to create a P ⁺ type buried layer in the P-well layer 7 to lower the current amplification factor β _opo2 of the transistor Tr ₂ to suppress latch-up. However, this method also increases the number of steps and costs. In terms of pattern, by increasing the distance between the P-well layer 7 and the drain layer of the P-channel MOS transistor 1, β _pop1 can be lowered, and in terms of manufacturing, lifetime killers such as gold can be diffused. Therefore, methods have been considered to lower β _pop1 and β _opo2 , but in either case, the area per gate increases, the leakage current increases, and the characteristics deteriorate. As described above, the conventional latch-up prevention method complicates the manufacturing process, resulting in high costs and deterioration of characteristics.

The present invention has been made in view of the above circumstances, and by forming a Schottky diode using the electrical wiring of a complementary MOS circuit, it is possible to suppress the latch-up phenomenon without causing the conventional problems. The purpose is to provide a semiconductor device.

An embodiment of the present invention will be described below with reference to the drawings. Note that this embodiment is an example in which it corresponds to that of the conventional example, so corresponding parts are given the same reference numerals, explanations are omitted, and different points will be explained. The features of this embodiment are as shown in FIGS. 4 and 5, P channel type MOS transistors 1, N
By using the source or drain electrode 11 of the channel type MOS transistor 2 and providing a Schottky diode D _S connecting the emitters and bases of the parasitic bipolar transistors Tr ₁ to _{Tr 4} in the vicinity thereof, This diode is used as a clamping diode to suppress the common emitter current amplification factor of the parasitic bipolar transistor to an incomparably small level compared to the conventional one, thereby preventing latch-up from occurring.

Generally, an N-type substrate has a donor concentration of about 10 ¹⁵ cm ^-3 and a P-well layer has a surface concentration of about 10 ¹⁶ cm ^-3 . Schottky diodes can be easily obtained for concentrations of this order, and suitable Schottky metals include, for example, Al, Ti,
W, Pt, and Ti--w alloys may be used, and with this, a transistor with a Schottky diode can be formed.

As a practical problem, it is not necessary to equip all parasitic transistors with Schottky diodes; if one of them is equipped with one, the grounded emitter current amplification factor can be kept extremely low, but especially in P. If a Schottky diode D _S is provided at the drain of the channel transistor 1 or the source of the N-channel transistor 2, the latch-up phenomenon can be effectively suppressed.

As explained above, according to the present invention, a Schottky diode can be formed using the electrode wiring of a CMOS circuit, without complicating the manufacturing process, increasing the area, or deteriorating the characteristics. Accordingly, a semiconductor device capable of preventing latch-up can be provided.

[Brief explanation of the drawing]

FIG. 1 is a CMOS inverter circuit diagram, FIG. 2 is a sectional view showing the IC structure of the circuit, FIG. 3 is an equivalent circuit diagram obtained by the same structure, and FIG. 4 is a sectional view of an embodiment of the present invention. FIG. 5 is an equivalent circuit diagram thereof. 1...P channel type MOS transistor, 2...N
Channel type MOS transistor, 6...N type substrate,
7...P-well layer, 11...electrode wiring, _Ds ...shotkey diode.

Claims (1)

[Claims] 1. A complementary MOS circuit formed on a semiconductor substrate, a latch-up phenomenon generating circuit consisting of a bipolar transistor circuit parasitically forming a thyristor in the circuit, and a latch-up prevention circuit that connects the base and emitter of the bipolar transistor of the circuit. A semiconductor device comprising a Schottky diode.