JPS6251035B2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention provides information such as characters, symbols, graphics, etc. transmitted in a time-division multiplexed manner to an unused area such as the vertical blanking period of a television signal. (hereinafter referred to as character information) is extracted and stored in a memory, and then read out from the memory and superimposed on a part of the video signal of the television signal, or displayed independently on the television screen separately from the video signal. This invention relates to a circuit for generating clock pulses for writing character signals and displaying character information on a television screen in a teletext receiver.

<Prior art> A teletext receiving device uses a clock pulse (hereinafter referred to as a write clock) for writing a character signal into a memory and a clock pulse (hereinafter referred to as a display clock) for displaying character information stored in the memory on a television screen. It generates two types of clock pulses:

FIG. 1 shows a block diagram of a proposed clock pulse generation circuit for a teletext receiver.

In this circuit, the reproduced color subcarrier is multiplied by 8 in the multiplier circuit 1 to 28.636 MHz, and further divided by 5 in the frequency dividing circuit 2 to obtain a predetermined clock of 5.73 MHz.

Here, the clock run-in signal (hereinafter referred to as CRI signal. The CRI signal will be described later) in the character signal is input as a reset signal to the 5 frequency division counter of frequency divider circuit 2, and synchronized with the character signal. In other words, the write clock is obtained.

In addition, a horizontal synchronizing signal (hereinafter referred to as H pulse) obtained within the television receiver is input as a reset signal to this 5 frequency division counter together with the CRI signal to obtain a clock synchronized with the H pulse, in other words, a display clock. There is. For details of this clock pulse generation circuit, reference may be made to, for example, Japanese Patent Application No. 53-142-1988, ``Jitter Suppression Device for Teletext Broadcasting Receiver,'' filed by the same applicant.

<Problems to be Solved by the Invention> The disadvantages of this clock pulse generation circuit are as follows.

(1) When the superimposition position of the multiplexed character signal changes with respect to the H pulse, there is a jitter of one clock of 28.636 MHz (approximately 35 ns).

(2) When receiving in a weak electric field area, the noise component of the reproduced color subcarrier increases as the electric field strength decreases, affecting the clock pulse and increasing jitter.

(3) Since a multiplier circuit is required, the circuit becomes complicated and the circuit space is large.

(4) Since the CRI signal is directly used as the reset signal, the write clock becomes inaccurate due to jitter in the CRI signal.

<Means for Solving the Problems> In view of the above points, the present invention provides a clock pulse generation circuit for stably storing character signals in a memory and displaying character information on a television screen without jitter. It is characterized by obtaining a predetermined clock pulse by a phase-locked loop (hereinafter referred to as PLL) circuit based on the flyback pulse (hereinafter referred to as FBP) obtained by a television receiver. do.

FIG. 2 shows a block diagram of a clock pulse generation circuit according to the present invention.

In this clock pulse generation circuit, a voltage controlled oscillator (hereinafter referred to as VCO) 10 oscillates at 5.73MHz, and a frequency divider 11 generates a frequency of 1/364 (15.73KHz).
The phase comparator 12 compares the phase of this signal with the FBP (15.73KHz) obtained from a television receiver, and the PLL controls the VCO 10 with the phase comparison output.
Configure the circuit. Note that 13 is a low-pass filter.

In this PLL circuit, for example, the oscillation of VCO10 is
By controlling the clock so that it can be temporarily stopped in synchronization with the signal (CRI integral signal), the oscillation output of the VCO 10, that is, the clock pulse, can provide a write clock synchronized with the CRI signal and a display clock synchronized with the FBP. It can be done.

<Function> The advantages of the clock pulse generation circuit using this PLL circuit are as follows.

(1) The jitter of the clock pulse can be made smaller than in the conventional circuit due to the stability of the VCO 10 and the stability of the system.

(2) Even if the electric field strength decreases, it does not affect the FBP itself, so jitter does not increase.

(3) The circuit becomes simpler.

(4) Write clock becomes accurate.

<Embodiment> An embodiment of the clock pulse generation circuit according to the present invention will be described in detail below with reference to FIG.

Of the write clock and display clock necessary for a teletext receiver, the generation of the display clock will be described first.

The display clock is a clock pulse for reading character information from the memory and displaying it on part or all of the television screen. Display of textual information without jitter requires that the display clock be synchronized with the horizontal output signal of the television receiver. For this reason, the clock pulse generation circuit according to the present invention uses a PLL circuit based on the FBP obtained in a television receiver. That is, VCO1
0 is oscillated at 5.73MHz, which is the display clock, and this output is divided by 364 using the frequency divider 11 to reduce the frequency to 15.73KHz.Then, it is input to the phase comparator 12 along with FBP, and if there is a phase difference, it is calculated by that amount. Takes out the output according to the phase difference. After passing this output through a low-pass filter (hereinafter referred to as LDF) 13, it is added to the VCO 10 to control the oscillation frequency. In this way, a clock (display clock) matching the phase of the FBP is obtained as the output of the VCO 10.

Note that when this display clock is generated, the reset input of the CRI integral signal to the voltage controlled oscillator 10 is cut off, and the phase is matched only to FBP.

Since the display clock is generated based on FBP, there is little jitter in the text information displayed on the TV screen, and a stable lock is always obtained even when the field strength of the TV radio waves decreases.

Next, the generation of the write clock will be described. The write clock is a clock for reproducing character signals in the video signal. In order to reproduce a character signal without error, it is not enough that the frequency matches the clock rate of the character signal; it is also necessary to match the phase.

Character signals always have a CRI signal (1, 0, 1, 0) at the beginning as a clock synchronization signal.
..., 1, 0'' repeating signals for 16 bits are sent out. Figure 3 shows a detailed diagram of the CRI signal.

The clock pulse generator is composed of a PLL circuit that generates a display clock whose phase matches that of FBP, and is configured so that the output of this circuit can be used as a write clock as a clock synchronized with the CRI signal.

During the horizontal scanning period in which character signals are superimposed (hereinafter referred to as multiple horizontal scanning period), a signal obtained by integrating the CRI signal (hereinafter referred to as
This is called the CRI integral signal. ) is used to key VCO10. That is, by stopping the oscillation of the VCO 10 while the CRI integral signal is being input and restarting the oscillation at the trailing edge of the CRI integral signal, a write clock whose phase matches the character signal is obtained.

FIG. 4 is a timing chart explaining this operation, in which (i) shows the CRI signal, (ii) shows the CRI integral signal, and (iii) shows the period during which the oscillation of the VCO 10 is stopped.

Here, using a signal obtained by integrating the CRI signal is
This is to obtain a more accurate write clock by averaging the jitter of the 16-bit CRI signal. Note that it will be understood that stopping the oscillation of the VCO 10 can be suppressed by using the CRI signal or a signal responsive to the CRI signal without using the CRI integral signal.

Now, when it comes to the multiple horizontal scanning period, H
The PLL circuit is locked by the pulse (FBP).
The frequency of VCO 10 is held at 5.73MHz.
That is, the frequency control voltage of the VCO 10 is constant during multiple horizontal scanning periods. It goes without saying that the characteristics of the low-pass filter 13 are appropriately selected.

When a CRI integral signal is input to the VCO 10 as a keying input while this lock is applied, the VCO 10 temporarily stops oscillating in response to the CRI integral signal, and then resumes oscillation. Specifically, the VCO 10 is configured to stop oscillating when the CRI integral signal exceeds _V0 . for example,
As the VCO 10, it is possible to use a multivibrator that oscillates while the CRI integral signal is smaller than _V0 .

Therefore, when the CRI integral signal rises and becomes equal to or higher than V ₀ , the VCO 10 stops oscillating, and when the CRI integral signal subsequently decreases and becomes smaller than V ₀ , the VCO 10 starts oscillating again. At this time, the frequency control voltage applied to the VCO 10 is the original voltage held constant during the multiple horizontal scanning period as described above, so the oscillation frequency is constant at 5.73MHz.

In this way, a write clock whose phase matches that of the CRI signal is obtained as the output of the VCO 10, and the phase is optimal for writing the control and character pattern signals sent following the CRI signal in the character signal.

Here, the VCO 10 is configured such that the reference voltage of the comparator provided on the input side can be adjusted by a variable means, so that the write clock is optimal for control sent following the CRI signal and for writing character pattern signals. Of course, if a Schmitt circuit with a fixed reference voltage is used as this comparator, it is possible to adjust the phase of the clock to the optimum phase using a phase shifter. It is possible.

Therefore, in the above clock pulse generation circuit, both the write clock and display clock clock pulses are generated by the same VCO 10, and during the multiplex horizontal scanning period _TA , the write clock that matches the phase of the character signal is also generated. Text information display period T
During _B , a display clock matching the phase of FBP is obtained.

That is, as shown in FIG. 5, in one field, the multiple horizontal scanning period T _A becomes the write clock valid period and writing is executed, while the display period T _B
is the valid period of the display clock, and the display is executed.

The clock generation circuit according to the present invention can also be applied to cases where the write clock and display clock have different frequencies and the frequency ratio of both clock pulses is expressed as a simple integer ratio. As an example, the write clock is 5.73MHz and the display clock is 11.45MHz.
FIG. 6 shows a block diagram of a clock pulse generating circuit in the case of Hz, that is, a frequency ratio of 1:2. VCO10 is the write clock, 5.73MHz
PLL to oscillate and match the phase of FBP.
form a circuit. Key VCO10 with the CRI integrator to obtain a 5.73MHz write clock. These are further doubled by the doubling circuit 14 to 11.45M.
Get the display clock in Hz.

<Effects of the Invention> According to the teletext receiving device of the present invention, the same
The VCO can generate a write clock and a display clock, and the phase of the write clock can be made to match the phase of the signal for clock synchronization of character signals, so character signals can be written to memory properly. Since the phase of the display clock is made to match the phase of FBP, it is possible to reduce jitter when displaying character information, and the write clock and display clock are generated using FBP as a reference. Therefore, stable operation can be obtained even when receiving in areas with weak electric fields.

[Brief explanation of the drawing]

Figure 1 shows a block diagram proposed as a clock generator for a teletext receiver.
FIG. 2 is a block diagram of the clock generator according to the present invention, FIG. 3 is an explanatory diagram explaining the details of the CRI signal of the character signal, FIG. 4 is a timing chart explaining the operation of the same, and FIG. 6 shows an explanatory diagram for explaining the valid periods of a write clock and a display clock, respectively, and FIG. 6 shows a block diagram of another embodiment of the present invention. 10: Voltage controlled oscillator (VCO), 12: Phase comparator.

Claims (1)

[Claims] 1. Receive character signals such as characters and figures multiplexed during the vertical blanking period of a television signal, store these character signals in a memory using clock pulses synchronized with these, and read them from there. A teletext receiving device configured to display a teletext broadcast includes a voltage controlled oscillator whose oscillation frequency is controlled based on a flyback pulse obtained within the television receiver, and the oscillation from the voltage controlled oscillator When using the received output character signal as a clock pulse for writing into memory, an oscillation output reset by a signal obtained by integrating the clock synchronization signal included in the character signal is derived, and the output is stored in memory. What is claimed is: 1. A teletext receiving device characterized in that, when used as a clock pulse for displaying a character signal, switching control is performed to derive an oscillation output synchronized with a flyback pulse.