JPS6251498B2 - - Google Patents
Info
- Publication number
- JPS6251498B2 JPS6251498B2 JP56089578A JP8957881A JPS6251498B2 JP S6251498 B2 JPS6251498 B2 JP S6251498B2 JP 56089578 A JP56089578 A JP 56089578A JP 8957881 A JP8957881 A JP 8957881A JP S6251498 B2 JPS6251498 B2 JP S6251498B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- bonded
- cooling
- flow channel
- metal foil
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W40/00—Arrangements for thermal protection or thermal control
- H10W40/70—Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
- H10W40/77—Auxiliary members characterised by their shape
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/877—Bump connectors and die-attach connectors
Landscapes
- Cooling Or The Like Of Electrical Apparatus (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体素子を基板にフエイスダウン接
合する形式の電子装置の冷却装置に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a cooling device for an electronic device in which a semiconductor element is face-down bonded to a substrate.
従来の電子装置の冷却装置を第１図により説明
する。 A conventional cooling device for an electronic device will be explained with reference to FIG.
第１図において、基板１に接合された半導体チ
ツプ２と冷却液の流水路３ａを有する冷却板３と
接続したキヤツプ４との間に熱伝達接続体が形成
される。この熱伝達接続体は一方が良好な熱的相
互接続を設けるように金属箔の束５を半田付けな
どによつて背板６への取付け溝として働く溝７に
組付けられ、他方は半導体チツプ２と接触させ
る。また、金属箔の束５は束の端部を同時に保持
しかつ微小分割によつて形成された個々の小さな
箔を保護する働きをする弾性スリーブ８を束５の
周辺部に備えている。金属箔の束５の長さは半導
体チツプ２に加えられる力が良好な熱伝導接触面
を与えるのに必要な量以内にあり、かつ半導体チ
ツプ２に加えることができる最大力を越えない程
度にする。 In FIG. 1, a heat transfer connection is formed between a semiconductor chip 2 bonded to a substrate 1 and a cap 4 connected to a cooling plate 3 having a cooling fluid flow channel 3a. This heat transfer connection is assembled, on one side, by soldering or the like with a metal foil bundle 5 into a groove 7 which serves as a mounting groove in the back plate 6 to provide a good thermal interconnection, and on the other side a semiconductor chip. 2. The bundle 5 of metal foils is also provided with an elastic sleeve 8 around the periphery of the bundle 5, which serves to simultaneously hold the ends of the bundle and protect the individual small foils formed by micro-division. The length of the metal foil bundle 5 is such that the force applied to the semiconductor chip 2 is within the amount necessary to provide a good thermally conductive contact surface and does not exceed the maximum force that can be applied to the semiconductor chip 2. do.
しかし、このような従来技術にはつぎのような
問題点があげられる。 However, such conventional technology has the following problems.
(1) 熱伝達接続体は、構成部材である金属箔の束
５、溝７、弾性スリーブ８などが組み合わされ
たもので構造が複雑であり、且つ組み合わされ
た状態で大きいため、冷却装置が厚くなる。(1) The heat transfer connector is a combination of constituent members such as a bundle of metal foil 5, a groove 7, an elastic sleeve 8, etc., and has a complex structure. It gets thicker.
(2) 半導体チツプ２と金属箔の束５との接触条件
が微妙であり、熱伝達接続体構成部材の加工お
よび組立に精度を要する。(2) The contact conditions between the semiconductor chip 2 and the metal foil bundle 5 are delicate, and precision is required in processing and assembling the components of the heat transfer connector.
本発明は、半導体素子と素子冷却用構造体とを
接合した場合、その接合部および半導体素子のフ
エイスダウン接合部などに発生する熱ひずみを軽
減することができる電子装置の冷却装置を提供す
ることを目的とするものである。 An object of the present invention is to provide a cooling device for an electronic device that can reduce thermal strain that occurs at the bonded portion and the face-down bonded portion of the semiconductor device when a semiconductor device and a device cooling structure are bonded. The purpose is to
本発明の特徴とするところは基板に半導体素子
をフエイスダウン接合する形式の電子装置におい
て、金属膜を蒸着した半導体素子に金属箔より成
る熱伝導板を半田により接合し、この熱伝導板の
半導体素子接合側の裏側を冷却用流水路とし、前
記熱伝導板の半導体素子と接合する領域以外の部
分に熱ひずみを吸収する突起を設けたものであ
る。 The present invention is characterized in that in an electronic device in which a semiconductor element is face-down bonded to a substrate, a heat conductive plate made of metal foil is bonded to a semiconductor element on which a metal film is deposited by soldering, and the semiconductor element on this heat conductive plate is A cooling flow channel is provided on the back side of the element bonding side, and projections for absorbing thermal strain are provided in a portion of the heat conductive plate other than the area bonded to the semiconductor element.
以下に本発明の実施例を第２図〜第５図により
説明する。第２図はパツケージの全体構造図であ
る。基板９に複数個の半導体素子１０が半田ボー
ル１１によりフエイスダウン接合される。半導体
素子１０の背面には金属膜が蒸着され、半田付け
が可能であり、この半導体素子１０には半田層１
２により薄い金属箔１３、例えば、アルミニウ
ム、銅などから成る箔またはメツキ箔が接合され
る。 Embodiments of the present invention will be described below with reference to FIGS. 2 to 5. FIG. 2 is a diagram showing the overall structure of the package. A plurality of semiconductor elements 10 are face-down bonded to a substrate 9 using solder balls 11 . A metal film is deposited on the back surface of the semiconductor element 10 and can be soldered, and the semiconductor element 10 has a solder layer 1
2, a thin metal foil 13, for example, a foil made of aluminum, copper, etc., or a plating foil is bonded.
この金属箔１３の反接合面側は冷却板１４とと
もに冷却用流水路１４ａを形成することにより単
純で、かつ冷却効果の大きい構造となつている。 The opposite surface side of the metal foil 13 forms a cooling flow channel 14a together with the cooling plate 14, resulting in a simple structure with a large cooling effect.
この金属箔１３には、第３図に示すように半導
体素子１０を接合する面以外の部分を接合面の反
対側に凸状とした突起１５が設けられる。突起１
５の幅、高さ、および隅部と先端の円弧の半径な
どは半導体素子１０の配置間隔に応じて最適値を
定める。また、半導体素子１０を基板９へ接合す
る半田ボール１１の配置により熱ひずみが特定方
向に主として生ずることが予想される場合には、
第４図のように熱ひずみを吸収する必要のある方
向にのみに突起１５を設けるようにしても良い。
さらに、ひずみ方向を想定できない場合には、第
５図のように半導体素子１０を接合する部分のみ
を円形とし他の部分を凸状とした突起１５を設け
るようにしても良い。 As shown in FIG. 3, this metal foil 13 is provided with a protrusion 15 whose portion other than the surface to which the semiconductor element 10 is bonded has a convex shape on the opposite side of the bonding surface. Protrusion 1
The width, height, radius of the corner and tip of the semiconductor element 5, and the radius of the arc are determined to be optimum values according to the arrangement interval of the semiconductor elements 10. Furthermore, if thermal strain is expected to occur mainly in a specific direction due to the arrangement of the solder balls 11 that join the semiconductor element 10 to the substrate 9,
As shown in FIG. 4, the protrusions 15 may be provided only in the direction necessary to absorb thermal strain.
Furthermore, if the strain direction cannot be assumed, a protrusion 15 may be provided in which only the part where the semiconductor element 10 is bonded is circular and the other part is convex, as shown in FIG.
つぎに、本発明の実施例の作用を述べる。第２
図に示すようなパツケージにおいて半田ボール１
１を介し半導体素子１０が接合される構造では、
半導体素子１０と基板９の熱膨張係数の違い及び
温度差に伴なう熱膨張の差が生ずる。この熱膨張
の差は半導体素子１０と基板９を接合する半田ボ
ール１１にひずみとして加わる。このひずみは、
パツケージの電源をオン、オフすることにより変
化するため、半田ボール１１はひずみの繰返しを
受け、ひずみの程度により疲労破壊する。また、
熱の発生源である半導体素子１０は温度によつて
特性が変化する場合がある。このため、半導体素
子１０の温度を適温に保つ効果と温度差に伴なう
熱ひずみを低減する目的により半導体素子１０を
冷却し、パツケージの信頼性を維持している。温
度差による熱ひずみを低減するために冷却用流水
路１４ａに熱を伝導する方法として最適なものは
半導体素子１０と冷却用流水路１４ａを完全接合
する構造である。しかし、冷却用流水路１４ａを
剛性の高い構造とした場合、冷却用流水路部構成
部材と半導体素子との熱膨張係数の違い及び両者
の温度差により、両者を接合した部分に熱ひずみ
が生じる。この熱ひずみは半導体素子の両接合面
において強度的に弱い方に集中することになる。 Next, the operation of the embodiment of the present invention will be described. Second
Solder ball 1 in the package as shown in the figure.
In the structure in which the semiconductor element 10 is bonded via 1,
There is a difference in thermal expansion coefficient between the semiconductor element 10 and the substrate 9, and a difference in thermal expansion due to the temperature difference. This difference in thermal expansion is applied as strain to the solder balls 11 that join the semiconductor element 10 and the substrate 9. This strain is
Since the solder balls 11 are subjected to repeated strain as the power to the package is turned on and off, the solder balls 11 undergo fatigue failure depending on the degree of strain. Also,
The characteristics of the semiconductor element 10, which is a heat generation source, may change depending on the temperature. Therefore, the semiconductor element 10 is cooled to maintain the temperature of the semiconductor element 10 at an appropriate temperature and to reduce thermal strain caused by temperature differences, thereby maintaining the reliability of the package. The most suitable method for conducting heat to the cooling flow channel 14a in order to reduce thermal strain due to temperature differences is a structure in which the semiconductor element 10 and the cooling flow channel 14a are completely joined. However, when the cooling flow channel 14a has a highly rigid structure, thermal strain occurs in the part where they are joined due to the difference in thermal expansion coefficient between the cooling flow channel component and the semiconductor element and the temperature difference between the two. . This thermal strain is concentrated on the weaker side of both bonding surfaces of the semiconductor element.
そこで本実施例のように冷却用流水路部に例え
ば、アルミニユーム、銅などからなる金属箔１３
またはメツキ箔を用い、この金属箔１３に突起１
５を設ける形状として剛性を低下させる。 Therefore, as in this embodiment, for example, a metal foil 13 made of aluminum, copper, etc. is used in the cooling flow channel section.
Alternatively, use plating foil and place the protrusion 1 on this metal foil 13.
5 reduces the rigidity.
この構造においては、冷却用流水路部と半導体
素子の間に発生する熱ひずみは金属箔１３の膨張
と剛性の低い突起１５の変形により吸収すること
ができる。このため、たとえば第２図に示すよう
に半導体素子１０を基板側には半田ボール１１に
より接合し、冷却用流水路側には完全接合した場
合、半田ボール１１に加わる熱ひずみは半導体素
子１０と基板９との熱膨張差と温度差により生ず
るひずみだけとなり、半田ボール１１の疲労強度
を著るしく向上させることになる。 In this structure, thermal strain generated between the cooling water channel and the semiconductor element can be absorbed by expansion of the metal foil 13 and deformation of the protrusions 15 having low rigidity. For this reason, for example, if the semiconductor element 10 is bonded to the substrate side with the solder balls 11 and completely bonded to the cooling flow channel side as shown in FIG. 2, the thermal strain applied to the solder balls 11 will be Only the strain caused by the thermal expansion difference and temperature difference between solder ball 9 and solder ball 11 is reduced, and the fatigue strength of solder ball 11 is significantly improved.
以上に詳述したように、本発明においてはフエ
イスダウンした半導体素子の背面に金属膜を蒸着
し冷却用流水路側に完全接合した場合、接合部に
発生する熱ひずみを、冷却用流水路側の部材に突
起を有する箔を用いることにより低減することが
できる。 As described in detail above, in the present invention, when a metal film is vapor-deposited on the back surface of a face-down semiconductor element and the metal film is completely bonded to the cooling flow channel side, the thermal strain generated at the bonded portion is absorbed by the member on the cooling flow channel side. This can be reduced by using a foil with protrusions.
また、突起を有する箔を冷却用流水路の一部と
することにより、構造を単純化するとともに冷却
効率を大きくできる。 Further, by using the foil having projections as part of the cooling flow channel, the structure can be simplified and the cooling efficiency can be increased.
第１図は従来の熱伝達接続体の構造図、第２図
は本発明の効果を説明するためのパツケージの構
造図、第３図、第４図、第５図は箔の断面構造図
である。
１……冷却板、２……キヤツプ、３……背板、
４……金属箔の束、５……溝、６……フランジ、
７……ピン、８……基板、９……チツプ、１０…
…弾性スリーブ、１１……冷却板、１２……箔、
１３……半田層、１４……半導体素子、１５……
半田ボール、１６……基板、１７……突起。
Fig. 1 is a structural diagram of a conventional heat transfer connection body, Fig. 2 is a structural diagram of a package for explaining the effects of the present invention, and Figs. 3, 4, and 5 are cross-sectional structural diagrams of a foil. be. 1... Cooling plate, 2... Cap, 3... Back plate,
4... Bundle of metal foil, 5... Groove, 6... Flange,
7...pin, 8...board, 9...chip, 10...
...Elastic sleeve, 11...Cooling plate, 12...Foil,
13...Solder layer, 14...Semiconductor element, 15...
Solder ball, 16...board, 17...protrusion.
Claims (1)
形式の電子装置において、金属膜を蒸着した半導
体素子に金属箔より成る熱伝導板を半田により接
合し、この熱伝導板の半導体素子接合側の裏側を
冷却用流水路とし、前記熱伝導板の半導体素子と
接合する領域以外の部分に熱ひずみを吸収する突
起を設けたことを特徴とする電子装置の冷却装
置。1. In an electronic device in which a semiconductor element is face-down bonded to a substrate, a heat conductive plate made of metal foil is bonded to the semiconductor element on which a metal film is vapor-deposited by soldering, and the back side of the heat conductive plate on the side where the semiconductor element is bonded is cooled. 1. A cooling device for an electronic device, characterized in that a projection for absorbing thermal strain is provided in a portion of the heat conductive plate other than a region bonded to a semiconductor element as a water flow channel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56089578A JPS57206055A (en) | 1981-06-12 | 1981-06-12 | Cooling system for electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56089578A JPS57206055A (en) | 1981-06-12 | 1981-06-12 | Cooling system for electronic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57206055A JPS57206055A (en) | 1982-12-17 |
| JPS6251498B2 true JPS6251498B2 (en) | 1987-10-30 |
Family
ID=13974675
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56089578A Granted JPS57206055A (en) | 1981-06-12 | 1981-06-12 | Cooling system for electronic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57206055A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6275599U (en) * | 1985-10-30 | 1987-05-14 | ||
| JPH01106992U (en) * | 1988-01-06 | 1989-07-19 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4531146A (en) * | 1983-07-14 | 1985-07-23 | Cutchaw John M | Apparatus for cooling high-density integrated circuit packages |
-
1981
- 1981-06-12 JP JP56089578A patent/JPS57206055A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6275599U (en) * | 1985-10-30 | 1987-05-14 | ||
| JPH01106992U (en) * | 1988-01-06 | 1989-07-19 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57206055A (en) | 1982-12-17 |
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