JPS6252330B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a data conversion circuit that converts fixed point data to floating point data without performing conditional processing. Traditionally, algorithms for converting fixed-point data to floating-point data have
Processing is divided by negative signs; for example, if a flowchart shows a processing process, positive and negative conditions are determined and paths are branched. Therefore, overhead of condition determination occurred, and the calculation processing speed was extremely slow. The software for converting fixed-point data to floating-point data was not easy to use because it required conditional judgment. The present invention eliminates the above-mentioned drawbacks of the conventional method and enables high-speed arithmetic processing from fixed-point data to floating-point data with one hardware instruction without the need to determine the positive or negative sign of fixed-point data. The purpose is to provide a conversion method. The present invention is characterized by a first register section connected to an input data bus and having a data width corresponding to the mantissa part of floating point data; an inverting circuit that inverts only the bit corresponding to the sign bit of the fixed-point data; a second register section connected to the input data bus and storing data corresponding to the exponent part of the floating-point data; and the first and second register sections. The floating point subtraction circuit inputs all the outputs of the register section as the A operand, and the fixed point data whose sign bit is inverted by the inverting circuit is placed in the first register section, and the fixed point data is inputted into the first register section. Adjustment data for moving the decimal point position of the fixed-point data to the decimal point position of the mantissa part of the floating-point data is input into the part, and the B operand of the floating-point subtraction circuit is a bit corresponding to the sign bit of the fixed-point data. The bits corresponding to the mantissa part of the floating point data up to the logic level are all logic 0, and the bits corresponding to the exponent part of the floating point data are fixed data similar to the adjustment data added to the second register part. A is input into the floating point subtraction circuit.
This is a data conversion circuit from fixed-point data to floating-point data by performing floating-point subtraction using operands and B operands and outputting normalized floating-point data to an output data bus. An embodiment of the present invention will be described below with reference to the drawings. A data conversion circuit that converts fixed-point data to normalized floating-point data is connected to data bus 1.
A address register 20 input and connected to 0, A
+1 address register 30, A+2 address register 4
It has an inverting circuit 60 connected to the most significant bit input of the 0, A+3 address register 50 and the A+2 address register 40, and each register 20, 30, 40, 5
The output of 0 is connected to a floating point subtraction circuit 70. Now, fixed-point data D _I is 2 bytes long (16 bits), and 4 bits is one unit.
Using hexadecimal notation, write D _I = H ₃ H ₂ H ₁ H ₀ . Here, H _i (i=3, 2, 1,
0) is di _j (j=3, 2, 1, 0) 1 or 0
If the digit is H _i =di ₃ di ₂ di ₁ di ₀ , it is a hexadecimal number of 4 bits per unit. Fixed-point display is a display in which the position of the decimal point is determined at a specific position in one word.
Assume that it is on the right side of H ₀ . There are ²⁴ possible values for H _i , and it is common practice to represent these 16 numbers using 10 numbers and 5 alphabetic characters as shown in Table 1.

[Table] As a first specific example of fixed-point data _DI , _DI ⁺ = (0001) ₁₆ = (0000 0000 0000 0001) ₂ = (+1) ₁₀ is given. Here (...) ₁₆ , (...) ₂ , (...
...) ₁₀ represents hexadecimal representation, binary representation, and decimal representation, respectively. Therefore, since the decimal point is on the right side of D _I ⁺ , D _I ⁺ =0×16 ³ +0×16 ² +0×16 ¹ +1×16 ⁰ (16
decimal system) =0×2 ¹⁵ +0×2 ¹⁴ +...+0×2 ³ +0×2 ² +0×2 ¹ +1×2 ⁰ (binary system) =+1×10 ⁰ (decimal system), and D _I ⁺ represents +1 in decimal notation. The most significant bit d ₃₃ of the 16-bit fixed-point data _DI is a sign bit, and when d ₃₃ = 0, the data _DI is a positive number, and when d ₃₃ = 1, the data D
_I is a negative number. Negative fixed-point data D _I
will be expressed in two's complement notation. For example, as a second specific example of fixed-point data D _I , DI ₋ ⁼ (FFFF) ₁₆ = (1111 1111 1111 1111) ₂ = (-1) ₁₀ is given. In other words, the binary representation of +1 (0000 0000
0000 0001) In order to take _{the two} 's complement of 2 and make it correspond to -1 in decimal, all the digits need to be inverted and "1" added to the least significant bit. D _I ⁻ =F×16 ³ +F×16 ² +F×16 ¹ +F×16 ⁰ (16
1×2 ¹⁵ +……1×2 ² +1×2 ¹ +1×2 ⁰ (binary) = −1×10 ⁰ (decimal), and D _I ⁻ is − in decimal. Represents 1. In the figure, each register 20, 30, 40, 5
0 each inputs write data signals 201, 301, 401, 501 for 1 byte, and also inputs read/write control signal 80 in common, and decode control signals 202, 302, 402, 502.
are input, and each outputs read data signals 203, 303, 403, and 503 of 1 byte. respective registers 20, 30, 40,
50, the read/write control signal 80 is logic 0 and the respective decode signals 202, 302, 402, 5
When 02 becomes logic 1, each 1-byte write data signal 201, 301, 401, 50
1 is written, and when the read/write control signal 80 becomes logic 1, each read data signal 203, 303, 403, 503 of 1 byte is read out. However, the most significant bit signal DW ₇ of the write data signal 401 as an input to the (A+2) address register 40 is input to one input terminal 601 of the exclusive OR circuit constituting the inverting circuit 60, and the other input terminal 602 is connected to the power supply _Vcc through a resistor 604 and is fixed at logic 1, so it is inverted and appears at the output terminal 603, and this inverted signal 603 is input to the most significant bit terminal 4017 of the A+2 address register 40. In the data conversion circuit of the above embodiment of the present invention, as a first step, the CPU converts the 2-byte fixed-point data D at addresses A+2 and A+3.
It starts with a command to write _I. When this write command is issued, the read/write control signal 80 becomes a write state of logic 0, and
Since the four decoded signals DEC0, DEC1, DEC2, and DEC3 of 2, 302, 402, and 502 have a logic (0, 0, 1, 0) that includes only logic 1,
One byte of write data 401 is written to the A+2 address register 40 as DW ₆ , DW ₅ , DW ₄ , . . . 7 of DW ₀
The bits remain unchanged, and only the most significant bit _DW7 is inverted by the inverting circuit 60 and set. Since the write command is a command to write 2 bytes of data, at the next time, the read/write control signal 8
0 is logic 0 and the four decode signals DEC0,
DEC1, DEC2, and DEC3 become logics (0, 0, 0, 1) including only logic 1, and 1-byte write data 501 is also placed in the A+3 address register 50 as it is. In this way, 2-byte fixed point data D _I =H ₃ H ₂ H ₁ H ₀ is placed in the A+2 address register 40 and the A+3 address register 50. Fixed-point data D _I is D _I ⁺ =
(0001) ₁₆ , the sign bit is inverted, and as is clear from Table 1, it becomes (8001) ₁₆ , and D _I
⁻ = (FFFF) ₁₆ , the sign bit is inverted, and as is clear from Table 1, it is in the form of (7FFF) ₁₆ ,
The numbers are placed in registers 40 and 50. Next, as a second step, the CPU instructs the A address register 20 and the A+1 address register 30 to write predetermined 2-byte data (4600) ₁₆ . Here, (46) ₁₆ is the adjustment value of the exponent part of the floating-point data to move the decimal point position of the fixed-point data to the decimal point position of the mantissa part of the floating-point data, and (00) ₁₆ is the adjustment value of the exponent part of the floating-point data. This is data to be stored in the register corresponding to the part where the data width of the mantissa part is longer than the fixed point data width. The meaning of fixed data (4600) ₁₆ will be explained in detail later. When the above-mentioned write command is issued, the read/write control signal 80 remains in the write state of logic 0, and the 20
The four decoded signals DEC0, DEC1, DEC2, DEC3 of 2,302,402,502 are (1,
0, 0, 0) and (0, 1, 0, 0), and the above 2 bytes of data (4600) 1 byte of data out of ₁₆ (46) ₁₆ is stored in the A address register 20, and 1 byte of data ( 00) Place ₁₆ in the A+1 address register 30. In this way, registers 20, 30,
40 and 50 have fixed point data D _I ⁺ = (+
1) When it is ₁₀ , 4 bytes of data _F ⁺ = (46008001) ₁₆ is placed and the fixed point data is D _I ^- = (-1)
When it is ₁₀ , 4-byte data _F ⁻ = (46007FFF) ₁₆ is set. Here, the meaning of the 2-byte fixed data (4600) ₁₆ will be explained. In this embodiment, one word of the floating point data _DF consists of 4 bytes of 32 bits, and as shown below, the most significant bit _f31 is used as a sign bit to indicate positive or negative, and this and _f30 , _f29 ... The upper 8 bits obtained by adding the 7 bits of _f24 are the exponent part, and the following 3 bytes of 24 bits are the mantissa part.

[Table] That is, when the exponent is n and the mantissa is p, floating point data D _F is expressed as D _F =±p×16 ⁿ with base 16. At this time, the mantissa p satisfies 0.1≦p<1. In other words, since the decimal point of the mantissa is to the left of x ₅ , the mantissa p is x _i
If (i=5, 4...0) is a hexadecimal number, p=x ₅ ×16 ^-1 +x ₄ ×16 ^-2 +x ₃ ×16 ^-3 +...+x ₀ ×
This is because it becomes 16 ^-6 . On the other hand, regarding the exponent part, since the number that can be expressed with a total of 7 bits excluding the sign bit is from 0 to 127, the middle value is 64, and larger numbers are treated as positive exponents, and smaller numbers are treated as positive exponents. is determined to be a negative exponent. _Therefore , when the reference point for the positive/negative of the exponent part of floating point data is (0100 0000), _{the reference point for the positive/negative of the exponent n is (E 1 E 0} ) ₁₆ = (40 ) ₁₆ = (0100 000) ₂ = (64) ₁₀ , so this can be set as n=0 and determined to correspond to 16 ⁰ . Then, for a positive exponent of positive data, (E ₁ E ₀ ) ₁₆ = (0100 0001) ₂ corresponds to 16 ¹ with n = 1, and the maximum exponent is (E ₁ E ₀ ) ₁₆ = (0111 1111) ₂ = (127) ₁₀ , n = 2 ⁶ - 1 = 63, corresponds to 16 ⁶³ . Also, for negative exponents of positive data, n=
Corresponds to 0 (E ₁ E ₀ ) ₁₆ = (0100 0000) ₂ = (64) 1 less than ₁₀ (E ₁ E ₀ ) ₁₆ = (0011 1111) ₂ corresponds to 16 ^-1 as q = -1 , one by one so that n=-2 ⁶ =-64, where the minimum exponent is (E ₁ E ₀ ) ₁₆ = (0000 0000) ₂ , corresponds to 16 ^-64 . Therefore, the index n satisfies -64≦q≦+63. The 2-byte fixed data (46 00) ₁₆ represents (E ₁ E ₀ x ₅ x ₄ ) ₁₆ = (46 00) ₁₆ = (0100 0110 0000 0000) ₂ = (64 + 6 0) ₁₀ , so n =+6. Therefore, in order to convert fixed point data to floating point data, if the data is positive,
The mantissa part of the lower 2-byte floating-point data (x ₃ x ₂ x ₁ x ₀ ) ₁₆ has the same bit configuration as the given 2-byte fixed-point data (H ₃ H ₂ H ₁ H ₀ ) ₁₆ Make it. However, here, the 2-byte length fixed-point data D _I = where the decimal point position is to the right of H ₀
(H ₃ H ₂ H ₁ H ₀ ) 4 where the decimal point position of ₁₆ is to the left of x ₅
Byte length positive floating point data D _F =
(E ₁ E ₀ x ₅ x ₄ x ₃ x ₂ x ₁ x ₀ ) To get the same number as ₁₆ ,
This upper 2 byte length (E ₁ E ₀ x ₅ x ₄ ) ₁₆ (4600) ₁₆
As such, the mantissa (x ₃ x ₂ x ₁ x ₀ ) must be multiplied by 16 ⁺⁶ . For example, when the fixed point data D _I is (+1) ₁₀ (D _I ⁺ = (0001) ₁₆₎ , the floating point data D _F ⁺ representing the same number (+1) ₁₀ is D _F ⁺ = (4600 0001 ) ₁₆ = 16 ⁺⁶ × (0 × 16 ^-1 + 0 × 16 ^-2 + ... + 1 × 16 ^-6 ) = (+1) ₁₀ . However, this floating point data D _F ⁺ is not normalized because the most significant digit x ₅ of the mantissa part is x ₅ =(0) ₁₆ . The normalization of the floating point data D _F ⁺ will be explained with respect to the floating point subtraction circuit 70. The floating point subtraction circuit 70 receives 32-bit A operand input data A = (A ₃₁ , A ₃₀ , ..., A ₀ ) and 32
Bit B operand input data B = (B ₃₁ ,
B ₃₀ , ..., B ₀ ), and input the lower 24 of the A operand.
Binary subtraction (A _x - B _x ) is performed on the mantissa part of bit A _x and the lower 24 bits of B _x in the B operand, and the 4-bit length upper digit of the resulting Q _x corresponding to the mantissa part is ( 0) Calculate using the upper 8 bits A _E of the A operand and the upper 8 bits B _E of the B operand corresponding to the exponent part so that a number that is not ₁₆ will come out, and calculate the correct exponent part Q _E , resulting in a total of 32 bits. A data bus 90 outputs normalized floating point data F.
This is what is output to. As shown, floating point subtraction circuit 70
B operand input data B = (B ₃₁ , B ₃₀ ,...
..., B ₀ ) has fixed data B _I = (0100
0110 0000 0000 1000 0000 0000 0000) ₂ is entered. The fixed data B _I is expressed as B _I =(4600 8000) ₁₆ in hexadecimal notation. Also, the 8-bit output 2 of registers 20, 30, 40, and 50
03, 303, 403, and 503 are connected to the A operand input of the floating point subtraction circuit 70.
The registers 20, 30, 40, and 50 store not the non-normalized floating point data D _F ⁺ itself, but data _F ⁺ =(4600 8001) ₁₆ in which the sign bit of the fixed point data is inverted. Here, read/write control signal 8
By making 0 a logical 1 in the read state,
32-bit data stored in registers 20, 30, 40, and 50 (in this case, _F ⁻ =
(46008001) ₁₆ ) is the A operand, and the fixed 32-bit data B _I = (46008000) ₁₆
Floating-point subtraction is performed with B as the operand. Lower 24 bits of A operand A _x = (008001) ₁₆
and the lower 24 bits of the B operand B _x = (008000) ₁₆
The operation regarding the mantissa part of A _x is the two's complement value of B _x .
_x = (FF7FFF) ₁₆ + (000001) ₁₆ = (FF8000) Since it is done by adding ₁₆ , the result Q _x is Q _x = (008001) ₁₆ + (FF8000) ₁₆ = (000001) ₁₆ = (+1) becomes ₁₀ . If this continues, Q _x = (000001) The most significant digit x ₅ of ₁₆ is (0) ₁₆ , so this digit x ₅ is (0) ₁₆
A number that is not i.e. the least significant digit (1) in this case ₁₆
It is necessary to move the decimal point six digits higher so that . For this purpose, the floating point subtraction circuit 70 calculates the result by using the upper 8 bits of the A operand, A _E = (46) ₁₆ , and the upper 8 bits of the B operand, B _E = (46) ₁₆ , which correspond to the exponent part. The upper 8 bits F _E corresponding to the exponent part of F are set as F _E =(41) ₁₆ , and the entire result F is output as F=(41100000) ₁₆ . This 32-bit output result F = (41100000) ₁₆
The most significant digit is (0) and the _mantissa part F _x =
(100000) has ₁₆ (+1) ₁₀ normalized floating point data. That is, given 16 bits of fixed point data (0001) ₁₆ becomes 32
Normalized floating point data of ₁₆ bits (41100000) is converted correctly. eventually,
This calculation result F is read by the CPU. Also, if the fixed-point data D _I is negative (-1) ₁₀
When D _I ⁻ = (FFFF) ₁₆ , the upper 16 bits of registers 20, 30, 40, and 50 store (4600) ₁₆ , and the lower 16 bits are fixed-point data with sign bit _f15 inverted. The resulting data _F ⁻ = (4600 7FFF) ₁₆ is stored. The contents of the register are input to the 32-bit A operand of the floating point subtraction circuit 70.
_F ⁻ is input, and the B operand input is fixed data B _I = (0100 0110 0000
0000 1000 0000 0000 0000) ₂ = (46008000) ₁₆ is input. Therefore, by setting the read/write control signal 80 to logic 1 in the read state, the 32-bit data _F ⁻ = (4600 7FFF) ₁₆ stored in the registers 20, 30, 40, and 50 and the fixed 32 Floating point subtraction is performed on bit data B _I =(46008000) ₁₆ . The operation between the lower 24 bits A _x = (007FFF) ₁₆ corresponding to the mantissa of the A operand and the lower 24 bits B _x = (008000) ₁₆ corresponding to the mantissa of the B operand is as follows:
A _x to B _x two's complement value _x = (FF7FFF) ₁₆ +
(000001) ₁₆ = (FF8000) This is done by adding ₁₆ , so the result is _{Q x} = (007FFF) ₁₆ + (FF8000) ₁₆ = (FFFFFF) ₁₆ = (-1) ₁₀ . At the same time, the floating point subtraction circuit 70 extracts the upper 8 _bits of the A operand corresponding to the exponent part.
= (46) ₁₆ and the upper 8 bits of the B operand B _E =
(46) ₁₆ , the upper 8 bits F _E corresponding to the exponent part of the result F are set as F _E = (C1) ₁₆ = (1100 0001) ₂ , and the lower 24 bits corresponding to the mantissa part of the result F F
Set _x to F _x = (100000) ₁₆ = (0001 0000 0000 0000 0000 0000) ₂ , and output floating point data F = (C1100000) ₁₆ normalized as a whole. The exponent part of the result F is F _E = (1100
0001) ₂ , so the most significant bit is 1. This shows that F is a negative number, n=
(000001) ₂ = (+1) Since it is ₁₀ , this exponent part F _E
represents −16 ⁺¹ . On the other hand, the mantissa part of the normalized floating point data F _x =
(100000) ₁₆ represents (+0.1) ₁₀ , so the output F=0.1×16 ¹ . That is, 16-bit negative fixed-point data (FFFF) ₁₆ is correctly converted to 32-bit normalized floating-point data F=(C1100000) ₁₆ . Ultimately, the result of this calculation can be read by the CPU. As described in detail above, if the data conversion circuit according to the present invention is used, one piece of hardware can convert fixed-point data to floating-point data without using software to determine whether the fixed-point data is positive or negative. Program processing can be performed using only software instructions. Therefore, the present invention contributes to reducing software and increasing the speed of conversion from fixed-point data to floating-point data.

[Brief explanation of the drawing]

The figure is a circuit diagram of an embodiment of a data conversion circuit according to the present invention. 10...input data bus, 20, 30, 40,
50...Register, 60...Inverting circuit, 70...
Floating point subtraction circuit, 80... Read/write control signal, 90... Output database, 201, 30
1,401,501...Write data signal, 2
02, 302, 402, 502...Decode signal, 203, 303, 403, 503...Read data signal.

Claims (1)

[Scope of Claims] 1. A first register section connected to an input data bus and having a data width corresponding to the mantissa part of floating-point data; and a fixed-point register section of the data sent from the data bus to the first register section. an inversion circuit that inverts only the bit corresponding to the sign bit of the data;
a second register section that is connected to the input data bus and stores data corresponding to the exponent part of the floating point data; and a floating point subtraction circuit that inputs all outputs of the first and second register sections as an A operand. The fixed point data whose sign bit has been inverted by the inversion circuit is placed in the first register section, and the decimal point position of the fixed point data is set as the decimal point of the mantissa part of the floating point data in the second register section. As the B operand of the floating point subtraction circuit, only the bit corresponding to the sign bit of the fixed point data is logic 1, and all the bits corresponding to the mantissa of the other floating point data are input. The bits corresponding to the exponent part of the floating point data set to logic 0 are fixedly input with the same data as the adjustment data added to the second register section, and the A operand and B operand
A data conversion circuit that converts fixed-point data to floating-point data by outputting floating-point data normalized by floating-point subtraction of operands to an output data bus. 2. The conversion from fixed-point data to floating-point data according to claim 1, in which logic 0 is placed in the upper part of the first register part other than the register part in which fixed-point data is stored. Data conversion circuit. 3 Move the decimal point to the right of the least significant bit of 2-byte fixed-point data to the left of the most significant bit of the mantissa of floating-point data consisting of a 1-byte exponent and 3-byte mantissa. In case, the sign of the exponent part of floating point data is 10
2. The conversion circuit from decimal point data to floating point data according to claim 1, wherein when the number is 64 in hexadecimal, a hexadecimal number (46) is input to the second register section.