JPS6252466B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor integrated circuit including a power PNP type transistor.

"Prior Art" As a semiconductor integrated circuit including a power NPN type transistor, for example, the one shown in FIG. 1 is known. The drawing shows a small signal transistor and a resistor in addition to the power NPN transistor. First, let me explain about power NPN transistors.
1 is a collector low resistance region, 2 is a collector high resistance region, 5 is an N ^- type region similar to region 2, 6a is a base region, 7a is an emitter region, 10a, 10b,
10c is an electrode. To explain the small signal transistor, 4a is the collector low resistance region;
5 is a collector high resistance region, 7b is a collector extraction region, 8a is a base region, 9 is an emitter region, and 10d, 10e, and 10f are electrodes. Regarding the resistance, 4b is a parasitic leakage current prevention region, 8b is a resistance region, and 10g and 10h are electrodes. 3 and 6b are isolation regions for making the small signal transistor and the resistor electrically independent. 1
0' is a SiO ₂ film.

However, when it is desired to integrate a power PNP type transistor and other circuit elements, simply reversing the conductivity type of the above structure makes it difficult to create other electrically independent circuit elements. Also,
Regions 2 and 5 are usually formed by epitaxial growth, and it is inevitable that there will be many crystal defects on the surface side of region 5. This leads to a decrease in the manufacturing yield of semiconductor integrated circuits due to insufficient withstand voltage of the power NPN transistor.
For this reason, a structure in which the emitter region and base region of the power NPN transistor are formed in region 2 has also been considered. However, with this structure, the current amplification factor becomes too high, resulting in insufficient breakdown voltage of the power NPN transistor, making it difficult to obtain normally required characteristics.

``Object of the Invention'' The present invention is intended to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor integrated circuit including a power PNP type transistor with good electrical characteristics.

"Example" The present invention will be explained below based on the drawings.

FIGS. 2 to 10 are for explaining a semiconductor integrated circuit according to an embodiment of the present invention along the manufacturing process.

First, as shown in FIG. 2, a P ^- type silicon region 12 is formed on a P ⁺ type silicon region 11 by epitaxial growth.

Next, as shown in FIG. 3, mutually independent N-type diffusion regions 13a and 13b are simultaneously formed in region 12.

Next, as shown in FIG. 4, a P-type diffusion region 15a annularly surrounding region 13b is formed in region 12, and a P-type diffusion region 15b is formed in region 13b at the same time.

Next, as shown in Figure 5, mutually independent N ⁺
Shape diffusion regions 16a and 16b are simultaneously formed in region 15b.

Next, as shown in FIG. 6, N ⁻
A shaped silicon region 17 is formed by epitaxial growth.

Next, as shown in FIG. 7, the P ⁺ type diffusion region 18
A18b and a18c are formed in the region 17 at the same time.
At this time, region 18a is connected to region 13a at least in the final stage. The region 18b is connected to the region 15a at least in the final stage and annularly surrounds a part of the region 17 having the region 13b below it. Region 18c is connected to region 15b at least in the final stage, and region 16 is formed below it.
A part of region 17 with a and region 16 below it
A part of the region 17 having b is each annularly surrounded.

Next, as shown in ^FIG .
a and 19b are formed in the region 17 at the same time. Area 1
9a has its bottom connected to region 13a at least in the final stage, and its sides connected to region 18a so as to annularly surround region 18a. Area 19
b is connected to region 16a at least in the final stage.

Next, as shown in FIG.
P-type diffusion regions 2 in the upper regions 17 of 6b, respectively.
0a and 20b, and then N ⁺ in the region 20a.
A shaped diffusion region 21 is formed.

Finally, as shown in FIG.
Form 2i. 23 is a SiO ₂ film.

In FIG. 10, the parts of the power PNP transistor are explained: 11 is a collector resistance region, 12 is a collector high resistance region, 17 around 13a and 19a is a base region, 19a is a base extraction region, and 18a is an emitter region. , 22a,
22b and 22c are collector, base, and emitter electrodes.

In FIG. 10, one NPN transistor and one resistor are also formed. Regarding this NPN type transistor, 16a is a collector low resistance region, 17 above 16a is a collector high resistance region, 1
9b is a collector drawer area, 20a is a base area, 21 is an emitter area, 22d, 22e, 22
f is the collector, base, and emitter electrodes. Regarding the resistor, 16b is a parasitic leakage current prevention region, 20b is a resistance region, and 22g and 22h are electrodes for resistance.

Regions 18b and 15a are isolation regions for making a part of region 17 surrounded by these regions electrically independent from the base region of the power PNP transistor. Further, the regions 18c and 15b, together with the presence of the region 13b, function as isolation regions for making the NPN transistor and the resistor, which are formed in a part of the region 17 surrounded by the region 18c, electrically independent. The regions 18c and 15b are usually
It is grounded by electrode 22i.

Note that there is a region 1 between the region 18a and the region 13a, and between the region 18a and the region 19a, respectively.
7 may remain. area 18b,
15a may be formed so as to surround the formation region of the power PNP type transistor. That is, even if the region 19a is formed to surround the region 19a in an annular shape, it functions in the same way as a region separating from the base region of the power PNP transistor. Furthermore, when used as a circuit in which the PN junction between 12 and region 17 is reverse biased, a part of region 17 surrounded by regions 18b and 15a is electrically independent, so regions 13b, 15b, 18c The formation of is not necessary. That is, two (in fact, many) parts of the region 17 surrounded by the regions 18b and 15a are formed,
It is sufficient to form an NPN transistor and a resistor for each.

"Effects of the Invention" According to the present invention, a semiconductor integrated circuit including a power PNP transistor can be realized, and, for example, a low-loss voltage regulator using a PNP transistor as a main switch can be constructed. Furthermore, since the main part of the active region of the power PNP type transistor is formed in the internal region with few crystal defects, insufficient breakdown voltage and the like are avoided, and the manufacturing yield is greatly improved. In addition, in this power PNP type transistor, the impurity concentration in the base region has a distribution with a peak slightly away from the emitter region, and the emitter injection efficiency is high, so even with a relatively wide base width, a sufficiently large current can be generated. Amplification factor can be obtained. Therefore, it is convenient when it is desired to obtain a large current amplification factor or when it is desired to increase the breakdown strength by widening the base width.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a conventional semiconductor integrated circuit. FIGS. 2 to 10 are cross-sectional views showing semiconductor integrated circuits according to embodiments of the present invention in the order of manufacturing steps. In FIG. 10, 11...first semiconductor region,
12...second semiconductor region, 17...third semiconductor region, 13a...fourth semiconductor region, 19a...fifth semiconductor region
Semiconductor region, 18a...Sixth semiconductor region, 18b
and 15a... seventh semiconductor region.

Claims (1)

[Claims] 1. A first semiconductor region of P type and low resistance, a second semiconductor region of P type and high resistance adjacent to the first semiconductor region, and a second semiconductor region of N type adjacent to the second semiconductor region. a high-resistance third semiconductor region; an N-type fourth semiconductor region formed as a buried layer spanning from the second semiconductor region to the third semiconductor region; and a fourth semiconductor region extending from the surface of the third semiconductor region to the fourth semiconductor region. an N-type low resistance fifth semiconductor region formed to annularly surround a part of the third semiconductor region; and the third semiconductor region surrounded by the fifth semiconductor region.
In a part of the semiconductor region, the third semiconductor region extends from the surface of the third semiconductor region to the fourth semiconductor region in a remaining or non-remaining state between the fourth semiconductor region and the fifth semiconductor region. a P-type sixth semiconductor region; and a portion of the third semiconductor region that reaches the second semiconductor region from the surface of the third semiconductor region and is not surrounded by the fifth semiconductor region as the fourth semiconductor region. a P-type seventh semiconductor region formed to be electrically isolated from the region and the fifth semiconductor region, and a part of the third semiconductor region electrically isolated by the seventh semiconductor region. a collector electrode of a PNP transistor connected to the first semiconductor region; a base electrode of the PNP transistor connected to the fifth semiconductor region; and a semiconductor circuit element formed using the sixth semiconductor. An emitter electrode of the PNP transistor connected to a semiconductor integrated circuit.