JPS6252473B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit that integrates logic devices that can achieve low power consumption and high integration.

Conventional low-power logic devices are generally complementary ICs, that is, CMOS-structured ICs in which a P-channel MOS transistor and an N-channel MOS transistor are connected in series between a power supply VDD and GND. This CMOSIC is widely used in watches, calculators, memory, etc. due to its low power performance. Figure 1 shows this CMOS inverter. 1 indicates a P-channel transistor, and 2 indicates an N-channel transistor. Also, FIG. 2 shows the structure of this CMOS. Create a P ^- well 4 in the N ^- substrate 3. After that, N ⁺ becomes the source and drain on the N channel side.
Diffusion layers 5 and 6 or P ⁺ diffusion layers 7 and 8 on the P side are formed, and gate films 9 and 10 and gate electrodes 11 and 12 are formed. Furthermore, the gate input VG and drain output VD correspond to those shown in FIG. As can be seen from this structure, two gate electrodes and two drain diffusion layers are required to form one gate stage. Therefore, it has two major drawbacks: low integration and low speed due to large parasitic capacitance. Therefore, for example, if we take a CMOS memory, its standby power is on the order of μW, and by backing up the battery, the memory can be made non-volatile and used as a non-volatile RAM. Making this data non-volatile is a major factor in replacing conventional core memory in order to make devices more compact. On the other hand, unless the memory capacity and speed can be increased, it will not be possible to apply it to mainframe memory, which is mainly used in computers.
Therefore, this CMOS memory, which has extremely low standby power and low operating power, has a low degree of integration and cannot be increased in capacity as described above, and is also slow in speed, resulting in a narrow range of applications.

Therefore, an object of the present invention is to provide a logic device that uses low power like CMOSIC and has higher integration and higher speed than CMOS.

FIG. 3 shows a structure as a specific example of the present invention. A P ^-- epi layer 22 is formed on an N ⁺ substrate 21 . After that, the N ^- part 24 for the normal P channel transistor (this is used as an interface part, etc., but it can be removed if unnecessary) and the P ^- part 2
3. Form a diffusion layer. The P ^- portion, which becomes the N-channel substrate, is biased to the ground potential GND by the P ⁺ diffusion 25. Further, the entire substrate is biased to VDD which is a positive potential due to the N ⁺ diffusion 33. N ⁺ diffusion 2 that becomes the source and drain on the N channel side
9, 30 and P ⁺ diffusion layer 31 on the P channel side,
32, gate oxide films 35 and 36, and gate electrode 3
8 and 39 form normal MOS transistors. The device of the present invention is composed of an N ⁺ diffusion layer 26 formed at the same time as the N ⁺ diffusion layers 28, 29, 30, and 33 forming normal sources and drains, and an N ⁺ diffusion layer 27 formed deeper and separately. The gate film 34 and the gate electrode 37 are covered with normal N.
Control the conductive layer of the channel. Also deep
The N ⁺ diffusion layer 27 and the substrate 21 operate as a load portion of this N channel transistor via the P ^-- epi layer 22.

FIG. 4 is an enlarged view of this part, and the symbols are the same as in FIG. 3. The shaded area 43 is a depletion layer extending from the N ⁺ substrate 21 to the P ⁻ epi layer 22 . If a positive potential is applied to the gate electrode 37 of the N-channel transistor, an inversion layer 45 is formed directly under the gate and it is turned on, and the potential VDN of the drain N ⁺ diffusion layer 26 is the source of the N ⁺ diffusion layer 2.
It has the same potential as GND of 8. At this time, the N ⁺ diffusion layer is at the same potential as the P ^-- layer and the P ^- layer that serve as the substrate, so the depletion layer 42
does not spread that much and only depends on the diffusion potential. However, since the P ^-- layer has a particularly low concentration, the depletion layer is slightly
It spreads more easily than in the P ^- layer. The spread length _D of this depletion layer is expressed as (1) _D = √2( _D + _DN )・_B. Here, εsi is the dielectric constant V of silicon
_D is the diffusion potential, V _DN is the potential between N ⁺ and the P ^- layer and the P ^-- layer, g is the electric charge, and N _B is the concentration of the P ^- layer and the P ^-- layer. If the N channel gate becomes GND,
When the channel is turned off, the deep N ⁺ diffusion layer is pulled toward the N ⁺ substrate 21 side due to slight leakage between the depletion layers 42 and 43 and approaches the V _DD potential. Then, according to equation (1), when V _D increases, the depletion layer length _D
increases, and as shown by the broken line 44, the drain contacts the depletion layer 43 and is strongly pulled toward V _DD by positive feedback. The expansion and contraction of this depletion layer due to the drain potential acts as a load for this N-channel transistor. Since the P ^-- epilayer 22 has a very low concentration, a slight change in the drain potential V _DN causes a large change in the spread of the depletion layer, as can be seen from equation (1).
This is the reason why a P ^-- layer is used. If the diffusion depth and concentration can be sufficiently controlled, the structure shown in Figure 2, in which a P ^- well is diffused into an N ^- substrate like a normal CMOSIC, can be used as a deep layer. The same principle can be applied if only the drain diffusion layer is provided. Moreover, if the slight leakage is ignored even if only a normal N ⁺ diffusion layer is used, the structure shown in FIG. 2 without the P channel transistor is also the same. At this time, the diffusion layer of the P ^- well needs to be shallow.

FIG. 5 shows the load current characteristics of FIG. 4. If the drain potential V _DN is the same potential as the substrate, the depletion layer is connected, but the current value is naturally zero. Also, the time depletion layer where _VDN is at the same potential as the substrate's GND is far away, and the current IDN is very small. As V _DN increases little by little, the depletion layer approaches and carriers begin to diffuse through it, causing the current to rise exponentially with respect to V _DN . In this way, a negative resistance characteristic as shown in the figure is obtained. a has a high substrate concentration,
It gets lower as you go to c. Also drain N ⁺ layer and substrate
This property also changes depending on the spacing of the N ⁺ layers. The characteristics of the inverter shown in Figure 4 require V _DN to be stabilized.
When is 0, it is better to have slightly more IDNs than channel leaks. Also, if the operating current is not required to be extremely low, V
When _DN is 0, if the depletion layer is kept in some contact, the load current can be quite large, which is effective in increasing the speed.

FIG. 6 shows another example of application of the present invention, in which the drain depletion layer is brought into contact with the V _DD side in a planar manner. A P ^- well 62 is formed in an N ^- substrate 61. After that, N ⁺ diffusion layers 63, 64, and 65 for source/drain and V _DD bias are formed.
Thereafter, gate films 59 and 66 and electrodes 60 and 67 are formed. The input of this inverter is electrode 67. If the N ⁺ diffusion layer 64 of the drain is at the GND potential, the depletion layer is shrunk as shown in 69 and is separated from the depletion layer 68 of the N ⁺ diffusion layer 63 . If V _DN is V
When approaching _{the DD} potential, the drain depletion layer becomes like 70, contacts the depletion layer 68, and operates in the same manner as shown in FIG. At this time, the gate electrode 60 on the contact point of this depletion layer becomes GND, which plays the role of pushing the drain and V _DD bias depletion layer downward from the surface and ensuring control of the depletion layer.
It is not necessary if the characteristics shown in the figure can be achieved. Furthermore, if the portion in contact with the depletion layer is formed with an extremely low concentration as shown in FIG. 4, the operation becomes more stable. Naturally, even if the N type in the above example is replaced with a P type, and the P type is replaced with an N type semiconductor layer, the same operation will occur.

FIG. 7 shows a static random access memory (RAM) cell constructed using the logic device of the present invention. transistor 7
3 and 74 are N-channel active elements, and 71 and 72 are loads for controlling the depletion layer according to the present invention. 71 and 73, 72 and 74 constitute an inverter. Transistors 75 and 76 are transfer gates switched by the address line ADDRESS, and control data input/output to/from BIT.

FIG. 8 shows a diagram configuring a two transistor/cell static memory using a depletion layer controlled load. Conventional statics always had six elements, but the same characteristics can be obtained with one-third of them. The fact that there are two stable potentials (d) at the same current value in FIG. 5 is utilized. The transfer gate 81 switched by the ADDRESS line has a slight leakage between it and the substrate (GND potential). If this were a constant current, it would be a memory cell that statically, and with a very small current, stores whether it is a low potential or a high potential. This is an unprecedented static memory. In other words, a large number of cells can be accommodated on one chip, and the high degree of integration, which has been a problem with conventional static memories, can be easily achieved. Although the gate and source of transistor 82 are at the same potential, a small current (subthreshold current) flows through the surface to maintain the contents of the cell. Further, this current does not need to be a constant current, and a slight leak such as punch-through or juncture may be used, or a resistor such as polysilicon may be used.

FIG. 9 is an example in which the memory cell shown in FIG. 7 is patterned. polysilicon layers 102, 94,
95 is a diffusion region 91, 92, 93 surrounded by solid lines.
Configure the gate on top of. A wiring 104,1
05, 106, 107 are x marks 96, 97, 10
0, 101 and diffusion regions 91, 92, 93, and ×
Contact is made to the polysilicon at marks 98 and 99. The diffusion region 91 is a source 92, 9 of GND potential.
3 is a drain. The area of this cell is 42μm×
28μm x 60μm, NMOS 960μm x 40μm
This is a significant decrease compared to the previous year. 4th with this pattern
To describe an example of a prototype memory fabricated using the structure shown in the figure, the concentration of the P ^-- layer is approximately 5 x 10 ¹⁴ /cm ² , the concentration of the P ⁺ layer and
P ^-- layer thickness 11μm, N ⁺ depth 3μm, P ^- depth 4μm
It is formed by ion implantation. At this time, the standby power per cell is approximately 1 μW, and the operating speed for address access is approximately 150 msec. This is slightly less power than traditional CMOS memory, but nearly three times faster.

FIG. 10 is an example in which the cells of FIG. 8 are patterned. The gate line 113 and the source diffusion layer 110 are
It has the same potential as GND. A memory section with depletion layer control exists directly below the drain 111. gate line 1
14 controls the transfer gate. 115
Al wiring 11 to input and output cell data
Contact BIT made in 6. The cell size is only 12 μm x 21 μm, which is only 5% of a conventional CMOS cell. Conversely, it is possible to achieve 20 times more memory capacity. This device can be manufactured similarly to the pattern of FIG. 9 described above. Furthermore, when transferring this cell, the impedance of the cell is lowered by biasing the gate line 113 to the + side, and the read access speed gradually increases.

The present invention realizes the role of a load at low power and high speed by controlling the depletion layer, and as described above, the degree of integration is significantly improved while maintaining the low power operation of CMOS. Also drain output,
Since the device area for both gate input and CMOS is less than half that of CMOS, combined with the lower substrate concentration, the parasitic capacitance is reduced to one-third, resulting in a noticeable increase in speed. Therefore, the logic device according to the present invention requires lower operating power than conventional devices.
It is superior in all respects, such as high integration and high speed, and is particularly effective in achieving large capacity and high speed, as can be seen by comparing memory as before.

[Brief explanation of the drawing]

Figure 1 shows a conventional CMOS inverter, and Figure 2 shows its structure. FIG. 3 shows an example of the structure of a logical device according to the present invention. FIG. 4 is a partial diagram thereof, FIG. 5 is a load characteristic of the present invention, and FIG. 6 is another example of the present invention. 7 and 8 show a memory cell using the element of the present invention. Figures 9 and 10 are the 8th
The pattern shown in FIG. 9 is shown. 42, 43, 44, 68, 69, 70... depletion layer, 71, 72, 80... depletion layer control load.

Claims (1)

[Claims] 1. A semiconductor integrated circuit comprising a substrate of a first conductivity type, a first region of a second conductivity type formed on the substrate, and a MOS transistor formed in the first region. In the MOS transistor, the MOS transistor includes a gate electrode, a drain region, and a source region to which a first potential is applied, and a first depletion layer is formed near a junction region between the substrate and the first region. A second depletion layer is formed near the drain region and expands as the potential of the drain region changes from the first potential to the second potential, and a second depletion layer is formed in the vicinity of the drain region. A semiconductor integrated circuit characterized in that the first region is a load resistance whose current value changes according to the spread of the second depletion layer. 2 the second region formed near the drain region;
2. The semiconductor integrated circuit according to claim 1, wherein the depletion layer expands in response to changes in the potential of the drain region and comes into contact with the first depletion layer.