JPS6252476B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor rectifier, and particularly to a method for manufacturing a high voltage semiconductor rectifier.

There are many methods for manufacturing semiconductor rectifying elements, such as silicon chips (hereinafter referred to as chips), but one method for forming a PN junction by diffusion is to use an N-type (or P-type) silicon wafer 1 as shown in FIG. 1 or 2. Generally, a P-type (or N-type) impurity is thermally diffused to form a PN junction 2, and then the bonding surface is coated with silicone rubber, SiO ₂ 3, etc. to form a chip.

In particular, in the case of so-called ultra-high voltage rectifiers of 5 KV or higher, it is common to have a so-called composite chip structure in which a plurality of the above-mentioned single chips are stacked in series as shown in FIG.

In the case of this type of conventional type, it is necessary to overlap and connect individual chips using a mount, etc., and stacking multiple chips causes problems such as positional deviation and mounting accuracy, and the number of chips to be stacked is also high. There were also limits to the so-called pressure resistance.

SUMMARY OF THE INVENTION The object of the present invention is to eliminate these conventional drawbacks and provide a method for manufacturing a high-voltage semiconductor rectifying element having ultra-high voltage by using ultra-high voltage pellets as single pellets instead of stacking individual pellets.

An embodiment of the present invention will be explained in the order of manufacturing steps with reference to the drawings. In FIG. 4, P type impurities are selectively penetrated and diffused alternately in a band shape in the lateral direction of an N type silicon wafer 1 to form P ⁺ type regions. 6 to form an arbitrary number of consecutive P ⁺ -N-P ⁺ -N... junctions. Next, holes 7 passing through the wafer 1 in the thickness direction are formed at the P ⁺ N junction so as to be arranged at predetermined intervals. For example, photoetching technology can be used for this purpose, and the thickness of the wafer 1 can be
In the case of 30 μm, through holes with an average diameter of about 60 μm can be provided. Of course, laser or electron beam technology may also be used. Through hole 7
is provided at every other P ⁺ N junction, and the
Contact windows 8, 8' are provided in the SiO ₂ film 3 at the NP ⁺ junction or at the wafer edge (FIG. 4a). Next, the side surface of the through hole 7 is coated with glass or embedded with glass. In other words, polysiloxane (liquid silicon compound) is applied to the relevant area and heat treated.
Heat treatment may be performed by forming a SiO ₂ film or applying powdered glass with good surface stability and high insulation effect. The contact windows 8, 8' may be provided at this stage. A conductive material such as aluminum is deposited on the contact windows 8, 8' to form a contact electrode 9' having a bonding pad and a contact electrode 9 for shorting the NP ⁺ junction (FIG. 4b). Next, the wafer is divided into chips 10 having a multilayer PN junction structure. The cathode lead wire 11 and the anode lead wire 12 are bonded (FIG. 4c). Finally, a rectifying element is fabricated by applying coding with a coating material such as silicone resin, and attaching a cathode electrode and an anode electrode as necessary, but these are not shown in the drawings as they are not directly related to the gist of the invention.

As explained in detail above, the method for manufacturing the semiconductor rectifier of the present invention uses photoresist technology and diffusion technology, so it can be manufactured with high precision.
Since there is no need to stack chips like in the past, a larger number of PN junctions can be connected in series than in the past, making it possible to achieve higher voltage resistance, and the PN junction surface is protected with an insulating coating such as glass or SiO ₂ film. Because of this, it operates extremely stably. in this way,
This has a great effect on increasing the voltage resistance and stabilizing the rectifying element.

[Brief explanation of the drawing]

1 and 2 are schematic cross-sectional views showing a conventional semiconductor rectifier chip, FIG. 3 is a side view of a composite chip, and FIG. 4 is a diagram for explaining the present invention according to the manufacturing process. In the figures, Figures a and b are cross-sectional perspective views showing a part of the wafer, and Figure c is a perspective view of an individual chip. 1...N-type silicon wafer, 2...PN junction, 3
...SiO ₂ , 4... Anode extraction electrode, 5... Cathode electrode, 6... P ⁺ type region, 7... Through hole, 8,
8'...Contact window, 9,9'...Contact electrode,
10... Chip, 11... Cathode lead wire, 12
...Anode lead wire.

Claims (1)

[Claims] 1. A step of selectively diffusing and forming a plurality of band-shaped regions of the other conductivity type that penetrate between one main surface and the other main surface of the semiconductor substrate of one conductivity type and are arranged parallel to each other on the main surface; A plurality of substrates comprising the substrate and regions of other conductivity type and covered with a silicon oxide film.
forming holes penetrating between the main surfaces through the silicon oxide film in a plurality of predetermined regions included in every other PN junction surface and having predetermined intervals on the main surface; A step of applying glass to the side surface of the through hole or filling the through hole with glass, and a PN without the through hole.
a step of depositing a conductive film on a plurality of predetermined regions having predetermined intervals on the main surface including the ends of the bonding surfaces; and dividing the through hole in a direction intersecting the plurality of PN bonding surfaces. A method for manufacturing a semiconductor rectifying element, comprising the step of cutting a substrate into rod shapes.