JPS6252874B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is an image display device that can reduce and display one screen of image data stored in a frame memory to 1/2 ^N in real time without losing the information of the original image. Regarding.

In recent years, calculators have been used to create various forms (text, tables,
A system has been announced for creating documents (described using pictorial images such as figures), but for example, if we consider outputting an A4-sized form, the resolution of A4 size is approximately 7 to 8 dots/mm. 2500
It becomes an image of ×3500 dots. This entire image of about 2500 x 3500 dots is displayed on a monitor display in order to see how it is finished, but the standard monitor display is 512 x 512 dots, and high resolution Even things
Since the maximum resolution is 1024 x 1024, there was a drawback that you could not view the entire A4 size image you created at once. Therefore, conventionally, in image display devices that have a frame memory with a capacity larger than the number of picture elements that can be displayed on one screen of a display monitor, the following method has been used to monitor the entire contents of the frame memory. . The first method is to input the image in the frame memory to an information processing device such as a computer, perform calculations within the information processing device to reduce the size, and output the result to the frame memory for display. The drawback is that it takes a long time to perform calculations within the processing device and transfer the image data. The second method is a method called scrolling, in which a reading start address of the frame memory is given, and from this starting point address, data of a size that can be displayed on one screen of the display monitor is read out and displayed. According to
One screen at any position within the frame memory can be freely monitored.

Furthermore, the third method is to divide the frame memory in advance into the size of one screen that can be displayed on the display monitor and set the screen position.
This is a method of displaying a specified screen on a frame memory on a display monitor by specifying a screen position to be monitored. This method is a special case of the second method (scrolling), and is a case where the reading start address of the frame memory is fixed for each screen size that can be displayed on one screen of the display monitor. However, according to the second and third methods, it is possible to monitor the entire contents of the frame memory by changing the reading start address of the frame memory and displaying it multiple times; The disadvantage was that it was not possible to monitor the entire contents of the system. Furthermore, it is also possible to generate discrete addresses when reading and displaying the contents of the frame memory, and to reduce the size by thinning out and reading the frame memory, but with this method, the information of the original image is lost, For example, a defect occurs in that a line of one pixel is omitted.

The purpose of this invention is to provide an image display that displays one screen of image data stored in a frame memory in real time by reducing it to 1/ ^2N vertically and horizontally so as not to lose the information of the original image. The goal is to provide equipment.

According to the present invention, there is provided a frame memory means having ^2N memory blocks and sequentially distributing and storing original image data constituting one screen in each block in units of scanning lines, and a frame memory means having 2N memory blocks in each block, which sequentially distributes and stores original image data constituting one screen, and ^2N memory blocks of the frame memory means. A readout means for simultaneously reading out ^2N sets of continuous picture element data whose horizontal coordinate positions on the ^2N scanning lines correspond to each other, and ^2N sets of consecutive picture elements simultaneously read out from the frame memory means. A calculation means for converting the data into continuous pixel data on a single scanning line that is horizontally reduced to 1/2 ^N without losing the information of the original image data, and picture elements output from the calculation means. It includes a display control means for converting data into a video signal for displaying the data on a display means described later, and a display means for displaying the output video signal of the display control means, and displays one screen of image data stored in a frame memory means. 1/2 ^N without losing the information of the original image in real time
An image display device capable of displaying images in reduced size is obtained.

Next, the present invention will be explained with reference to the drawings. In the following explanation, unless otherwise specified, memory block 2 of 1024 (horizontal) x 512 (vertical) pixels will be used.
When displaying the entire image stored in a frame memory of 1024 (horizontal) x 1024 (vertical) picture elements on a display monitor whose display screen size is 512 (horizontal) x 512 (vertical) picture elements. , the depth of 1 pixel is 1
The case of bit (binary) will be explained as an example. Furthermore, it is assumed that the display is displayed on the display monitor using an interlaced method.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, reference numeral 1 denotes a read/write control circuit that controls writing and reading of data to and from the frame memory 2. Frame memory 2
It has a capacity of 1024 (horizontal) x 1024 (vertical) and consists of 1024 (horizontal) x 512 (vertical) memory blocks 20 and 21 that can be read simultaneously, and each memory block consists of 8 consecutive memory blocks on one horizontal line. It is configured such that pixel data of 100 pixels can be read out at once.

Horizontal 2 read from this frame memory 2
The 2×8 image data in a line is input to the arithmetic circuit 3, where calculations (described later) are performed without losing the original image information, and the data is converted into four consecutive picture element data on a horizontal line. Output. The output picture element data is input to the display control circuit 4, a synchronizing signal is added thereto, and output to the display monitor 5 for display. The above is an overview of the operation of the present invention. Next, details of each circuit will be explained.

The read/write control circuit 1 controls writing and reading data to and from the frame memory 2, as described above. For writing, 1024 (horizontal)
×1024 (vertical) original image horizontally 1 line [1024
(horizontal) x 1 (vertical)], even lines are distributed and stored in the memory block 20 and odd lines are stored in the memory block 21 as 1024 (horizontal) x 512 (vertical) images, respectively. For reading, memory blocks 20 and 21
Interlace scanning is performed on both of the images at the same time, and readout control is performed to interlace and read out one screen of images from each memory block at 1024 (horizontal) x 256 (vertical) x 2 (times). .

As mentioned above, frame memory 2 is 1024
It is composed of two memory blocks 20 and 21 that store (horizontal)×512 (vertical) picture elements. FIG. 2 is a block diagram showing the detailed structure of memory block 20. In the figure, 200-4 to 200-
6, 202-4 to 202-6 are omitted.
As shown in the figure, the memory block 20 has eight sub-memory blocks 200-1 to 200-8 in order to be able to read data of eight pixels at the same time, and one of the sub-memory blocks has 128 pixels.
This is a memory that stores (horizontal) x 512 (vertical) picture elements. Memory block Y (vertical) address 9 bits and
(Horizontal) Of the 10 bits of the address, 7 bits excluding 3 bits from the LSB side are commonly input to all submemory blocks 200-1 to 200-8. Additionally, the 3 LSB side bits of the X address are input to the decoder 201, and its decode output D _1
-D8 are input to sub memory blocks 200-1 to 200-8 only during a write operation and serve as write enable signals. Sub memory block 20
Output data 0-1 to 200-8 are input to registers 202-1 to 202-8, respectively, and accumulated by read data strobe RST.

Memory block 21 is also exactly the same as memory block 20. As mentioned before, when writing to the memory blocks 20 and 21 configured in this way, pixel data on even lines (that is, even fields) is sent to memory block 20.
In addition, the memory block 21 stores picture element data on the parsitivity line (that is, the parsitivity field). Therefore, if you set the X and Y addresses of the original image as shown in Figure 3, it will be 1024 (horizontal) x 1024.
(vertical) horizontal lines Y ₀ , Y ₂ , Y ₄ ,...
..., Y ₁₀₂₂ is transferred to the memory block 20 as an even field Y ₁ , Y ₃ , Y ₅ , ...,
The picture element data on _Y1023 is stored in the memory block 21 as a parsial field. Further, to the sub-memory blocks 200-1 to 200-8, for example, if we consider on the horizontal line _Y0 , picture elements ( _X0 ,
Y ₀ ) is sent to submemory block 200-1, (X ₁ ,
Y ₀ ) goes to 200-2, (X ₂ , Y ₀ ) goes to 200-3...
...(X ₇ , Y ₀ ) is sequentially stored in 200-8, and from the picture element (X ₈ , Y ₀ ), it is also stored in sub memory block 20.
It returns to 0-1 and is repeatedly accumulated 8 pixels at a time. The image data accumulated in the above manner is
By simultaneously reading the two memory blocks 20 and 21 and the eight sub-memory blocks therein, a horizontal line Y ₀ as shown in FIG. 3 is output from the frame memory 2 in one read cycle. The continuous eight picture element data groups BE ₀ and B ₀ on Y ₁ and Y 1 can be read out simultaneously, and this is sequentially repeated in units of 8×2 groups.

The reason why 8 picture elements are read out simultaneously on one horizontal line is that in order to display image data of 512 x 512 picture elements on a display monitor, a basic block with a period of approximately 60 ns/pixel is generally required.

In addition, the access time of IC memories currently on the market is as fast as 50 to 60 ns, but they are very expensive and generally have access times of 20 to 60 ns.
A length of about 250 ns is used. Therefore, in order to display the image on the display in real time, it is necessary to read out four or more picture elements at once. In this example
The example shows a case where the size is reduced to 1/2, so
Generally, 8 or more picture elements must be read out. Therefore, in this embodiment, eight picture elements are read out simultaneously.

The 2×8 pixel data sequentially read out from the memory blocks 20 and 21 in this way is input to the arithmetic circuit 3, where it is computed so that the information of the original image is not lost, and the 1×4 pixel data is converted into data.

To avoid losing the information in the original image, for example, if there is a line of one pixel, if you simply thin it out and reduce it to 1/2, the line of one pixel that was in the original image will be removed. (This technique is known from the reduction technique used in general television broadcasting, etc.). This must be avoided especially in line images, so it means trying to avoid it as much as possible. Here, since it is a binary image and is reduced by 1/2, the logical sum (hereinafter R
(abbreviated as ) is performed by calculation.

FIG. 4 shows a detailed block diagram of the arithmetic circuit 3. As shown in the figure, the data of 2×8 picture elements read from memory blocks 20 and 21 are input to R circuits 300 and 301, respectively, and the outputs of each are input to R circuit 302 to generate a 2×8 picture element. The raw image data is converted to 1×4 picture element image data. Each of the R circuits 300, 301, and 302 is composed of four 2-input R gates.

FIG. 5 is a circuit diagram showing the connection relationship between R circuits 300, 301, and 302. R gate 300-
1 to 300-4 are picture element data groups in Figure 3.
8 picture elements of BE ₀ (X ₀ , Y ₀ ) (X ₁ , Y ₀ ), (X ₂ , Y ₀ ) ~
Among the picture element data of (X ₇ , Y ₀ ), (X ₀ , Y ₀ ), (X ₁ ,
Y ₀ ) to R gate 300-1, (X ₂ , Y ₀ )(X ₃ ,
Y ₀ ) to R gate 300-2, (X ₄ , Y ₀ ),
(X ₅ , Y ₀ ) to R gate 300-3, (X ₆ ,
Y ₀ ) and (X ₇ , Y ₀ ) are respectively input to the R gate 300-4 and the logical sum is taken. Further, the eight picture elements of the picture element data group _B0 in FIG. 3 are similarly input to the R gates 301-1 to 301-4, and the logical sum is taken. Furthermore, R gate 302-
1 to 302-4, R circuits 300 and 301
the corresponding outputs, i.e. 300-1 and 301
-1, 300-2 and 301-2, 300-3 and 3
The respective logical sums of 01-3, 300-4 and 301-4 are calculated and output. Therefore, the output of this arithmetic circuit 3 is, for example, for the picture element data groups BE ₀ and B ₀ , the four adjacent picture elements [(X ₀ , Y ₀ ), (X ₁ , Y ₀ ), (X ₀ , Y ₁ ), (X ₁ ,
Y ₁ )], [(X ₂ , Y ₀ ), (X ₃ , Y ₀ ), (X ₂ , Y ₁ ), (X ₃
，
Y ₁ )], [(X ₄ , Y ₀ ), (X ₅ , Y ₀ ), (X ₄ , Y ₁ ), (X ₅
，
Y ₁ )], [(X ₆ , Y ₀ ), (X ₇ , Y ₀ ) (X ₆ , Y ₁ ), (X ₇ ,
Y ₁ )]. The image data read out from the memory blocks 20 and 21 as described above and calculated by the calculation circuit 3 is input to the display control circuit 4, where the 4-bit parallel data is converted to 1-bit serial data. The signal is converted, combined with horizontal/vertical synchronizing signals, and input to the display monitor 5 for display.

In this way, an image display device is realized that can reduce the entire contents of the frame memory, which has a capacity larger than the number of pixels that can be displayed on one screen of the display monitor, in real time without losing the information of the original image and display it on the display monitor. can.

In the above-mentioned embodiment, the case of binary data was explained, but even in the case of multi-value data, the arithmetic circuit 3 for reducing the size so as not to lose the information of the original image can be configured to This can be achieved in the same way as the binary case by creating a circuit that calculates the average of . In addition, in order to further reduce the display to 1/4, 1/8, etc., divide the memory block configuration into 4, 8, etc. blocks and store them sequentially in horizontal line units at the time of writing. Simultaneously access when reading, 16 points become 1 point, 64 points become 1 point
This can be achieved by performing an operation such as ... on a point and displaying it.

Therefore, according to the present invention, by skillfully combining memory blocks and arithmetic circuits, it is possible to obtain a reduced image without losing the information of the original image, and the effect is particularly great in processing line images. There is something.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing the detailed structure of a memory block, and FIG. 3 is a conceptual diagram for explaining picture element blocks that are simultaneously read out from the memory block. 4 are block diagrams showing the detailed configuration of the arithmetic circuit 3, and FIG. 5 is a circuit diagram showing detailed connections of the arithmetic circuit 3. In the figure, 1 is a read/write control circuit, 2
3 is a frame memory, 3 is an arithmetic circuit, 4 is a display control circuit, and 5 is a display monitor.

Claims (1)

[Claims] 1 to 2 ^N memory blocks, each block sequentially distributing and storing original image data constituting one screen in units of scanning lines; and 2 ^N memory blocks from the 2 ^N memory blocks of the frame memory means.
A readout control means for simultaneously reading out ^2N sets of continuous plurality of picture element data corresponding to the horizontal coordinate positions on the scanning line of the book; and ^2N sets of continuous picture element data simultaneously read out from the frame memory means. a calculation means for converting the pixel data outputted from the calculation means into continuous pixel data on one scanning line that is horizontally reduced to 1/2 ^N without losing information in the original image memory; a display control means for converting the video signal into a video signal for display; and a display means for displaying the output video signal of the display control means;
An image display device characterized by displaying one screen of image data stored in a frame memory means in real time and reduced to 1/ ^2N so as not to lose the information of the original image.