JPS625358B2 - - Google Patents
Info
- Publication number
- JPS625358B2 JPS625358B2 JP2220579A JP2220579A JPS625358B2 JP S625358 B2 JPS625358 B2 JP S625358B2 JP 2220579 A JP2220579 A JP 2220579A JP 2220579 A JP2220579 A JP 2220579A JP S625358 B2 JPS625358 B2 JP S625358B2
- Authority
- JP
- Japan
- Prior art keywords
- metal thin
- thin film
- film
- conductor pattern
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910052751 metal Inorganic materials 0.000 claims description 54
- 239000002184 metal Substances 0.000 claims description 54
- 239000010409 thin film Substances 0.000 claims description 54
- 239000010408 film Substances 0.000 claims description 49
- 239000004020 conductor Substances 0.000 claims description 35
- 239000012212 insulator Substances 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 19
- 238000010304 firing Methods 0.000 claims description 17
- 239000000919 ceramic Substances 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000007772 electroless plating Methods 0.000 claims description 2
- 229910052741 iridium Inorganic materials 0.000 claims description 2
- 229910052742 iron Inorganic materials 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 229910052762 osmium Inorganic materials 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 229910052702 rhenium Inorganic materials 0.000 claims description 2
- 229910052703 rhodium Inorganic materials 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 229910052720 vanadium Inorganic materials 0.000 claims description 2
- 229910052726 zirconium Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 description 21
- 230000000052 comparative effect Effects 0.000 description 12
- 238000007747 plating Methods 0.000 description 10
- 239000000853 adhesive Substances 0.000 description 8
- 230000001070 adhesive effect Effects 0.000 description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- AFCARXCZXQIEQB-UHFFFAOYSA-N N-[3-oxo-3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)propyl]-2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidine-5-carboxamide Chemical compound O=C(CCNC(=O)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F)N1CC2=C(CC1)NN=N2 AFCARXCZXQIEQB-UHFFFAOYSA-N 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- VZSRBBMJRBPUNF-UHFFFAOYSA-N 2-(2,3-dihydro-1H-inden-2-ylamino)-N-[3-oxo-3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)propyl]pyrimidine-5-carboxamide Chemical compound C1C(CC2=CC=CC=C12)NC1=NC=C(C=N1)C(=O)NCCC(N1CC2=C(CC1)NN=N2)=O VZSRBBMJRBPUNF-UHFFFAOYSA-N 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- YLZOPXRUQYQQID-UHFFFAOYSA-N 3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)-1-[4-[2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidin-5-yl]piperazin-1-yl]propan-1-one Chemical compound N1N=NC=2CN(CCC=21)CCC(=O)N1CCN(CC1)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F YLZOPXRUQYQQID-UHFFFAOYSA-N 0.000 description 1
- HCYDVSFCQZCWOF-UHFFFAOYSA-N [O-2].[O-2].[O-2].[O-2].[O-2].[V+5].B(O)(O)O.[V+5] Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[V+5].B(O)(O)O.[V+5] HCYDVSFCQZCWOF-UHFFFAOYSA-N 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000005355 lead glass Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
本発明は薄膜又は厚膜の導体パターンと厚膜絶
縁体を組合せた混成回路基板の製造方法の改良に
関する。
周知の如く、この種の混成回路基板はCML、
ECL、TTL、MOSなどのICやLSI等を実装する
のに用いられている。このため、実装されたIC
やLSIの信号線となる導電パターンはセラミツク
基板に対して強固に形成されると共に実装密度を
上げるため断面積が小さく、線巾が小さくなるよ
うに設計することが望ましい。
ところで、従来、混成回路基板を製造するには
セラミツク基板上に単一金属からなる導体パター
ンを形成した後、該導体パターンの少なくとも一
部に厚膜絶縁体を被覆する方法が採用されている
が、厚膜絶縁体の形成に際しての焼成により導体
パターンがクラツク等を発生する不都合さがあ
る。
このようなことから、最近、RCA社等からア
ルミナ基板上にCuとAuからなる２層構造の導電
パターンを形成する方法が開発されている。しか
しながら、この方法で形成された導電パターンは
基板であるアルミナとこの基板に接触するCuと
の間の接着強度が弱いために、導電パターンが剥
離し易く信頼性の点で問題がある。また、２層構
造の導電パターンとしてCr／Au、Ti／Auからな
るものも提案されているが、この導体パターン上
に厚膜絶縁ペーストを被覆し焼成すると、厚膜絶
縁体中にAuの接着用金属であるCr、Tiが拡散
し、その結果Au膜が分断されて信号線がオープ
ンとなる不都合さがある。
一方、上記方法とは別に選択メツキによる金パ
ターンを利用して導体パターンを形成する方法が
提案されている（昭和50年12月15日、電通学会、
Vol 75、No.176）。この方法はセラミツク基板上
にTi膜を蒸着し、さらにTi膜上にはAuメツキが
付着し難いためにこのTi膜上にAu選択メツキの
ための導電膜（Ni膜）を被着した後、この導電
膜上にAu選択メツキにより金パターンを形成
し、さらに該金パターンをマスクとして露出する
導電膜部分及びその下のTi膜部分をエツチング
除去して導電パターンを形成するものである。し
かしながら、この方法にあつてはAu選択メツ
キ、Auパターンをマスクとするエツチング除去
等のプロセスの複雑さにより作業能率の低下を招
く。また、Au選択メツキ時における金パターン
の精度がメツキマスクの性状に多大に影響され、
製造歩留りが悪いという欠点がある。さらに、
Au選択メツキに際してのメツキ電極の取付部を
導体パターンとは別の個所に設けなければならな
い等の問題がある。
そこで、本発明者は上記欠点を解消するために
鋭意研究した結果、厚膜絶縁体に対して拡散し易
い性質を有するものの、セラミツク基板に対する
接着性が良好な金属薄膜（第１の金属薄膜）をセ
ラミツク基板上に被着し、この金属薄膜上に酸化
し難く電気伝導性の良好な金属薄膜（第３の金属
薄膜）をじかに被着せず、これら第１、第３の金
属膜と異なる金属薄膜（第２の金属薄膜）を介し
て被着した３層構造膜で導体を構成することによ
つて、セラミツク基板に対する接着強度も、厚膜
絶縁体に対する第１の金属薄膜が拡散しても第２
の金属薄膜のセラミツクに対しての強度を保ち、
且つ、絶縁体下では、第２の金属はセラミツクに
対してさほど強度が強くないが、絶縁体によつて
覆れているので、第１の金属ほどの強度は不要で
あることを究明した。
しかして、本発明者は上記知見を踏えて更に研
究を重ねセラミツク基板上に上述の第１、第２、
第３の金属薄膜を順次被着した後、レジストパタ
ーンをマスクとする写真蝕刻法等により選択的に
エツチングすることによつて、従来の選択Auメ
ツキによる煩雑かつ厳格な工程管理を招くことな
く接着強度も厚膜絶縁体への適合性も満足した導
体パターンを備えた混成回路基板を極めて簡単か
つ歩留りよく製造し得る方法を見い出した。な
お、本発明により得た混成回路基板について更に
詳しく説明すれば、厚膜絶縁体に被覆されていな
い導体パターン部分はその最下層の第１の金属薄
膜によりセラミツク基板への接着性が補償され、
一方、厚膜絶縁体に被覆されている導体パターン
部分は第２の金属薄膜と第１、第３の金属薄膜と
が厚膜絶縁体を形成するときの焼成工程での高温
下で合金化することにより、厚膜絶縁体中に第１
の金属薄膜等が拡散することが防止される。第２
の金属は、第１の金属に比べセラミツクに対する
付着強度は劣るが、絶縁体がこの導体膜を被覆し
ているため、第２の金属と第３の金属が形状変化
し、分断されることはない。
すなわち、本発明はセラミツク基板上に薄膜又
は厚膜の導体パターンを形成し、さらに該導電パ
ターン上の少なくとも一部に厚膜絶縁体を形成し
て混成回路基板を製造するにあたり、セラミツク
基板上に該基板に対して接着力が強い第１の金属
薄膜、酸化し難い電気伝導性が良好な第３の金属
薄膜、及び第１、第３の金属薄膜の間にこれらと
異なる第２の金属薄膜を介在させた三層構造膜を
第１、第２、第３の金属薄膜の順序で形成する工
程と、この三層構造膜を選択的にエツチングして
導体パターンを形成する工程と、この導体パター
ンの少なくとも一部に絶縁ペーストを被覆した後
焼成せしめて厚膜絶縁体を形成する工程とを具備
したことを特徴とするものである。
本発明に使用するセラミツク基板としては、例
えばアルミナ基板、ガラス基板等を挙げることが
できる。
本発明に使用する第１の金属薄膜とは、基板に
対する接着力は強いが、厚膜絶縁体に対して拡散
し易い性質を有するもので、通常、酸化物自由生
成エネルギーが−130kcal／molより絶対値が大
きいものである。この第１の金属薄膜を具体的に
例示すれば、Ti、Zr、Ｖ及びCrのうち少なくと
も１種からなるものである。また、第１の金属薄
膜の厚さとしては50〜1000Åの範囲にすることが
望ましい。
本発明に使用する第２金属薄膜は基板に対する
接着力は劣るが、第１、第３の金属薄膜と異なる
材質であつて、これらと合金化し易いものであれ
ばよく、通常、酸化生成自由エネルギーが−90〜
120kcal／mol程度のものである。但し、第２の
金属薄膜は電気伝導性が格段に優れている必要性
はなく、第３の金属薄膜の下地として役目を有れ
ば足りる。この第２の薄膜を具体的に示すと
Ni、Cu、Co、Mo、Fe、Ｗ及びTaのうち少なく
とも１種からなるものである。また、第２の薄膜
の厚さは50〜2000Åの範囲にすることが望まし
い。
本発明に使用する第３の金属薄膜とは酸化し難
く電気伝導性の良好なものであり、具体的には
Au、Pt、Pd、Ir、Os、Re、Rhのうちの少くと
も１種からなるものである。また、第３の金属薄
膜の厚さは5000Å〜２μｍの範囲にすることが望
ましい。これ以上厚くしてもかまわないが、これ
は価格と要求する電気抵抗とのかね合いで決ま
る。
本発明における第１、第２、第３の金属薄膜の
被着手段としては、無電解メツキ、スパツタ、蒸
着等が採用し得る。
本発明における３層構造膜の選択エツチング手
段としては、例えばレジストパターンをマスクと
する写真蝕刻法等が採用し得る。
本発明に使用する絶縁ペーストとしては、例え
ば（Al2O3）o−（SiO2）o-1系ペースト、SiO2−PbO
系ペースト、硼珪酸ガラスペースト、硼珪酸鉛ガ
ラスペースト、硼酸酸化バナジウム系ペースト等
を挙げることができる。
次に、本発明の実施例を説明する。
実施例
アルミナ基板上に、スパツタ法により厚さ600
ÅのTi薄膜、厚さ1000ÅのNi薄膜、及び厚さ１
μｍのAu薄膜を順次被着して３層構造膜を形成
した。次いで、この３層構造膜をレジストパター
ンをマスクとした写真蝕刻法により選択的にエツ
チングして巾100μｍの導体パターンを形成し
た。その後、この導体パターン上に（Al2O3）o−
（SiO2）o-1系ペーストを塗布し、925℃で焼成せし
めて厚膜絶縁体を形成し混成回路基板を造つた。
しかして、本実施例の混成回路基板及び100μ
ｍ巾の導体パターンが100ÅTi／6000ÅAuからな
る混成回路基板（比較例１−１）、同パターンが
100ÅTi／１μｍAuからなる混成回路基板（比較
例１−２）、同パターンが1000ÅNi／１μｍAuか
らなる混成回路基板（比較例２−１）、同パター
ンが1000ÅNi／２μｍAuからなる混成回路基板
（比較例２−１）について、次のような評価条件
で導体パターンの抵抗変化を調べたところ、図の
如き結果となつた。評価は、絶縁体被覆前で焼成
前、同被覆前で925℃の１回焼成、同被覆前で４
回焼成、絶縁体被覆後で925℃の１回焼成、２回
焼成、３回焼成、４回焼成及び５回焼成、の８種
の条件下での導体パターンの抵抗変化を調べるこ
とにより行なつた。なお、図中のＡは本実施例の
導体パターンにおける抵抗特性曲線、B1は比較
例１−１の導体パターンにおける同特性曲線、
B2は比較例１−２の導体パターンにおける同特
性曲線、C1は比較例２−１の導体パターンにお
ける同特性曲線、C2は比較例２−２の導体パタ
ーンにおける同特性曲線である。
また、本実施例及び比較例１−２、比較例２−
１の導体パターンのアルミナ基板に対する接着強
度を調べたところ、下記表の如き結果となつた。
The present invention relates to an improved method for manufacturing a hybrid circuit board that combines a thin film or thick film conductor pattern and a thick film insulator. As is well known, this type of hybrid circuit board is CML,
It is used to implement ICs and LSIs such as ECL, TTL, and MOS. For this reason, the implemented IC
It is desirable that conductive patterns, which serve as signal lines for LSIs, be firmly formed on the ceramic substrate and designed to have a small cross-sectional area and small line width in order to increase packaging density. By the way, conventionally, in order to manufacture a hybrid circuit board, a method has been adopted in which a conductor pattern made of a single metal is formed on a ceramic substrate, and then at least a portion of the conductor pattern is coated with a thick film insulator. However, there is an inconvenience that cracks occur in the conductor pattern due to firing during the formation of the thick film insulator. For this reason, RCA and other companies have recently developed a method for forming a two-layer conductive pattern made of Cu and Au on an alumina substrate. However, the conductive pattern formed by this method has a problem in reliability because the adhesive strength between the alumina substrate and the Cu in contact with the substrate is weak, so the conductive pattern easily peels off. Also, two-layer conductive patterns made of Cr/Au and Ti/Au have been proposed, but when this conductive pattern is coated with a thick film insulating paste and fired, Au adheres to the thick film insulator. There is an inconvenience that the metals Cr and Ti diffuse, resulting in the Au film being divided and the signal line becoming open. On the other hand, apart from the above method, a method has been proposed in which a conductor pattern is formed using a gold pattern by selective plating (December 15, 1975, IEICE,
Vol. 75, No. 176). In this method, a Ti film is deposited on a ceramic substrate, and since it is difficult for Au plating to adhere to a Ti film, a conductive film (Ni film) for selective Au plating is deposited on this Ti film. A gold pattern is formed on this conductive film by selective Au plating, and the exposed conductive film portion and the underlying Ti film portion are removed by etching using the gold pattern as a mask to form a conductive pattern. However, in this method, the work efficiency is lowered due to the complexity of processes such as Au selective plating and etching removal using the Au pattern as a mask. In addition, the accuracy of the gold pattern during Au selective plating is greatly influenced by the properties of the plating mask,
It has the disadvantage of poor manufacturing yield. moreover,
There are problems such as the need to provide a mounting portion for the plating electrode at a location different from the conductor pattern when selectively plating Au. Therefore, as a result of intensive research in order to eliminate the above-mentioned drawbacks, the inventors of the present invention have developed a metal thin film (first metal thin film) that has the property of easily diffusing into thick film insulators but has good adhesion to ceramic substrates. is deposited on a ceramic substrate, and a metal thin film (third metal thin film) that is difficult to oxidize and has good electrical conductivity is not directly deposited on this metal thin film, and a metal different from these first and third metal films is used. By constructing the conductor with a three-layer structure film deposited via a thin film (second metal thin film), the adhesive strength to the ceramic substrate can be improved even when the first metal thin film is diffused to the thick film insulator. Second
Maintains the strength of the metal thin film against ceramic,
Furthermore, it was found that although the second metal is not as strong as the ceramic under the insulator, since it is covered by the insulator, it does not need to be as strong as the first metal. Based on the above knowledge, the present inventor has conducted further research and found that the above-mentioned first, second, and
After sequentially depositing the third metal thin film, selective etching is performed using a photolithography method using a resist pattern as a mask, allowing bonding without the complicated and strict process control required by conventional selective Au plating. We have found a method for manufacturing a hybrid circuit board with a conductor pattern that has satisfactory strength and compatibility with thick film insulators in an extremely simple manner and with high yield. In addition, to explain in more detail about the hybrid circuit board obtained according to the present invention, the adhesiveness of the conductor pattern portion not covered with the thick film insulator to the ceramic substrate is compensated by the first metal thin film in the lowermost layer,
On the other hand, the conductor pattern portion covered with the thick film insulator is alloyed at high temperatures during the firing process when the second metal thin film and the first and third metal thin films form the thick film insulator. By this, the first layer is formed in the thick film insulator.
This prevents the metal thin film etc. from diffusing. Second
The adhesive strength of this metal to the ceramic is inferior to that of the first metal, but since the insulator covers this conductor film, the second metal and third metal will not change shape and be separated. do not have. That is, the present invention forms a thin film or thick film conductor pattern on a ceramic substrate, and further forms a thick film insulator on at least a portion of the conductive pattern to produce a hybrid circuit board. A first metal thin film that has strong adhesion to the substrate, a third metal thin film that is resistant to oxidation and has good electrical conductivity, and a second metal thin film different from these between the first and third metal thin films. a step of forming a three-layer structure film in the order of first, second, and third metal thin films; a step of selectively etching this three-layer structure film to form a conductor pattern; The method is characterized by comprising a step of coating at least a portion of the pattern with an insulating paste and then firing it to form a thick film insulator. Examples of the ceramic substrate used in the present invention include an alumina substrate and a glass substrate. The first metal thin film used in the present invention has strong adhesion to the substrate, but has the property of easily diffusing into thick film insulators, and usually has an oxide free formation energy of less than -130 kcal/mol. The absolute value is large. A specific example of this first metal thin film is one made of at least one of Ti, Zr, V, and Cr. Further, the thickness of the first metal thin film is preferably in the range of 50 to 1000 Å. Although the second metal thin film used in the present invention has poor adhesion to the substrate, it may be made of a material different from the first and third metal thin films and easily alloyed with them, and usually has a free energy of oxidation formation. is −90~
It is about 120kcal/mol. However, the second metal thin film does not need to have particularly excellent electrical conductivity; it is sufficient if it serves as a base for the third metal thin film. Specifically, this second thin film is
It consists of at least one of Ni, Cu, Co, Mo, Fe, W, and Ta. Further, it is desirable that the thickness of the second thin film is in the range of 50 to 2000 Å. The third metal thin film used in the present invention is one that is difficult to oxidize and has good electrical conductivity.
It is composed of at least one of Au, Pt, Pd, Ir, Os, Re, and Rh. Further, it is desirable that the thickness of the third metal thin film is in the range of 5000 Å to 2 μm. It may be made thicker than this, but this is determined by the balance between price and required electrical resistance. In the present invention, electroless plating, sputtering, vapor deposition, etc. can be employed as the means for depositing the first, second, and third metal thin films. As the means for selectively etching the three-layer structure film in the present invention, for example, a photolithographic method using a resist pattern as a mask can be employed. Examples of the insulating paste used in the present invention include (Al 2 O 3 ) o -(SiO 2 ) o-1 paste, SiO 2 -PbO
Examples include a borosilicate glass paste, a borosilicate lead glass paste, a boric acid vanadium oxide paste, and the like. Next, examples of the present invention will be described. Example A thickness of 600 mm was deposited on an alumina substrate using the sputtering method.
Å thick Ti thin film, 1000 Å thick Ni thin film, and 1 Å thick Ni thin film.
A three-layer structure film was formed by sequentially depositing μm thick Au thin films. Next, this three-layer structure film was selectively etched by photolithography using the resist pattern as a mask to form a conductor pattern with a width of 100 μm. Then, on this conductor pattern (Al 2 O 3 ) o −
(SiO 2 ) O-1 paste was applied and fired at 925°C to form a thick film insulator and a hybrid circuit board was fabricated. Therefore, the hybrid circuit board of this embodiment and the 100μ
A hybrid circuit board (comparative example 1-1) with a m-wide conductor pattern of 100ÅTi/6000ÅAu,
A hybrid circuit board made of 100ÅTi/1μmAu (Comparative Example 1-2), a hybrid circuit board with the same pattern made of 1000ÅNi/1μmAu (Comparative Example 2-1), a hybrid circuit board with the same pattern made of 1000ÅNi/2μmAu (Comparative Example 2) Regarding -1), when the resistance change of the conductor pattern was investigated under the following evaluation conditions, the results were as shown in the figure. The evaluation is before firing before insulation coating, once firing at 925℃ before insulation coating, and 4 degrees before insulation coating.
This was done by examining the resistance change of the conductor pattern under eight conditions: double firing, once firing at 925℃ after insulator coating, twice firing, third firing, fourth firing, and fifth firing. Ta. In addition, A in the figure is the resistance characteristic curve of the conductor pattern of this example, B1 is the same characteristic curve of the conductor pattern of Comparative Example 1-1,
B 2 is the same characteristic curve for the conductor pattern of Comparative Example 1-2, C 1 is the same characteristic curve for the conductor pattern of Comparative Example 2-1, and C 2 is the same characteristic curve for the conductor pattern of Comparative Example 2-2. In addition, this example, Comparative Example 1-2, Comparative Example 2-
When the adhesive strength of the conductor pattern No. 1 to the alumina substrate was investigated, the results were as shown in the table below.
【表】
上述した図及び表から明らかなように本発明の
混成回路基板における３層構造からなる導体パタ
ーンは厚膜絶縁体の被覆の有無、焼成回数に関係
なく抵抗変化が全くなく（図中のＡ参照）しかも
アルミナ基板に対して高い接着強度を有すること
がわかる。これに対し、導電パターンがTi／Au
からなる比較例１−１、１−２は基板上で単に焼
成を繰り返す場合には抵抗の変化がないが、厚膜
絶縁体を被覆すると、抵抗が上昇し、ついには断
線となる。また、導体パターンがNi／Auからな
る比較例２−１、２−２は厚膜絶縁体被覆後も抵
抗の変化がないが上表に示すように基板に対する
接着強度が24Kg／cm2と著しく弱い欠点がある。
以上詳述した如く、本発明によればセラミツク
基板上に３層構造膜を被覆し、この３層構造膜を
選択的にエツチングして導体パターンを形成した
後、この導体パターンの少なくとも一部に厚膜絶
縁体を形成することによつて、セラミツク基板に
対する導体パターンの接着性を第１の金属薄膜で
補償し、かつ厚膜絶縁体の形成に際しての焼成時
に第１の金属薄膜が拡散しその上の第３の金属薄
膜が分断されるのを第１〜第３の金属薄膜が焼成
時の高温によつて合金化することで防止でき、セ
ラミツク基板に対する接着強度も厚膜絶縁体への
適合性も十分満足し得る導体パターンを備えた信
頼性の高い混成回路基板を簡単かつ歩留りより製
造できる等顕著な効果を有する。[Table] As is clear from the above figures and tables, the conductor pattern consisting of the three-layer structure in the hybrid circuit board of the present invention has no resistance change at all regardless of whether it is covered with a thick film insulator or the number of firings (in the figure). (see A) Furthermore, it is clear that the adhesive has high adhesive strength to the alumina substrate. In contrast, the conductive pattern is Ti/Au
In Comparative Examples 1-1 and 1-2, there is no change in resistance when firing is simply repeated on the substrate, but when a thick film insulator is coated, the resistance increases and eventually wire breakage occurs. In addition, in Comparative Examples 2-1 and 2-2, in which the conductor pattern is made of Ni/Au, there is no change in resistance even after coating with a thick film insulator, but as shown in the table above, the adhesive strength to the substrate is remarkable at 24 kg/cm 2 . There are weak drawbacks. As described in detail above, according to the present invention, a three-layer structure film is coated on a ceramic substrate, a conductor pattern is formed by selectively etching the three-layer structure film, and then at least a portion of the conductor pattern is etched. By forming the thick film insulator, the adhesion of the conductor pattern to the ceramic substrate is compensated by the first metal thin film, and the first metal thin film is diffused during firing to form the thick film insulator. The first to third metal thin films are alloyed by the high temperature during firing to prevent the upper third metal thin film from being separated, and the adhesive strength to the ceramic substrate is also compatible with thick film insulators. This method has remarkable effects such as being able to easily manufacture a highly reliable hybrid circuit board with a conductor pattern that satisfies the performance and has a high yield.
図は本発明の実施例及び従来の混成回路基板に
おける導体パターンの厚膜絶縁体の被覆前、被覆
後の焼成による抵抗値変化を示す特性図である。
The figure is a characteristic diagram showing resistance value changes due to firing before and after coating of the thick film insulator of the conductor pattern in the embodiment of the present invention and the conventional hybrid circuit board.
Claims (1)
成し、さらに該導体パターン上の少なくとも一部
に厚膜絶縁体を形成して混成回路基板を製造する
にあたり、セラミツク基板上に該基板に対して接
着力が強い第１の金属薄膜、酸化し難い電気伝導
性が良好な第３の金属薄膜、及び第１、第３の金
属薄膜の間にこれらと異なる第２の金属薄膜を介
在させた三層構造膜を第１、第２、第３の金属薄
膜の順序で形成する工程と、この三層構造膜を選
択的にエツチングして導体パターンを形成する工
程と、この導体パターンの少なくとも一部に絶縁
ペーストを被覆した後焼成せしめて厚膜絶縁体を
形成する工程とを具備したことを特徴とする混成
回路基板の製造方法。 ２ 第１の金属薄膜がTi、Zr、Ｖ及びCrのうち
の少なくとも一種、第２の金属薄膜がNi、Cu、
Co、Mo、Fe、Ｗ及びTaのうちの少なくとも一
種、第３の金属薄膜がAu、Pt、Pd、Ir、Os、
Re、Rhのうちの少なくとも一種からなることを
特徴とする特許請求の範囲第１項記載の混成回路
基板の製造方法。 ３ 第１の金属薄膜の厚さが50〜1000Å、第２の
金属薄膜の厚さが50〜2000Å、第３の金属薄膜の
厚さが5000Å〜２μｍであることを特徴とする特
許請求の範囲第１項または第２項記載の混成回路
基板の製造方法。 ４ 第１、第２、第３の金属薄膜を無電解メツキ
またはスパツタにより形成することを特徴とする
特許請求の範囲第１項記載の第１項〜ないし第３
項のいずれかに記載の混成回路基板の製造方法。[Claims] 1. In manufacturing a hybrid circuit board by forming a thin film conductor pattern on a ceramic substrate and further forming a thick film insulator on at least a portion of the conductor pattern, A first metal thin film that has strong adhesion to the substrate, a third metal thin film that is difficult to oxidize and has good electrical conductivity, and a second metal thin film different from these between the first and third metal thin films. a step of forming an interposed three-layer structure film in the order of first, second, and third metal thin films; a step of selectively etching the three-layer structure film to form a conductor pattern; and a step of forming a conductor pattern by selectively etching the three-layer structure film; 1. A method for manufacturing a hybrid circuit board, comprising the step of coating at least a portion of the insulating paste with an insulating paste and then firing the insulating paste to form a thick film insulator. 2 The first metal thin film is at least one of Ti, Zr, V, and Cr, and the second metal thin film is Ni, Cu,
At least one of Co, Mo, Fe, W and Ta, the third metal thin film is Au, Pt, Pd, Ir, Os,
The method for manufacturing a hybrid circuit board according to claim 1, characterized in that the hybrid circuit board is made of at least one of Re and Rh. 3 Claims characterized in that the first metal thin film has a thickness of 50 to 1000 Å, the second metal thin film has a thickness of 50 to 2000 Å, and the third metal thin film has a thickness of 5000 Å to 2 μm. A method for manufacturing a hybrid circuit board according to item 1 or 2. 4. Items 1 to 3 of Claim 1, wherein the first, second, and third metal thin films are formed by electroless plating or sputtering.
A method for manufacturing a hybrid circuit board according to any one of paragraphs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2220579A JPS55115392A (en) | 1979-02-27 | 1979-02-27 | Method of fabricating hybrid circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2220579A JPS55115392A (en) | 1979-02-27 | 1979-02-27 | Method of fabricating hybrid circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55115392A JPS55115392A (en) | 1980-09-05 |
| JPS625358B2 true JPS625358B2 (en) | 1987-02-04 |
Family
ID=12076283
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2220579A Granted JPS55115392A (en) | 1979-02-27 | 1979-02-27 | Method of fabricating hybrid circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55115392A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6486224A (en) * | 1987-09-28 | 1989-03-30 | Nec Corp | Standby device for microcomputer |
| JPH07212988A (en) * | 1994-01-14 | 1995-08-11 | Fujitsu Ten Ltd | Power supply for microcomputer |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4628149A (en) * | 1981-11-30 | 1986-12-09 | Nippon Electric Co., Ltd. | Substrate having a pattern of an alloy of gold and a noble and a base metal with the pattern isolated by oxides of the noble and the base metals |
| JPH0382188A (en) * | 1989-08-25 | 1991-04-08 | Kyocera Corp | Manufacture of ceramic wiring board |
| JP4921426B2 (en) * | 2008-06-30 | 2012-04-25 | イースタン技研株式会社 | Fresh water rust prevention treatment equipment |
-
1979
- 1979-02-27 JP JP2220579A patent/JPS55115392A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6486224A (en) * | 1987-09-28 | 1989-03-30 | Nec Corp | Standby device for microcomputer |
| JPH07212988A (en) * | 1994-01-14 | 1995-08-11 | Fujitsu Ten Ltd | Power supply for microcomputer |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55115392A (en) | 1980-09-05 |
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