JPS62535B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus, and particularly to an information processing apparatus that can process two different microprograms in parallel and synchronize them when necessary.

A conventional information processing device is provided corresponding to a first microprogram consisting of a series of first microinstructions, and instructs a first microinstruction decoding circuit to perform decoding in an initial state and after execution of the first microinstructions. generating a first decode cycle signal for decoding the first microinstruction; generating a first wait cycle signal until a first condition fulfillment signal is supplied after decoding the first microinstruction; and generating a first wait cycle signal after decoding the first microinstruction; a first cycle control circuit that generates a first execution cycle signal that instructs a first microinstruction execution circuit to execute when the first condition fulfillment signal is supplied; and a first cycle control circuit that is parallel to the first microprogram. A second microinstruction decoding circuit is provided for instructing a second microinstruction decoding circuit to perform decoding in an initial state and after execution of the second microinstructions. generating a second decode cycle signal; generating a second wait cycle signal until a second condition fulfillment signal is supplied after decoding the second microinstruction; and generating the second wait cycle signal after decoding the second microinstruction; and a second cycle control circuit that generates a second execution cycle signal that instructs the second microinstruction execution circuit to execute when the condition fulfillment signal is supplied.

In this way, the conventional information processing apparatus processes two different microprograms in parallel.

However, if it becomes necessary to synchronize one microprogram with another, to achieve the synchronization, e.g.
Information indicating that synchronization is required.
As a test condition, the microprogram that receives the information is tested multiple times after being able to transmit it to the other microprogram, and synchronization is performed for the first time when the test is successful. This had the drawback of increasing the number of steps in the program and increasing the time required for synchronization.

In other words, the conventional information processing apparatus has the disadvantage that synchronization takes time.

An object of the present invention is to provide an information processing device that can shorten synchronization time.

In other words, an object of the present invention is to eliminate the need for synchronization by the microprogram itself, such as executing the same instruction multiple times when synchronizing two microprograms, by adding a synchronization circuit, and to reduce the time required for synchronization. The purpose is to provide information processing that can save time.

That is, an object of the present invention is to eliminate the need to execute the same instruction multiple times when synchronizing two microprograms by dividing one machine cycle into a decode cycle and an execution cycle, thereby reducing the time required for synchronization. Our goal is to provide an information processing device that can.

The information processing device of the present invention is provided corresponding to a first microprogram consisting of a series of first microinstructions, and causes a first microinstruction decoding circuit to perform decoding in an initial state and after execution of the first microinstructions. generates a first decode cycle signal for instructing, and after decoding the first microinstruction, the first decode cycle signal is
generates a wait cycle signal, and generates a first execution cycle signal that instructs a first microinstruction execution circuit to execute when the first condition fulfillment signal is supplied after decoding the first microinstruction; a first cycle control circuit; and a second microprogram which is processed in parallel with the first microprogram and includes a series of second microinstructions, and which is brought into an initial state when a synchronization signal is supplied. A second decode cycle signal is generated in an initial state and after execution of the second microinstruction, and a second wait cycle signal is generated after the second microinstruction is decoded until a second condition fulfillment signal is supplied. a second cycle control circuit that generates a second execution cycle signal when the second condition fulfillment signal is supplied after decoding the second microinstruction; a third decode cycle signal for selecting the second decode cycle signal and instructing the second microinstruction decoding circuit to decode by selecting the first decode cycle signal when the synchronization signal is supplied; selects the second execution cycle signal when the synchronization signal is generated and the synchronization signal is not supplied, and selects the first execution cycle signal when the synchronization signal is supplied to the second microinstruction execution circuit. and a synchronization circuit that generates a third execution cycle signal for instructing execution.

That is, the information processing device of the present invention has two different
In an information processing device that processes two microprograms in parallel, a circuit generates a decode cycle for decoding microinstructions for each microprogram, and as a result of the decoding of the microinstructions, the microinstructions are executed until a predetermined condition is satisfied. two cycle control circuits each having a circuit that generates a wait cycle when it is necessary to postpone the program and a circuit that generates an execution cycle that executes the microinstruction upon completion of the decode cycle and the wait cycle; and a synchronization circuit for synchronizing the decode cycle and execution cycle.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

The information processing device shown in FIG. 1 includes a first cycle control circuit CC, a second cycle control circuit CC', and a selection circuit SEL which is a synchronization circuit.

The cycle control circuit CC includes a decode cycle flip-flop 1 for generating a decode cycle signal B which is reset every time a clock P is supplied, and a wait cycle flip-flop for generating a wait cycle signal D. 3 and an execution cycle flip-flop 2 for generating an execution cycle signal C.

The cycle control circuit CC' also includes a decode cycle flip-flop 1' for generating a decode cycle signal B' which is reset every time the clock P is supplied, and a decode cycle flip-flop 1' for generating a wait cycle signal D'. Wait cycle flip-flop 3' and run cycle signal
It includes an execution cycle flip-flop 2' for generating C', and is brought to an initial state when a synchronization signal K is supplied.

Furthermore, the selection circuit SEL selects either the decode cycle signal B or B' depending on whether or not the synchronization signal K is supplied, and also selects either the execution cycle signal C or C' to decode the signal. It is output as a cycle signal H and an execution cycle signal J.

The cycle control circuit CC is provided corresponding to a first microprogram, and this first microprogram is composed of a series of first microinstructions. Further, the cycle control circuit CC' is provided corresponding to the second microprogram, and the cycle control circuit CC' is provided corresponding to the second microprogram.
The microprogram consists of a series of second microinstructions.

This first microprogram is processed according to a decode cycle signal B supplied to a first microinstruction decode circuit (not shown) and an execution cycle signal C supplied to a first microinstruction execution circuit (not shown).

Further, the second microprogram is processed in parallel with the first microprogram,
A decode cycle signal H supplied to a second micro-instruction decode circuit (not shown) and a second micro-instruction decode circuit (not shown)
The execution cycle signal J supplied to the microinstruction execution circuit is processed according to the execution cycle signal J.

Next, details of the cycle control circuit CC will be explained.

Decode cycle flip-flop 1 is a flip-flop that generates decode cycle signal B, and its positive output, which becomes decode cycle signal B, is also input to AND circuits 6 and 10. Further, a negative output indicating that the decoding is completed is input to an AND circuit 4, and the output of the AND circuit 4 is logically summed with a positive output that becomes an execution cycle signal C output from an execution cycle flip-flop 2, which will be described later. The input signal is taken as an input to the decode cycle flip-flop 1.

The execution cycle flip-flop 2 is a flip-flop that generates an execution cycle signal C;
Its positive output, which becomes the execution cycle signal C, is input to the OR circuit 5. Further, a negative output indicating that execution has ended is input to the AND circuit 4 described above.

Wait cycle flip-flop 3 is a flip-flop for generating wait cycle signal D, and its positive output, which becomes wait cycle signal D, is input to AND circuit 7 and AND circuit 11, and a negative output indicating that the wait has ended is inputted to AND circuit 7 and AND circuit 11. The output is input to an AND circuit 4. The condition fulfillment signal A is input to the AND circuits 6 and 7 and the inverter circuit 9, and the outputs of the AND circuits 6 and 7 are both input to the OR circuit 8.
The logical OR is taken at and becomes the input to the execution cycle flip-flop 2. On the other hand, the output of the inverter circuit 9 is input to AND circuits 10 and 11, and the outputs of the AND circuits 10 and 11 are logically summed together by an OR circuit 12 and are input to the wait cycle flip-flop 3.

Here, the decode cycle flip-flop 1
The positive outputs of the execution cycle flip-flop 3 are input to the selection circuit SEL as a decode cycle B and an execution cycle C, respectively, and are used to control the instructions of the first microprogram FW1.

1' to 12' in the cycle control circuit CC' are the same as 1 to 12 in the cycle control circuit CC.

Cycle control circuit CC′ and cycle control circuit CC
The difference is that a synchronization signal K is connected to the reset inputs of the decode cycle flip-flop 1', the wait cycle flip-flop 2', and the execution cycle flip-flop 3'. This synchronization signal K is also connected to the selection condition input of the selection circuit SEL, which is a synchronization circuit. The selection circuit SEL is a circuit that is a feature of the present invention, and is a circuit that selects decode cycle signals B, B', execution cycles C,
C' is input, and the output of this selection circuit SEL is the second
It is used to control the microinstructions of the microprogram FW2.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

Immediately after the power is turned on, decode cycle flip-flops 1 and 1', wait cycle flip-flops 3 and 3', and execution cycle flip-flops 2 and 2' are all set to "0", but when the first clock When P is input, decode cycle flip-flops 1 and 1' are set to "1". Here, when the condition fulfillment signal A is "1", the outputs of the AND circuit 6 and the OR circuit 8 become "1", and in the next cycle, the execution cycle flip-flop 2 is set, and the cycle following the decode cycle is executed. Similarly, when the condition fulfillment signal A' is "1", the execution cycle flip-flop 2' becomes "1" and the first and second microprograms are executed in the decode cycle and execution cycle, respectively. 1 command is completed.

On the other hand, the execution cycle flip-flops 2, 2'
The output of is the set input for the decode cycle flip-flops 1 and 1', so the next execution cycle is the decode cycle. This sequence is guaranteed while the condition fulfillment signals A and A' are "1".

When the result of decoding a microinstruction postpones the execution of the instruction due to waiting for data, etc., the condition fulfillment signal A becomes "0" and the wait cycle flip-flop 3 becomes "0" by the outputs of the AND circuits 10 and 11 and the OR circuit 12. 1” and similarly,
When the condition fulfillment signal A' is "0", the wait cycle flip-flop 3' is set to "1" and the next decode cycle is a wait cycle. When the condition fulfillment signals A and A' become "1", the AND circuits 7 and 7' perform an AND operation, and an execution cycle begins.

On the other hand, when the condition fulfillment signal A becomes "1", the outputs of the AND circuits 10 and 11 become "0" and the wait cycle flip-flop 3 is reset to "0". Similarly, when the condition fulfillment signal A' becomes "1", the wait cycle flip-flop 3' is reset to "0".

Here, in the selection circuit SEL, the synchronization signal K is “0”
Therefore, a decode cycle signal B' and an execution cycle signal C' are output.

The above are two microprograms FW1 and FW
This is a case where microprograms FW1 and FW2 are operating independently of each other, but for some reason microprograms FW1 and
At the time when it becomes necessary to synchronize FW2, the microprogram FW1 sets the synchronization signal K to "1", and the selection circuit SEL selects the decode cycle signal B and the execution cycle signal C, while the decode cycle flip-flop 1', the run cycle flip-flop 2' and the wait cycle flip-flop 3' are reset.

Therefore, microprogram W2 executes microinstructions using decode cycle signal B and execution cycle signal C, and
Synchronized to FW1. Micro program FW
2 occurs during the wait cycle, the wait cycle flip-flop 3' is reset by the synchronization signal K, so the wait cycle
D' becomes "0", the wait state is released, and the program is placed under the control of the microprogram FW1 as described above.

As described above, it is possible to synchronize two different microprograms without repeating instructions multiple times.

By adding a synchronization circuit, the information processing device of the present invention can generate two decode cycle signals and an execution cycle signal for synchronization, instead of determining whether or not synchronization is necessary using a microprogram and performing synchronization. Since the signal can be supplied to the microinstruction decoding circuit and microinstruction execution circuit corresponding to each of the two microprograms, synchronization time can be reduced.

That is, the information processing device of the present invention has two different
In order to process two microprograms in parallel, by having two sets of three cycle generation circuits and a synchronization circuit, the effect is that the control circuit of one microprogram can synchronize the control circuit of the other microprogram. There is.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. CC, CC'... Cycle control circuit, SEL... Selection circuit, 1, 1'... Decode cycle flip-flop, 2, 2'... Execution cycle flip-flop, 3, 3'... Wait cycle Flip-flop, 4, 4'...AND circuit, 5, 5'...
OR circuit, 6, 6', 7, 7'...AND circuit,
8, 8'...OR circuit, 9, 9'...Inverter circuit, 10, 10', 11, 11'...AND circuit,
12, 12'...OR circuit, A, A'...condition fulfillment signal, B, B', H...decode cycle signal,
C, C', J... Execution cycle signal, D, D'...
Wait cycle signal, P...clock, K...
Synchronization signal.

Claims (1)

[Claims] 1. A first micro-instruction decoding circuit provided corresponding to a first micro-program consisting of a series of first micro-instructions and for instructing a first micro-instruction decoding circuit to perform decoding in an initial state and after execution of the first micro-instructions. Generates a decode cycle signal, and generates a first wait cycle signal until a first condition fulfillment signal is supplied after decoding the first microinstruction, and generates a first wait cycle signal until the first condition is satisfied after decoding the first microinstruction. a first cycle control circuit that generates a first execution cycle signal that instructs the first microinstruction execution circuit to execute when the signal is supplied; a second microinstruction consisting of a second microinstruction;
A second decode cycle signal is generated after the initial state and the execution of the second microinstruction, and a second decode cycle signal is generated after the second microinstruction is decoded. A second wait cycle signal is generated until a second condition fulfillment signal is supplied.
a second cycle control circuit that generates a second execution cycle signal when the second condition fulfillment signal is supplied after decoding the microinstruction; and a second cycle control circuit that generates a second execution cycle signal when the second condition fulfillment signal is supplied; selecting a cycle signal and generating a third decode cycle signal for instructing a second microinstruction decode circuit to decode by selecting the first decode cycle signal when the synchronization signal is supplied; Selecting the second execution cycle signal when the synchronization signal is not supplied, selecting the first execution cycle signal when the synchronization signal is supplied, and instructing the second microinstruction execution circuit to execute. An information processing device comprising: a synchronization circuit that generates a third execution cycle signal for performing a third execution cycle signal.