JPS6253864B2 - - Google Patents

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a data transfer system between a main storage device and an auxiliary storage device or an input/output device, and particularly relates to a data transfer method between a main storage device and an auxiliary storage device or an input/output device, and in particular, a DMA (Direct Memory Transfer System) between each device.
The present invention relates to an input/output processing method that controls the completion of transfer to the main storage device and padding processing by notifying the completion and abort of the transfer from the DMA controller.

[Conventional technology and problems]

When transferring data between main storage and auxiliary storage or input/output devices, storage media with fixed formats such as sector files, etc.
Unless a hard error or the like is detected, the transfer cannot be completed at any point other than a format break. However, it is not necessarily necessary to prepare data for that format (length) on the main memory, and there is a method that transfers only the actually valid data and then sends out padding data for the rest. is taken. Padding
Although the data is created without accessing the main memory, for example, it may be a fixed value such as all "0", or the data read last from the main memory may be repeatedly used as padding data. Such padding data can occur at any stage of the data transfer path, such as a channel, an input/output controller, an input/output device, etc.

For example, when padding data is generated on the input/output device side, upon receiving a transfer end notification from the channel (or DMA controller), the input/output device will no longer transfer data to or from the main storage device. When writing to the medium, if the specified point (format break) has not been reached, the padding data generated in the input/output device is written up to the specified point and the input/output operation is completed. In this case, there is no need for transfers between the main storage device and the input/output device, which improves processing efficiency, but overall, the hardware increases, and the input/output device side If the system does not allow padding, there is a problem. For example, if the input/output device or input/output control device has blocks or
For example, this is a system in which the transfer amount is notified in units of sectors, and the transfer cannot be terminated midway.

[Purpose of the invention]

The present invention is based on the above considerations, and includes:
The purpose is to provide an input/output processing method that can implement padding even at the channel (or DMA controller) stage.

[Structure of the invention]

To this end, the input/output processing method of the present invention includes a main storage device, a central processing unit, an access controller that accesses the main storage device, interface control with the access controller, and input/output processing based on instructions from the central processing unit. A data processing device that includes an adapter that selects an output device and mediates data transfer, and an input/output controller that requests commands by being activated via the adapter from the central processing unit, analyzes the commands, and controls data transfer. In the system, the access controller has an address register in which a transfer address is set, a byte counter in which the number of transferred bytes is set, and a status register in which a transfer status is set, and also handles transfer requests from the adapter. The address register and byte counter are updated by the number of bytes transferred for each transfer by accessing the main memory in response to The adapter is configured to notify the access controller whether the transfer has ended or there is an error, and when the adapter is notified of the end of the transfer from the access controller, it creates padding data and performs the padding process with the input/output controller. and when the access controller notifies the user that there is an error, the controller is configured to send a message to the input/output controller to terminate the transfer without performing padding processing. It is something.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an example of the configuration of a system to which the present invention is applied, and FIG. 2 is a diagram showing the configuration of one embodiment of the present invention. In the figure, 1 is the main memory, 2 is
CPU (central processing unit), 3 is DMA controller,
4 and 4-1 to 4-3 are adapters, 5-2 is a display workstation, 6 and 6-1 to 6-3 are IO controllers, and 7 is a printer.
Controller, 8 is MT controller, 9 is printer, 10 is magnetic tape device, 11-1 and 11-
2 is the disk controller, 12-1 and 12-
2 is a magnetic disk device, 13 is an SS access controller, 14, 43 and 63 are data buffers, 31 is an address register, and 32 is a byte register.
33 is a status register, 34 is a determination circuit, 41 and 62 are control registers, and 42 and 61 are transfer protocol control units.

In Figure 1, during input/output operations, instructions are sent to the CPU.
2, for example, the IO controller 6-3 and the disk controller 11- via the adapter 4-1.
1 (device controller), and data transfer is performed by DMA controller 3, adapter 4-1,
This is done via the IO controller 6-3 and disk controller 11-1.

FIG. 2 shows the configuration of a specific embodiment of the present invention. This will be explained below with reference to FIG. In FIG. 2, a CPU 2 controls an IO controller 6 and the like via a DMA controller 3 and an adapter 4. For example, for the address register 31 of the DMA controller 3
DMA address settings and byte counter 32
The operation is designated by setting the byte count for the adapter 4 and setting the control register group 41 of the adapter 4. When a command is transmitted from the CPU 2 to the IO controller 6, the IO controller 6 determines whether the command can be executed based on the device status, etc., and if it is a data transfer command such as read/write, it is determined that the command is in the data transfer phase. To notify adapter 4, signal DATA and
Turn on REQ. Adapter 4 signals this
The data is transmitted to the DMA controller 3 using DREQ, and when the signal DACK is returned from the DMA controller 3, the data is transferred via the data bus. DMA
Controller 3 receives signal DREQ from adapter 4
The main storage device 1 is accessed in response to a request from the main storage device 1, and the contents of the address register 31 and byte counter 32 are updated by the number of bytes transferred for each transfer. Then, the determination circuit 34 checks the contents of the status register 33 and byte counter 32, and determines that there is an error using the signal BREAK.
The adapter 4 is notified of the end of the transfer by the signal STOP. In other words, the byte counter 32 indicates the amount of data prepared on the main memory,
The number of transfer bytes remaining is zero (byte counter 32
(0), the DMA controller 3 turns on the signal STOP along with the signal DACK to notify that this is the last transfer of the adapter 4. The adapter 4 controls the interface with the DMA controller 3, selects an input/output device according to instructions from the CPU 2 (turns on the signal SEL), and mediates data transfer. The IO controller 6 requests a command upon activation from the CPU 2 via the adapter 4 (turn off both the signals MSG and DATA and raise the signal REQ), decodes it, and sends the command via the adapter 4 and the DMA controller 3. Controls transfer protocols such as data transfer, data transfer to and from IO devices. Protocol control involves the exchange of messages between the adapter 4 and the IO controller 6. For example, a “command completed” message from IO controller 6 to adapter 4, or an IO message from adapter 4.
The transfer sequence is controlled by, for example, an "abort" message to the controller 6.

Byte counter 3 in DMA controller 3
As mentioned earlier, 2 indicates the amount of data prepared on the main memory, whereas the IO controller 6 is notified of the number of blocks to be processed for input/output (for example, in units of sectors). Even if the byte counter 32 of the DMA controller 3 becomes "0", the signal REQ may be raised.
In such a case, create padding data in adapter 4 and transfer data between adapter 4 and IO controller 6.
Transfer between the adapter 4 and the main storage device 1 continues, but transfer between the adapter 4 and the main storage device 1 is not performed. Processing completion notification to CUP2 is then made at the time when all transfers are completed on the device side.

In addition, if you want to abort the transfer without padding due to an error detected by the DMA controller 3, the signal
Also turn on BREAK. Adapter 4 is a signal
When BREAK is turned on, it turns on the signal ATN without padding. The signal ATN is a signal that notifies the IO controller 6 that there is a message to be sent. In response, the IO controller 6 turns on the signal MSG to indicate that it will receive the message (at this time, the signal DATA is turned on). off) and turn on signal REQ. Then, the adapter 4 places a message on the data bus indicating that an error has been detected and turns on the signal ACK. This causes the transfer to be aborted without padding.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the adapter uses two signals STOP and BREAK from the DMA controller (or channel) to notify the adapter whether the transfer is complete or an error has occurred. If the transfer is completed, the padding process is performed, and if there is an error, the transfer is aborted without performing the padding process, so the CPU is notified faster in the event of an error.
Transition to retry becomes faster. Also, two signals
You can easily control whether padding is performed using STOP and BREAK.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of a system to which the present invention is applied, and FIG. 2 is a diagram showing the configuration of one embodiment of the present invention. 1...Main storage device, 2...CPU (Central Processing Unit),
3...DMA controller, 4 and 4-1 or 4-
3...Adapter, 5-2...Display workstation, 6 and 6-1 or 6-3...IO controller, 7...Printer controller, 8...
MT controller, 9...Printer, 10...Magnetic tape device, 11-1 and 11-2...Disk controller, 12-1 and 12-2...Magnetic disk device, 13...SS access controller, 14,
43 and 63...Data buffer, 31...Address register, 32...Byte counter, 33...
Status register, 34...judgment circuit, 41 and 62...control register group, 42 and 61...
Transfer protocol control unit.

Claims (1)

[Claims] 1 A main storage device, a central processing unit, an access controller that accesses the main storage device, interface control with the access controller, selection of input/output devices and mediation of data transfer based on instructions from the central processing unit, etc. In the data processing system, the access controller includes an adapter that performs data transfer, and an input/output controller that requests commands by activation via the adapter from the central processing unit, analyzes the commands, and controls data transfer. It has an address register in which an address is set, a byte counter in which the number of transferred bytes is set, and a status register in which the transfer status is set, and it accesses the main memory in response to a transfer request from the adapter. The above address register and byte counter are updated by the number of bytes transferred for each transfer, and the above status register and byte counter are checked to notify the above adapter whether rotation has ended or an error has occurred. When the adapter is notified of the end of transfer from the access controller, it creates padding data, performs padding processing with the input/output controller, and receives an error message from the access controller. An input/output processing method characterized in that, when a transfer is notified, a message is sent to the input/output controller to terminate the transfer without performing padding processing.