JPS6253966B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a master-slave flip-flop circuit.

Conventional master-slave flip-flop circuits generally require a large number of components for construction. However, although it is desirable to increase monolithic integration, circuits of this type requiring a large number of elements are at a severe disadvantage in this respect, especially when integrated in large numbers as shift registers. be.

SUMMARY OF THE INVENTION An object of the present invention is to provide a master-slave flip-flop circuit with excellent integration and an extremely small number of elements.

The invention includes two NAND gates each having at least two inputs, the output and one input of which are cross-connected to each other to form a flip-flop, and two multi-emitter transistors each having at least two emitters. the collectors and bases of the transistors are cross-connected to each other to form a flip-flop;
and the collectors are each connected to another input of the NAND gate, the emitters of one of the transistors are connected in common to form a clock input terminal, and the other emitters of the transistors form complementary data input terminals, A master-slave flip-flop circuit is obtained in which the input threshold of the NAND gate is between the collector potential of the flip-flop-connected transistor when it is on, when it is off, and when it is off. It is also possible to obtain a master-slave flip-flop circuit in which the bases of the two multi-emitter transistors described above are connected not directly to the collectors of each other but via resistors.

The present invention will be explained in detail below using the drawings. First, an example of a conventional master-slave flip-flop circuit will be described with reference to FIG. Here, transistors Q ₂ and Q ₇ constitute a master flip-flop. Transistors Q ₁ and Q ₆ are inverters for signal transmission. Transistors Q ₃ , Q ₄ ,
A slave flip-flop is constructed by two NAND circuits consisting of Q ₅ , Q ₈ , Q ₉ , and Q ₁₀ . Furthermore, diodes D ₁ to _{D 3} are provided for level shifting. The operation of this circuit is as follows:
When the clock pulse applied to CLOCK is high, the master flip-flop and slave flip-flop are separated and the slave flip-flop retains its previous state. When the level of the clock pulse decreases and exceeds a certain threshold, the output signal is transmitted to the slave flip-flop via the inverter of transistors Q ₁ and Q ₆ .
If the level of the clock pulse then rises, the slave flip-flop will maintain its current state. As shown in the figure, this circuit is composed of 23 elements in total, including 10 transistors, 3 diodes, and 10 resistors. Although it is technically easy to construct a given circuit with such a large number of elements, high-density integration is desirable to be able to construct a circuit with the same function using as few elements as possible. Currently highly desired. Conventional circuits are disadvantageous in this regard.

Next, one embodiment of the present invention will be described with reference to FIG.

In this embodiment, transistors _Q1 and _Q4 are cross-connected to form a master flip-flop. Diodes D ₁ and D ₂ are used for level shifting. The feature here is that there is no inverter found in conventional examples in the connection between the master flip-flop and slave flip-flop, and as a result, the number of level shifting diodes is reduced by one, and the number of diodes in the master flip-flop is reduced by one. The loop can also be constructed with just 2 transistors and 2 resistors. It can also be seen that the slave flip-flop is also composed of four transistors and two resistors, and is composed of an extremely small number of elements compared to the conventional example.

Its operation will be explained next. The voltage between the base and emitter when the transistor is conductive (ON) is Vf (generally about 0.8V), the voltage between the collector and emitter when it is saturated is φ (about 0.1V), and the input level is high, which is floating. Assume that the low level is φ. First, input Vin-1 is at high level (float), input Vin-2 is at low level (φ), and transistor _Q6 is
Consider when ONQ ₂ is OFF. When the clock pulse is high, the collector level of transistor _Q4 is Vf+2φ. Since the input threshold of the inverter section of the slave flip-flop consisting of transistors Q ₅ and Q ₆ is Vf - φ, transistor Q ₆ continues to be turned on with a margin of 3 φ. Also, regardless of the collector level of transistor Q ₁ being 2Vf + φ, transistor Q ₂ and transistors Q ₆ and Q ₅ are
Since it is ON, there is a margin of Vf - 2φ.
Keeps it off. At this time, even if the level of the input signal is reversed, that is, Vin-1 is a low level (φ)
Even if Vin-2 becomes a high level (float), of course the transistor _Q2 continues to be OFF and the transistor _Q6 continues to be ON. That is, when the clock pulse (CLOCK) is high, the master flip-flop and slave flip-flop are separated.

In the initial state, the clock pulse starts to fall, and when the clock pulse level becomes the same as the emitter level Vf+φ of transistor _Q4 , the transistor
Current begins to flow to the emitter on the clock side of _Q4 . Furthermore, the clock pulse level decreases and Vf
-2φ, the collector level of transistor _Q4 exceeds the threshold value Vf-φ of the inverter of the slave flip-flop, the slave flip-flop is inverted, and transistor _Q6 is turned off.
Then, transistor _Q2 turns on. That is, the master flip-flop and slave flip-flop are in a coupled state. Furthermore, even if the clock pulse becomes completely low level (φ), the base level of transistor Q ₄ is Vf + φ, so transistor Q ₂ continues to be ON with a margin of 2φ, and the contents of the inverted slave flip-flop are not destroyed. do not have. Also, since the collector level of transistor _Q4 is 2φ, transistor _Q1 will not turn on even if the clock becomes completely low level, and transistor _Q6 will not turn on with a margin of V _f -3φ.
Keeps it off. At this time, even if the input signal is inverted, the collector level of transistor Q ₄ is 2φ, so transistor Q ₁ continues to be OFF, and the contents of the slave flip-flop are not destroyed. Next, when the clock pulse rises, the master flip-flop and slave flip-flop become separated. It has been shown above that the master flip-flop circuit can be constructed using a significantly smaller number of elements.
Furthermore, since the level of this circuit is small, it is considered suitable for high-speed processing.

Next, a second embodiment of the present invention will be described with reference to FIG. This is an improved version of the embodiment described above, and is intended to increase the operating margin (2φ) of the ON-side slave inverter when the clock pulse is at a low level. Operates by resistor division by inserting resistors R ₅ and R ₆ between the base of transistor Q ₁ and the collector of transistor Q ₄ and between the base of transistor Q ₄ and the collector of transistor Q ₁ of the master flip-flop, respectively. The aim is to improve margins. In other words, when the clock pulse is at a low level (φ), the transistor
When Q ₄ and Q ₂ are ON, the collector of transistor Q ₁ is no longer at φ + Vf but at a sufficiently high level (φ + Vf + R ₆ /R ₂ + R ₆ (Vcc - φ - 2Vf), so the ON operation margin of transistor Q ₁ is can be enlarged.Also, this does not have any adverse effect on other operations.Even if two resistors are added, the number of elements is still sufficiently small compared to the conventional circuit.

In such a case, the present invention is highly effective because when it is monolithically integrated, a master-slave flip-flop with an extremely small number of elements, which is suitable as a unit circuit of a shift register, can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a master-slave flip-flop circuit used in a conventional shift register. FIG. 2 is a circuit diagram showing a first embodiment of a master-slave flip-flop according to the invention, and FIG. 3 is a circuit diagram showing a second embodiment of the invention. _Q1 to _Q8 : transistors, _D1 to _D3 : diodes, _R1 to _R10 : resistors.

Claims (1)

[Scope of Claims] 1. Two NAND gates having at least two inputs whose output and one input are cross-connected to each other to form a flip-flop, and at least two emitters, the collector and base of which are cross-connected to each other. two multi-emitter transistors, the collectors of each of the multi-emitter transistors are each DC-connected to the other input of the NAND gate, and one emitter of each of the multi-emitter transistors is commonly connected. The other emitter of the multi-emitter transistor is led out as a data input terminal via a level shifting diode, and when the clock input terminal is at a high level, one of the multi-emitter transistors is conductive. A master-slave flip-flop circuit characterized in that the collector potential of the transistor is higher than the input threshold of the NAND gate. 2. The master-slave flip-flop circuit according to claim 1, wherein the bases of the multi-emitter transistors are connected to each other's collectors via resistors.