JPS6254260B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a call progress signal and network identification code receiving circuit for a time division electronic exchange.

Conventionally, in order for an exchange to receive a call progress signal specified by the CCITT (International Telegraph and Telephone Consultative Committee) Recommendation It reported to the signal processing device and received the call progress signal by software. In the CCITT Recommendation X.71 signaling system,
Following the call progress signal, the switch must receive the network identification code. At this time, there are the following two time relationships between the call progress signal and the network identification code. That is, (1) No other signal is inserted between the call progress signal and the network identification code, and the first character of the network identification code, Alphabet No. 5, is inserted immediately after the last character of the call progress signal.
When the 3/11 character appears, (2) a "1" signal of one or more bits is inserted between the call progress signal and the network identification code, and the final character of the call progress signal, a "1" signal of one or more bits, This is a case where signals appear in the order of two or more SYN characters and the international Alphabet No. 5 3/11 character, which is the first character of the network identification code.

In the case of (1) above, a call progress signal receiving circuit using a conventional software system can receive both a call progress signal and a network identification code. However, in the case of (2) above, the network identification code may not be correctly received after receiving the call progress signal. That is, in the case of (2) above, after receiving the call progress signal, it is necessary to detect the SYN character again and reestablish character synchronization. However, the software cannot recognize whether the above case (1) or the above case (2) is occurring immediately after receiving the call progress signal, and furthermore, the next character is the International Alphabet 3/11 character. It can only be recognized by determining whether or not it is. Therefore, it is necessary for software to perform this recognition process and then instruct the character synchronization establishment circuit to resynchronize the character.
Therefore, if the software takes a long time to perform this recognition process, the resynchronization instruction will be delayed, and by the time the character synchronization establishment circuit executes character resynchronization, the SYN pattern cannot be received. have Furthermore, if software performs this recognition processing, it has the disadvantage of reducing the software processing capacity.

The present invention improves this point, and even if the time relationship between the call progress signal and the network identification code is in (1) or (2) above, the call progress signal and network identification code can be correctly processed without imposing a processing load on the software. The object is to provide a circuit that can receive an identification code.

The present invention provides a time-sharing electronic exchange in which a synchronous signal receiving circuit includes a character synchronization establishing circuit, and the character receiving circuit is effective only when character synchronization is established. After receiving 10 characters, the next consecutive character (first character) and the next consecutive character (second character) are received as a call progress signal, and then the next character (third character) is received. If the character is not the 3/11 character of International Alphabet No. 5, the character synchronization establishment circuit is reset and character resynchronization is performed.

An embodiment of the present invention will be described based on the drawings.
FIG. 1 is a circuit diagram of a main part of an exchange according to an embodiment of the present invention. Receiving line 1 is character synchronization establishment circuit 2
and the character receiving circuit 3, respectively. The character synchronization establishment signal 5 and the control information line 6 from the character synchronization establishment circuit 2 are
It is connected to the character receiving circuit 3. A character reception signal line 7 from the character reception circuit 3 is led to a clock terminal CK of a counter circuit 8 and one input terminal of an AND circuit 9. Further, the data line 10 from this character receiving circuit 3 is connected to the International Alphabet No. 5 3/10 character detection circuit (hereinafter referred to as "3/10 character detection circuit") 11, the International Alphabet No. 5
It is connected to a 3/11 character detection circuit (hereinafter referred to as "3/11 character detection circuit") 12 and a central processing unit 13, respectively.

The output of this 3/10 character detection circuit 11 is led to the starting terminal TR of the counter circuit 8. The output of this counter circuit 8 is led to an input terminal of an AND circuit 15. The inverted output of the 3/11 character detection circuit 12 is led to the other input terminal of the AND circuit 15. The output of this AND circuit 15 is inverted and guided to the other input terminal of the AND circuit 9. Further, the output of this AND circuit 15 is led to one input terminal of an OR circuit 16. The other input terminals of this OR circuit 16 include
The output of the central processing unit 13 is guided.

The output of this OR circuit 16 is led to the reset terminal of the character synchronization establishing circuit 2. Further, the output of the AND circuit 9 is output from the central processing unit 13.
guided by.

FIG. 2 is a diagram showing the time relationship between the call progress signal received by the circuit shown in FIG. 1 and the network identification code. In FIG. 2a, no other signal is inserted between the call progress signal A and the network identification code B, and the first character of the network identification code B, the first character of the call progress signal A, is immediately followed by the International Alphabet No. The case where the 3/11 character of 5 appears is shown. This is the case of (1) above.

FIG. 2b shows a case where a "1" signal of one or more bits is inserted between the call progress signal A and the network identification code B. FIG. This is the case in (2) above.

Note that "SYN" in FIG. 2 indicates a synchronous signal (synchronous idle).

With such a circuit configuration, received data from the receiving line 1 is guided to the character synchronization establishment circuit 2 and the character receiving circuit 3. Character synchronization establishment circuit 2 detects a SYN pattern from the received data and establishes character synchronization on the receiving line. When character synchronization is established, an output is given to the character synchronization establishment signal line 5, and the character receiving circuit 3 is controlled by the control information shown on the control information line 6.
Reports that character synchronization has been established. Once the character synchronization establishment circuit establishes synchronization, it stops the SYN pattern detection operation until it is reset next time by the reset signal from the OR circuit 16. The character receiving circuit 3 assembles a character based on the control information shown on the control information line 6 when there is an input signal from the character synchronization establishment signal line 5. When the character is assembled, an output is sent to the character reception signal line 7, and the assembled character data is placed on the data line 10. When the 3/11 character detection circuit 11 detects a 3/10 character from the sent character data, this detection output is given to the counter circuit 8, and the counter circuit 8 is activated. When this counter circuit 8 is activated, its contents are cleared to "0", and then the clock terminal
Each time there is an input signal to CK, it advances by 1, and when the counter value reaches "3", it sends out the counter output,
When there is a next clock input, the counter value is set to "4" and the operation stops. Therefore, if the 3/11 character detection circuit 12 does not detect the 3/11 character at the time when the 3/10 character detection circuit 11 receives the 3/10 character and receives the third character, the AND circuit 15 The gate output of is given to the OR circuit 16.

The character synchronization establishment circuit 2 is reset by the gate output of the OR circuit 16. For this reason,
Immediately, the character synchronization establishment circuit 2 performs a SYN pattern detection operation and receives a network identification code. Therefore, a signal sequence as shown in FIG. 2b is accurately received. Also, AND circuit 1
When the gate output of 5 is sent out, the central controller 13
In order to stop the character reception report, the AND circuit 9 is closed to report that no character has been received.

As explained above, according to the present invention, after receiving the 3/10 character of International Alphabet No. 5,
The first and second characters following this are received as call progress signals, and the third character that follows is received, which is the international Alphabet No.
If the character is not 3/11 of 5, the circuit configuration is such that the character is immediately resynchronized.

Therefore, call progress signals and network identification codes can be accurately received. Furthermore, since this is done by hardware, the burden on the software can be reduced and the software processing efficiency can be improved, which is an excellent effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the main parts of an embodiment of the present invention.
FIG. 2 is a diagram showing the time relationship between the call progress signal and the network identification code in the above embodiment. 1...Reception line, 2...Character synchronization establishment circuit,
3... Character receiving circuit, 5... Character synchronization establishment signal line, 6... Control information line, 7... Character receiving signal line, 8... Counter circuit, 9, 15... AND circuit, 10... Data line, 11... 3/10 character Detection circuit, 12...3/11 character detection circuit, 13...Central processing unit, 16...OR circuit.

Claims (1)

[Claims] 1. A character synchronization establishment circuit that establishes character synchronization between a reception line and an exchange by receiving a synchronization signal code, and a character reception circuit that receives characters on the reception line, and when the character reception circuit establishes character synchronization. A 3/10 character detection circuit that detects the 3/10 character of International Alphabet No. 5 and a 3/11 character of International Alphabet No. 5 in the signal reception method of the time division electronic exchange configured to operate. do3/
After the 11 character detection circuit and the above 3/10 character detection circuit detect the 3/10 character, the next first
The third character is received as a call progress signal, and the next second character is received as a call progress signal.
A signal receiving system for a time division electronic exchange, comprising: a circuit for sending a reset signal to the character synchronization establishing circuit when the 3/11th character is not detected as a 3/11 character by the 3/11 character detection circuit.