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JPS6254277B2 - - Google Patents
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JPS6254277B2 - - Google Patents

Info

Publication number
JPS6254277B2
JPS6254277B2 JP56123890A JP12389081A JPS6254277B2 JP S6254277 B2 JPS6254277 B2 JP S6254277B2 JP 56123890 A JP56123890 A JP 56123890A JP 12389081 A JP12389081 A JP 12389081A JP S6254277 B2 JPS6254277 B2 JP S6254277B2
Authority
JP
Japan
Prior art keywords
input
ctr
count value
waveform
dial pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56123890A
Other languages
Japanese (ja)
Other versions
JPS5825791A (en
Inventor
Akira Ishizawa
Kazuo Hamasato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56123890A priority Critical patent/JPS5825791A/en
Publication of JPS5825791A publication Critical patent/JPS5825791A/en
Publication of JPS6254277B2 publication Critical patent/JPS6254277B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q1/00Details of selecting apparatus or arrangements
    • H04Q1/18Electrical details
    • H04Q1/30Signalling arrangements; Manipulation of signalling currents
    • H04Q1/32Signalling arrangements; Manipulation of signalling currents using trains of DC pulses
    • H04Q1/36Pulse-correcting arrangements, e.g. for reducing effects due to interference

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Manipulation Of Pulses (AREA)

Description

【発明の詳細な説明】 本発明は交換装置において、端末より送られて
きたダイヤルパルスの波形を整形する方式に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system for shaping the waveform of a dial pulse sent from a terminal in a switching device.

従来のダイヤルパルス波形整形方式は一般に継
電器を用いる方式であつた。該方式では、継電器
の動作遅延時間と復旧遅延時間の差による波形歪
を考慮して、整形後の波形がデユーテイ50%にな
るように電話機のダイヤルパルス信号をデユーテ
イ30%程度で送出していた。この種の方式では、
継電器を用いていることから小形化できない欠点
があつた。
Conventional dial pulse waveform shaping methods generally use relays. In this method, the telephone dial pulse signal was sent out at a duty rate of approximately 30% so that the waveform after shaping would have a duty of 50%, taking into consideration the waveform distortion caused by the difference between the relay's operation delay time and recovery delay time. . In this kind of method,
Since it uses a relay, it has the disadvantage that it cannot be made smaller.

これに対して電子回路で同様の機能を実現する
試みが幾つかなされているが(例えば昭和55年度
電子通信学会総合全国大会論文集、論文番号
397、臼田他「デイジタル交換機用加入者回路の
IC化」)、大容量のコンデンサが必要で、かつ所
望の時間精度を得るためにはコンデンサおよび抵
抗値に高精度なものが必要となり、集積回路に取
り込むことができないこと、及び入力波形と整形
後の出力波形とで、デユーテイを変えるため、充
放電時間を個々に設定する時定数変更手段が必要
となり、回路が複雑化すること等の欠点があつ
た。
In response, several attempts have been made to realize similar functions using electronic circuits (for example, Proceedings of the 1985 National Conference of the Institute of Electronics and Communication Engineers, Paper No.
397, Usuda et al. “Subscriber circuit for digital exchange
``IC''), a large capacitor is required, and in order to obtain the desired time accuracy, a highly accurate capacitor and resistance value is required, which cannot be incorporated into an integrated circuit, and the input waveform and shaping In order to change the duty depending on the subsequent output waveform, a time constant changing means for individually setting the charging/discharging time is required, which has the disadvantage of complicating the circuit.

本発明はこれらの欠点を除去するために、通話
線の電流の有無によるアツプダウンカウンタを制
御し、該アツプダウンカウンタの計数値が所定の
値、例えば一定値又は零に達したことをもつて通
話線の電流の有無を判定するようにし、かつ該カ
ウンタを計数する場合、計数値の増加用と減少用
に別なクロツクを用いるようにしたもので、それ
により、入力波形と整形後の出力波形のデユーテ
イが異なる場合にも柔軟に対応でき、しかも集積
回路に向き、雑音やチヤツタに影響されないダイ
ヤルパルス波形整形方式を提供するものである。
以下、本発明を図面について詳細に説明する。
In order to eliminate these drawbacks, the present invention controls an up-down counter depending on the presence or absence of current in the communication line, and controls the up-down counter when the counted value of the up-down counter reaches a predetermined value, for example, a constant value or zero. When determining the presence or absence of current in the telephone line and counting the counter, separate clocks are used for incrementing and decrementing the count value, thereby making it possible to distinguish between the input waveform and the output after shaping. The present invention provides a dial pulse waveform shaping method that can flexibly handle cases where waveform duties differ, is suitable for integrated circuits, and is not affected by noise or chatter.
Hereinafter, the present invention will be explained in detail with reference to the drawings.

第1図は本発明の一実施例であつて、CNVは
本発明によるダイヤルパルス波形整形回路、
TELは電話機端未のダイヤルの接点、LA,LB
は通話線路、A,Bは交換局のの出端子、DET
は電流検出手段を示す。ダイヤルパルス波形整形
回路CNVのCTRはアツプダウンカウンタであつ
て、Uはアツプ制御入力、Dはダウン制御入力、
Cはクロツク入力、Qoはnカウント出力、ALL
“0”はすべて零の場合の出力端子である。又、
FFはフリツプフロツプであつて、Sはセツト入
力、Rはリセツト入力、Qはフリツプフロツプ出
力である。AND1、AND2は禁止端子付アンド
回路、INVは反転回路、ORはオア回路である。
SCN IN、SCN OUT、およびCLK1、CLK2は
ダイヤルパルス波形整形回路CNVの入力あるい
は出力端子であつて、SCN INはダイヤルパルス
入力端子、SCN OUTは整形出力端子、CLK1は
計数値の増加用クロツク信号入力端子、CLK2
は計数値の減少用クロツク信号入力端子である。
FIG. 1 shows an embodiment of the present invention, in which CNV is a dial pulse waveform shaping circuit according to the present invention;
TEL is the contact point of the dial at the end of the telephone, L A , L B
is the communication line, A and B are the output terminals of the switching center, DET
indicates current detection means. CTR of the dial pulse waveform shaping circuit CNV is an up-down counter, U is an up control input, D is a down control input,
C is clock input, Q o is n count output, ALL
“0” is an output terminal when all are zero. or,
FF is a flip-flop, S is a set input, R is a reset input, and Q is a flip-flop output. AND1 and AND2 are AND circuits with inhibit terminals, INV is an inverting circuit, and OR is an OR circuit.
SCN IN, SCN OUT, CLK1, and CLK2 are the input or output terminals of the dial pulse waveform shaping circuit CNV, where SCN IN is the dial pulse input terminal, SCN OUT is the shaping output terminal, and CLK1 is the clock signal for increasing the count value. Input terminal, CLK2
is a clock signal input terminal for decreasing the count value.

第2図は第1図の動作を説明するためのタイミ
ング図で、第1図と同種記号は該当部分の波形を
表わしている。第2図において、aの波形部分は
電話機端末のダイヤル接点のチヤツタを表わし、
bの波形部分は雑音による不用パルスを表わし、
cの波形部分は雑音による波形割れを表わしてい
る。SCN INは通話線に流れる電流の電流検出手
段DETでの検出出力波形、CTR、FF後にカツコ
を付して記した記号はアツプダウンカウンタ
CTR、フリツプフロツプFFの各端子の波形、
(CTR)はアツプダウンカウンタCTRの計数値で
ある。
FIG. 2 is a timing diagram for explaining the operation of FIG. 1, and symbols similar to those in FIG. 1 represent waveforms of corresponding portions. In FIG. 2, the waveform part a represents the chatter of the dial contact of the telephone terminal,
The waveform part b represents unnecessary pulses due to noise,
The waveform portion c represents waveform cracking due to noise. SCN IN is the detection output waveform of the current detecting means DET of the current flowing in the communication line, and the symbol written with a bracket after CTR and FF is an up-down counter.
Waveforms of each terminal of CTR and flip-flop FF,
(CTR) is the count value of the up-down counter CTR.

次に第2図を参照して第1図の動作を説明す
る。電話機端未のダイヤルの接点TELが断続動
作することにより、電源Eによつて通話線路L
A,LBに断続電流が流れる。該断続電流を電流検
出手段DETが検出し、論理信号レベルに変換す
るが、その波形は第2図のSCN INで示したよう
にチヤツタ等を含んでおり、それがダイヤルパル
ス波形整形回路CNVに入力される。該入力信号
SCN INの“1”、すなわち通話線路LA,LB
電流が流れている場合にアツプダウンカウンタ
CTRはアツプ側に制御され、該入力信号SCN IN
の“0”、すなわち通話線路LA,LBに電流が流
れていない場合にアツプダウンカウンタCTRは
INVを通してダウン側に制御される。アンド回路
AND1の第1入力は入力信号SCN IN、第2入力
はクロツク信号CLK1、禁止入力はアツプダウ
ンカウンタCTRの計数値が一定値Qoになつた場
合の信号を入力し、アンド回路AND2の第1の
入力は入力信号SCN INの反転信号、第2入力は
クロツク信号CLK2、禁止入力はアツプダウン
カウンタCTRの計数値が零になつた場合の信号
を入力する。アンド回路AND1,AND2の出力
はオア回路ORにより論理和されてアツプダウン
カウンタCTRのクロツク入力信号とし、アツプ
ダウンカウンタCTRの計数値が一定値に達した
ときにフリツプフロツプFFをセツトし、該CTR
の計数値が零に達したときにフリツプフロツプ
FFをリセツトする。そして、該フリツプフロツ
プFFのQ出力を波形整形出力SCN OUTとす
る。
Next, the operation shown in FIG. 1 will be explained with reference to FIG. By intermittent operation of the dial contact TEL at the end of the telephone, the telephone line L is connected by the power supply E.
Intermittent current flows through A and LB. The intermittent current is detected by the current detection means DET and converted to a logic signal level, but the waveform includes chatter etc. as shown by SCN IN in Fig. 2, and is sent to the dial pulse waveform shaping circuit CNV. is input. The input signal
When SCN IN is “1”, that is, current is flowing through the communication lines L A and L B , the up-down counter
CTR is controlled to the up side, and the input signal SCN IN
is “0”, that is, when no current flows in the communication lines L A and L B , the up-down counter CTR is
Controlled down side through INV. and circuit
The first input of AND1 is the input signal SCN IN, the second input is the clock signal CLK1, the inhibit input is the signal when the count value of the up-down counter CTR reaches a constant value Q o , and the first input of the AND circuit AND2 is input. The input is an inverted signal of the input signal SCN IN, the second input is the clock signal CLK2, and the inhibit input is a signal when the count value of the up-down counter CTR becomes zero. The outputs of the AND circuits AND1 and AND2 are logically summed by the OR circuit and used as a clock input signal for the up-down counter CTR. When the count value of the up-down counter CTR reaches a certain value, the flip-flop FF is set and the clock input signal for the up-down counter CTR is set.
Flip-flop occurs when the count value of reaches zero.
Reset FF. Then, the Q output of the flip-flop FF is set as the waveform shaping output SCN OUT.

今、入力信号SCN INが“0”の場合、CTR
(U)は“0”になり、かつCTR(D)は“1”となる
ため、CTRはダウン制御になる。この場合、
AND1の第1入力、即ちSCN INは“0”とな
り、該AND1の第2入力のクロツク信号CLK1
は出力されず、一方、AND2の第1入力、即ち
SCN INの反転信号は“1”となり、該AND2の
禁止入力はCTRの計数値が零でないため“0”
であり、該AND2の第2入力のクロツク信号
CLK2はOR回路を通してCTRのC端子に入力さ
れ、CTRはクロツク信号CLK2によつて計数値
を減少方向に計数する。このようにして、CTR
の計数値が零になるまで計数され、該CTRの計
数値が零に達すると、そのALL“0”端子が
“1”となり、その結果、前記AND2の禁止入力
は“1”となるため、該AND2の第2入力のク
ロツク信号CLK2は出力されず、CTRは計数動
作を停止し、かつFFのR端子は“1”になつて
該FFはリセツトされ、該FFの出力、即ち波形整
形出力SCN OUTは“0”になる。この状態は入
力信号SCN INが“1”になるまで維持される。
Now, if the input signal SCN IN is “0”, CTR
Since (U) becomes "0" and CTR (D) becomes "1", CTR is controlled down. in this case,
The first input of AND1, that is, SCN IN becomes "0", and the clock signal CLK1 of the second input of AND1 becomes "0".
is not output, while the first input of AND2, i.e.
The inverted signal of SCN IN becomes “1”, and the inhibit input of AND2 becomes “0” because the count value of CTR is not zero.
and the clock signal of the second input of AND2
CLK2 is inputted to the C terminal of CTR through an OR circuit, and CTR counts the count value in a decreasing direction by clock signal CLK2. In this way, CTR
is counted until the count value of the CTR reaches zero, and when the count value of the CTR reaches zero, the ALL “0” terminal becomes “1”, and as a result, the inhibition input of the AND2 becomes “1”. The clock signal CLK2 of the second input of the AND2 is not output, the CTR stops the counting operation, and the R terminal of the FF becomes "1", the FF is reset, and the output of the FF, that is, the waveform shaped output. SCN OUT becomes “0”. This state is maintained until the input signal SCN IN becomes "1".

ダイヤルパルス波形整形回路CNVの入力信号
SCN INが“1”に変形した場合は、CTR(U)は
“1”になり、かつCTR(D)は“0”となり、CTR
はアツプ制御になる。この場合、AND2の第1
入力SCN INの反転信号は“0”となり、該AND
2の第2入力のクロツク信号CLK2は出力され
ず、一方、AND1の第1入力SCN INは“1”と
なり、かつ該AND1の禁止入力はCTRの計数値
が一定値に達していないため“0”であり、該
AND1の第2入力のクロツク信号CLK1はOR回
路を通してCTRのC端子に入力され、CTRはク
ロツク信号CLK1によつて計数値を増加方向に
計数する。該CTRは計数値が一定値Qoに達する
までクロツク信号CLK1を計数し、該CTRの計
数値が一定値に達すると、そのQo出力が“1”
になり、その結果、前記AND1の禁止入力は
“1”となるため、該AND1の第2入力のクロツ
ク信号CLK1は出力されず、CTRは計数動作を
停止し、かつFFのS端子は“1”になつて該FF
はセツトされ、該FFの出力、すなわち波形整形
出力SCN OUTは“1”になる。この状態は入力
信号SCN INが“0”になるまで維持される。
Input signal of dial pulse waveform shaping circuit CNV
When SCN IN changes to “1”, CTR(U) becomes “1” and CTR(D) becomes “0”, and CTR
becomes up control. In this case, the first of AND2
The inverted signal of input SCN IN becomes “0”, and the corresponding AND
The clock signal CLK2 of the second input of AND1 is not output, while the first input SCN IN of AND1 is "1", and the inhibit input of AND1 is "0" because the count value of CTR has not reached a certain value. ” and applicable
The clock signal CLK1 of the second input of AND1 is inputted to the C terminal of CTR through an OR circuit, and CTR counts the count value in an increasing direction by the clock signal CLK1. The CTR counts the clock signal CLK1 until the count value reaches a constant value Qo , and when the count value of the CTR reaches the constant value, its Qo output becomes “1”.
As a result, the inhibit input of the AND1 becomes "1", so the clock signal CLK1 of the second input of the AND1 is not output, the CTR stops counting, and the S terminal of the FF becomes "1". ” became the FF
is set, and the output of the FF, that is, the waveform shaping output SCN OUT becomes "1". This state is maintained until the input signal SCN IN becomes "0".

第1図の構成によれば、CTRの計数値の増加
および減少を行うためのクロツクを増加用クロツ
クCLK1と減少用クロツクCLK2とに分けたゝ
め、CTRの計数値の増加時間及び減少時間を
個々に設定することができる。従つて、入力波形
と整形後の出力波形とでデユーテイが異なる場合
に柔軟に対応することができる。また、通話線路
A,LBに雑音が誘導した場合に生じる雑音パル
スb又は電話機のダイヤル接点TELのチヤツタ
によつて生じる不用パルスaあるいは波形割れc
に対して、通話電流の有無のどちらかに発生頻度
ないし継続時間がかたよつた場合、発生頻度ない
し継続時間の多い動作状態のカウンタが所定の値
に達するまでの時間を長くする。すなわちクロツ
クの周期を長くすることによつて、不用パルス、
波形割れの場合の不用に対する保護作用を任意に
設定することができ、動作が安定なダイヤルパル
スの波形整形を行うことができる。
According to the configuration shown in FIG. 1, the clock for increasing and decreasing the CTR count value is divided into an increase clock CLK1 and a decrease clock CLK2, so that the increase time and decrease time of the CTR count value are Can be set individually. Therefore, it is possible to flexibly deal with the case where the duty is different between the input waveform and the output waveform after shaping. In addition, noise pulses b that occur when noise is induced in the communication lines L A and L B , or unnecessary pulses a or waveform cracks c that occur due to the chatter of the telephone dial contact TEL.
On the other hand, if the frequency of occurrence or duration varies depending on whether the communication current is present or not, the time required for the counter of the operating state where the occurrence frequency or duration is high to reach a predetermined value is lengthened. In other words, by lengthening the clock period, unnecessary pulses,
The protective effect against disuse in the case of waveform cracking can be set arbitrarily, and the waveform shaping of dial pulses with stable operation can be performed.

以上の説明において、アツプダウンカウンタ
CTRの内部構成には言及しなかつたが、その構
成法については周知であり、更にアンド回路
AND1、AND2、反転回路INV等はアツプダウ
ンカウンタCTRを構成するゲート回路等に併合
することも可能であり、本発明はその構成により
制限されるものではない。またフリツプフロツプ
FFをリセツトする際のアツプダウンカウンタ
CTRの計数値については“0”の場合を例示し
たが、これに限らず、Qoよりも小さい値なる他
の値でもよい。
In the above explanation, the up-down counter
Although I did not mention the internal configuration of the CTR, its configuration method is well known, and the AND circuit
AND1, AND2, the inverting circuit INV, etc. can be combined with the gate circuit etc. constituting the up-down counter CTR, and the present invention is not limited by their configuration. Also flipflop
Up-down counter when resetting FF
Although the CTR count value is "0" as an example, it is not limited to this, and may be any other value smaller than Qo .

以上説明したように、本発明は、大容量コンデ
ンサ、高精度抵抗を用いることなく、しかもデイ
ジタル回路で構成したため、集積回路に好適であ
り、小形で経済的で高精度なダイヤルパルス波形
整形回路を提供できる利点があり、更に、アツプ
ダウンカウンタを計数する場合、計数値の増加用
と減少用に別なクロツクを用いたため、入力波形
と整形後の出力波形とでデユーテイが異なる場合
に柔軟に対応でき、かつ雑音、チヤツタによる不
用パルス、波形割れを取り除くことができる利点
もある。
As explained above, the present invention does not use large capacity capacitors or high-precision resistors, and is constructed with a digital circuit, so it is suitable for integrated circuits and provides a compact, economical, and highly accurate dial pulse waveform shaping circuit. Moreover, when counting the up-down counter, separate clocks are used for incrementing and decrementing the count value, so it can flexibly handle cases where the duty is different between the input waveform and the output waveform after shaping. It also has the advantage of eliminating noise, unnecessary pulses due to chatter, and waveform distortion.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す図、第2図は
第1図の動作を説明するためのタイミング図であ
る。 TEL…電話機端末のダイヤル接点、LA,LB
…通話線路、A,B…交換局の出端子、DET…
電流検出手段、E…直流電線、CNV…ダイヤル
パルス波形整形回路、CTR…アツプダウンカウ
ンタ、FF…フリツプフロツプ、INV…反転回
路、AND1,AND2…禁止入力付アンド回路、
OR…オア回路、SCN IN…波形整用回路入力信
号入力、CLK1…加算用クロツク入力、CLK2
…減算用クロツク入力。
FIG. 1 is a diagram showing one embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of FIG. 1. TEL…Dial contact of telephone terminal, L A , L B
...Talking line, A, B...Exchange terminal, DET...
Current detection means, E...DC wire, CNV...dial pulse waveform shaping circuit, CTR...up-down counter, FF...flip-flop, INV...inverting circuit, AND1, AND2...AND circuit with inhibit input,
OR...OR circuit, SCN IN...Waveform shaping circuit input signal input, CLK1...Addition clock input, CLK2
...Clock input for subtraction.

Claims (1)

【特許請求の範囲】[Claims] 1 電話機から通話線を経由して送られるダイヤ
ルパルス信号を入力し、該ダイヤルパルス信号と
異なるデユーテイを持つ出力信号に整形するダイ
ヤルパルスの波形整形方式において、計数値が増
加する場合と減少する場合で各々異つたクロツク
を用いるアツプダウンカウンタ回路を備え、前記
通話線に流れる断続電流信号の有無により、前記
カウンタ回路の計数値が増加あるいは減少する方
向に切換えてクロツクを計数し、前記計数値が予
め定めた第1の値に達したときをもつて通話線に
電流が有りとし、第2の値に達したときをもつて
通話線に電流が無しとすることを特徴とするダイ
ヤルパルスの波形整形方式。
1 In a dial pulse waveform shaping method that inputs a dial pulse signal sent from a telephone via a telephone line and shapes it into an output signal with a duty different from that of the dial pulse signal, cases in which the count value increases and cases in which it decreases The up-down counter circuits each use a different clock, and depending on the presence or absence of an intermittent current signal flowing through the communication line, the count value of the counter circuit is switched in the direction of increasing or decreasing to count the clocks, and the count value is A dial pulse waveform characterized in that when a predetermined first value is reached, a current is present in the telephone line, and when a second value is reached, there is no current in the telephone line. Plastic surgery method.
JP56123890A 1981-08-07 1981-08-07 Waveform shaping system for dial pulse Granted JPS5825791A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56123890A JPS5825791A (en) 1981-08-07 1981-08-07 Waveform shaping system for dial pulse

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56123890A JPS5825791A (en) 1981-08-07 1981-08-07 Waveform shaping system for dial pulse

Publications (2)

Publication Number Publication Date
JPS5825791A JPS5825791A (en) 1983-02-16
JPS6254277B2 true JPS6254277B2 (en) 1987-11-13

Family

ID=14871880

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56123890A Granted JPS5825791A (en) 1981-08-07 1981-08-07 Waveform shaping system for dial pulse

Country Status (1)

Country Link
JP (1) JPS5825791A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008136085A (en) * 2006-11-29 2008-06-12 Renesas Technology Corp Toggle detection circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5227344A (en) * 1975-08-27 1977-03-01 Oki Electric Ind Co Ltd Code integrating circuit

Also Published As

Publication number Publication date
JPS5825791A (en) 1983-02-16

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