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JPS625482B2 - - Google Patents
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JPS625482B2 - - Google Patents

Info

Publication number
JPS625482B2
JPS625482B2 JP3187880A JP3187880A JPS625482B2 JP S625482 B2 JPS625482 B2 JP S625482B2 JP 3187880 A JP3187880 A JP 3187880A JP 3187880 A JP3187880 A JP 3187880A JP S625482 B2 JPS625482 B2 JP S625482B2
Authority
JP
Japan
Prior art keywords
adhesive
layer
adhesive sheet
conductors
multiple layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP3187880A
Other languages
Japanese (ja)
Other versions
JPS56128001A (en
Inventor
Teruo Furuya
Akira Hasegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3187880A priority Critical patent/JPS56128001A/en
Publication of JPS56128001A publication Critical patent/JPS56128001A/en
Publication of JPS625482B2 publication Critical patent/JPS625482B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P3/00Waveguides; Transmission lines of the waveguide type
    • H01P3/02Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
    • H01P3/08Microstrips; Strip lines
    • H01P3/088Stacked transmission lines

Landscapes

  • Waveguides (AREA)

Description

【発明の詳細な説明】 この発明は各層間が電気的に接続されたトリプ
レートストリツプラインの多層一体化方法に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for integrating multiple layers of triple-plate strip lines in which each layer is electrically connected.

ここで、トリプレートストリツプライン部には
各種機能を有するマイクロ波回路が形成されてい
るものとする。
Here, it is assumed that a microwave circuit having various functions is formed in the triplate stripline section.

第1図は従来のトリプレートストリツプライン
の多層一体化方法を示す概略断面図であり、図
中、1は圧力・熱、2a,2b,2c,2dは地
導体、3a,3b,3c,3dは誘電体基板、4
a,4bは内部導体、5は結合孔、6は接着シー
ト(あるいは接着剤)である。
FIG. 1 is a schematic cross-sectional view showing a conventional method for integrating multiple layers of a triple-plate stripline. 3d is a dielectric substrate, 4
a and 4b are internal conductors, 5 is a coupling hole, and 6 is an adhesive sheet (or adhesive).

この従来のトリプレートストリツプラインの多
層一体化方法について以下説明する。
This conventional method for integrating multiple layers of triplate strip lines will be described below.

誘電体基板3a,3b,3c,3d間及び各層
間すなわち地導体2b,2c間に接着シート6を
はさみ込み、これら全体に圧力・熱1を加えてト
リプレートストリツプラインの多層一体化を計つ
ていた。
An adhesive sheet 6 is sandwiched between the dielectric substrates 3a, 3b, 3c, and 3d and between each layer, that is, between the ground conductors 2b and 2c, and pressure and heat 1 are applied to the entirety to integrate the multi-layered triplate strip line. It was on.

しかし、この一体化方法の欠点は各層間の電気
的な接続が結合孔5を介して十分になされない事
であり、この種の不具合が製造過程で多発してい
る事であつた。
However, a drawback of this integration method is that the electrical connections between the layers cannot be made sufficiently through the coupling holes 5, and this type of problem frequently occurs during the manufacturing process.

理由は結合孔5を形成する地導体2b,2c間
及び内部導体4a,4b間の接続が圧着だけであ
るため、接着シート6及び結合孔5を形成する地
導体2b,2c、内部導体4a,4bの厚み誤差
により地導体2b,2c間及び内部導体4a,4
b間の電気的接続が十分に成されなかつたためで
ある。
The reason is that the connection between the ground conductors 2b, 2c forming the bonding hole 5 and between the internal conductors 4a, 4b is only by crimping. 4b between the ground conductors 2b and 2c and between the internal conductors 4a and 4.
This is because the electrical connection between b and b was not sufficiently established.

この発明は前述の従来の欠点を除去したもの
で、その目的は製造過程で生じる不具合の軽減に
ある。
This invention eliminates the above-mentioned drawbacks of the prior art, and its purpose is to reduce the problems that occur during the manufacturing process.

第2図はこの発明の一実施例の各層間が電気的
に接続されたトリプレートストリツプラインの多
層一体化方法を示す概略断面図であり、図中、1
は圧力・熱、、2a,2c,2dは地導体、3
a,3b,3c,3dは誘電体基板、4a,4b
は内部導体、5は結合孔、6は接着シート(ある
いは接着剤)、7は予備ハンダである。
FIG. 2 is a schematic cross-sectional view showing a method for integrating multiple layers of a triple plate strip line in which each layer is electrically connected according to an embodiment of the present invention.
is pressure/heat, 2a, 2c, 2d are ground conductors, 3
a, 3b, 3c, 3d are dielectric substrates, 4a, 4b
5 is an internal conductor, 5 is a bonding hole, 6 is an adhesive sheet (or adhesive), and 7 is preliminary solder.

以下、この発明によるトリプレートストリツプ
ラインの多層一体化方法について詳細に説明す
る。
Hereinafter, the method for integrating multiple layers of triple plate strip lines according to the present invention will be explained in detail.

各層間の地導体一枚を接着シート6で置換する
と共に誘電体基板3a,3b,3c,3d間にも
接着シート6をはさみ込み、併せて、結合孔5を
形成する内部導体4a,4b部分に予備ハンダ7
をし、これら全体を圧力・熱1を加えてトリプレ
ートストリツプラインの多層一体化を実現してい
る。この一体化方法によると各層間で地導体2c
を共用しているため、従来発生していた地導体間
の電気的接続の問題が除去され、併せて結合孔5
を形成する内部導体4a,4b間はハンダ付が成
されているため各層間の電気的接続は十分に成さ
れ、製造過程で発生していたトリプレートストリ
ツプラインの多層一体化による不具合が大巾に軽
減できる。
One ground conductor between each layer is replaced with an adhesive sheet 6, and the adhesive sheet 6 is also inserted between the dielectric substrates 3a, 3b, 3c, and 3d, and the inner conductors 4a and 4b portions forming the bonding holes 5 are also inserted. Spare solder 7
Then, by applying pressure and heat to the entire structure, multi-layer integration of the triple plate strip line was realized. According to this integration method, there is a ground conductor 2c between each layer.
Since the joint hole 5 is shared, the problem of electrical connection between the ground conductors that conventionally occurred is eliminated, and at the same time, the connection hole 5
Since the internal conductors 4a and 4b forming the circuit are soldered, the electrical connection between each layer is sufficient, and the problems caused by the multilayer integration of the triple plate strip line that occurred during the manufacturing process have been avoided. It can be reduced to a width.

ここで、誘電体基板3a,3b,3c,3d間
及び地導体2cと誘電体基板3b間にはさみ込ん
だ接着シート6が絶縁物であつても損失の点を除
けば特に問題はない。
Here, even if the adhesive sheet 6 sandwiched between the dielectric substrates 3a, 3b, 3c, and 3d and between the ground conductor 2c and the dielectric substrate 3b is an insulator, there is no particular problem except for loss.

なお、以上は各層の内部導体を接触させて成る
接触形の結合孔を用いたトリプレートストリツプ
ラインの多層一体化方法について述べたが、この
発明はこれに限らず結合孔をスロツト等で形成し
た無接触形のトリプレートストリツプラインの多
層一体化方法にも使用できる。
Although the method for integrating multiple layers of triplate strip lines using contact-type coupling holes formed by contacting the internal conductors of each layer has been described above, the present invention is not limited to this, and the coupling holes may be formed by slots, etc. It can also be used in a multilayer integration method for non-contact triplate strip lines.

以上、この発明によるトリプレートストリツプ
ラインの多層一体化方法によると各層間の地導体
一枚を接着シートで置換すると共に結合孔を形成
する内部導体を予備ハンダする事により、製造過
程で生じる各層間の電気的接続の不具合が大巾に
軽減できる。
As described above, according to the method for integrating multiple layers of a triplate strip line according to the present invention, by replacing one ground conductor between each layer with an adhesive sheet and pre-soldering the internal conductor forming the bonding hole, various Problems in electrical connections between layers can be greatly reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のトリプレートストリツプライン
の多層一体化方法を示す概略断面図、第2図はこ
の発明の実施例を示す概略断面図である。 図中、1は圧力・熱、2a,2b,2c,2d
は地導体、3a,3b,3c,3dは誘電体基
板、4a,4bは内部導体、5は結合孔、6は接
着シート、7は予備ハンダである。なお、図中同
一あるいは相当部分には同一符号を付して示して
ある。
FIG. 1 is a schematic sectional view showing a conventional method for integrating multiple layers of triple-plate strip lines, and FIG. 2 is a schematic sectional view showing an embodiment of the present invention. In the figure, 1 is pressure/heat, 2a, 2b, 2c, 2d
3 is a ground conductor, 3a, 3b, 3c, and 3d are dielectric substrates, 4a, 4b are internal conductors, 5 is a bonding hole, 6 is an adhesive sheet, and 7 is a preliminary solder. It should be noted that the same or corresponding parts in the figures are indicated by the same reference numerals.

Claims (1)

【特許請求の範囲】[Claims] 1 多層化されるトリプレートストリツプライン
の各層間の地導体一枚を接着剤あるいは接着シー
トで置換するとともに、結合孔を形成する内部導
体を予備ハンダすると共に、誘電体基板間にも接
着剤あるいは接着シートをはさみ込み、これら全
体に圧力および熱を加えて多層一体化するように
したことを特徴とするトリプレートストリツプラ
インの多層一体化方法。
1. Replace one ground conductor between each layer of the multi-layered triplate strip line with an adhesive or an adhesive sheet, pre-solder the internal conductor that forms the bonding hole, and also apply adhesive between the dielectric substrates. Alternatively, a multilayer integration method for triplate strip lines is characterized in that adhesive sheets are sandwiched and pressure and heat are applied to the entire structure to integrate the multilayers.
JP3187880A 1980-03-13 1980-03-13 Multilayer unification method of triplate strip line Granted JPS56128001A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3187880A JPS56128001A (en) 1980-03-13 1980-03-13 Multilayer unification method of triplate strip line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3187880A JPS56128001A (en) 1980-03-13 1980-03-13 Multilayer unification method of triplate strip line

Publications (2)

Publication Number Publication Date
JPS56128001A JPS56128001A (en) 1981-10-07
JPS625482B2 true JPS625482B2 (en) 1987-02-05

Family

ID=12343289

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3187880A Granted JPS56128001A (en) 1980-03-13 1980-03-13 Multilayer unification method of triplate strip line

Country Status (1)

Country Link
JP (1) JPS56128001A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1234957B (en) * 1989-07-21 1992-06-02 Selenia Ind Elettroniche RF DIVISION NETWORK FOR ARRAY TYPE ANTENNAS
US5309122A (en) * 1992-10-28 1994-05-03 Ball Corporation Multiple-layer microstrip assembly with inter-layer connections
GB2282270B (en) * 1993-03-31 1996-12-04 Motorola Inc Switch circuit and method therefor
JP3487283B2 (en) 2000-10-31 2004-01-13 三菱電機株式会社 Differential stripline vertical converter and optical module

Also Published As

Publication number Publication date
JPS56128001A (en) 1981-10-07

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