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JPS625489B2 - - Google Patents
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JPS625489B2 - - Google Patents

Info

Publication number
JPS625489B2
JPS625489B2 JP9024480A JP9024480A JPS625489B2 JP S625489 B2 JPS625489 B2 JP S625489B2 JP 9024480 A JP9024480 A JP 9024480A JP 9024480 A JP9024480 A JP 9024480A JP S625489 B2 JPS625489 B2 JP S625489B2
Authority
JP
Japan
Prior art keywords
constant current
current source
transistors
circuit
differential amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP9024480A
Other languages
Japanese (ja)
Other versions
JPS5715512A (en
Inventor
Masami Oonishi
Mitsuo Isobe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP9024480A priority Critical patent/JPS5715512A/en
Publication of JPS5715512A publication Critical patent/JPS5715512A/en
Publication of JPS625489B2 publication Critical patent/JPS625489B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G1/00Details of arrangements for controlling amplification
    • H03G1/0005Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0035Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using continuously variable impedance elements
    • H03G1/0082Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using continuously variable impedance elements using bipolar transistor-type devices

Landscapes

  • Control Of Amplification And Gain Control (AREA)

Description

【発明の詳細な説明】 本発明はトランジスタを用いた利得制御装置に
関するものであつて、特に低電圧で動作する機器
に好適な構成の装置を提供せんとするものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gain control device using transistors, and particularly aims to provide a device having a configuration suitable for equipment operating at low voltage.

利得制御装置は、一般的には利得制御動作に伴
う増幅トランジスタ直流動作点の変化がなく、ま
たこの装置の増幅特性をその利点にかかわらず直
線的に維持できることが望まれるが、この種の装
置のダイナミツクレンジが十分にあるならば前述
した直流動作点の変化が比較的大きくても許容さ
れる。しかしながらバツテリ駆動の機器等におけ
るように回路電源電圧が数V程度と低い場合には
直流動作点の変化は利得制御範囲を著しく制限す
るのみでなく周波数特性をも大きく変化させるた
めに機器の性能を劣化させる原因となる。本発明
に関する従来回路としては一例として特公昭53−
15355号公報「可変利得制御回路」に記載された
ものである。
Generally speaking, it is desirable for a gain control device to have no change in the DC operating point of the amplification transistor due to the gain control operation, and to be able to maintain the amplification characteristics of the device linearly regardless of its advantages. As long as there is a sufficient dynamic range, a relatively large change in the DC operating point can be tolerated. However, when the circuit power supply voltage is as low as a few volts, such as in battery-powered equipment, changes in the DC operating point not only significantly limit the gain control range but also greatly change the frequency characteristics, which impairs the performance of the equipment. This may cause deterioration. As an example of a conventional circuit related to the present invention,
This is described in Publication No. 15355 "Variable Gain Control Circuit".

これは第1図に示すようにトランジスタ1,2
と定電流源3で構成された差動増幅回路およびダ
イオード5,6と定電流源4とで構成された可変
インピーダンス回路から成り、これらを信号電流
源7で駆動し、定電流源3と4との電流比を変化
させて利得を制御するものである。回路の出力直
流レベルが利得制御によつて変化しないようにす
るには電流源3の電流値を固定とし、電流源4の
みを可変にすることで実現される。
This is done by transistors 1 and 2 as shown in Figure 1.
It consists of a differential amplifier circuit consisting of a constant current source 3 and a variable impedance circuit consisting of diodes 5 and 6 and a constant current source 4. These are driven by a signal current source 7, and the constant current sources 3 and 4 The gain is controlled by changing the current ratio between the In order to prevent the output DC level of the circuit from changing due to gain control, the current value of the current source 3 is fixed and only the current source 4 is made variable.

この回路の電流伝送能率η(入力信号電流i
sに対する出力信号電流ipの比)はトランジスタ
1,2の電流増幅率をheとし、定電流源3お
よび4の電流値をそれぞれI1,I5とすると、 η=i/i=1/(1/h+I/I
……(1) で表わされ、また1/he≪I5/I1の条件下において
は ηI1/I5 ……(2) と表わせる。したがつて所望の利得制御範囲を得
るにはそれに対応した電流変化を定電流源4に与
えねばならない。ところで通常信号電流源7は第
2図に示すように抵抗器12と信号電圧源11お
よび直流電圧源10で構成し、負荷側インピーダ
ンスに比較して抵抗12の抵抗値を十分大きく設
定することで実用可能であるが、電流源4を変化
させて利得制御した場合電流源4の電流変化分Δ
Iと第2図に示した抵抗12の抵抗値の積による
電圧変化が第1図のトランジスタ1,2のベース
バイアスの変動となる。例えば抵抗12の抵抗値
が数KΩであれば1mAの電流変化は数Vのベー
スバイアス変動となるので電源電圧Vccが数Vと
低い場合には使用できない。またベースバイアス
の大きな変動は第1図のトランジスタ1および2
のコレクタ−ベース逆バイアスの大きな変化とな
つてトランジスタ接合容量を変化させるので周波
数特性が変化する原因ともなる。
Current transmission efficiency of this circuit η 1 (input signal current i
The ratio of output signal current i p to s is calculated as follows: η 1 = i p /i, where the current amplification factors of transistors 1 and 2 are h e and the current values of constant current sources 3 and 4 are I 1 and I 5 , respectively . s = 1/(1/h e +I 5 /I 1 )
...(1), and under the condition of 1/h e <<I 5 /I 1 , it can be expressed as η 1 I 1 /I 5 ...(2). Therefore, in order to obtain a desired gain control range, a corresponding current change must be applied to the constant current source 4. By the way, the normal signal current source 7 is composed of a resistor 12, a signal voltage source 11, and a DC voltage source 10 as shown in FIG. 2, and by setting the resistance value of the resistor 12 sufficiently large compared to the load side impedance. Although it is practical, if the gain is controlled by changing the current source 4, the current change amount Δ of the current source 4
The voltage change caused by the product of I and the resistance value of the resistor 12 shown in FIG. 2 results in a change in the base bias of the transistors 1 and 2 shown in FIG. For example, if the resistance value of the resistor 12 is several kilohms, a current change of 1 mA results in a base bias fluctuation of several volts, so it cannot be used when the power supply voltage Vcc is as low as several volts. Also, large variations in base bias are caused by transistors 1 and 2 in Figure 1.
This results in a large change in the collector-base reverse bias of the transistor, which changes the transistor junction capacitance and causes a change in frequency characteristics.

以上のように利得制御装置では周波数特性を一
定に保つこと、また次段との直流結合を容易にす
るためにも増幅トランジスタの動作点が利得制御
動作によつて変化しないようにすることが望まれ
ている。
As mentioned above, in a gain control device, it is desirable to keep the frequency characteristics constant, and also to prevent the operating point of the amplification transistor from changing due to the gain control operation in order to facilitate DC coupling with the next stage. It is rare.

本発明は上記従来の欠点を解消させるべく増幅
トランジスタ動作点の変化が小さい利得制御装置
を提供せんとするものであつて、以下図面にもと
づいて詳しく説明する。
The present invention aims to eliminate the above-mentioned conventional drawbacks by providing a gain control device in which the change in the operating point of an amplifying transistor is small, and will be described in detail below with reference to the drawings.

第3図は本発明の基本構成図を示しており、従
来例を示す第1図と同じ機能を有するものについ
ては同符号を付している。第3図において1,2
はベース電極を差動入力端子とし、エミツタ電極
を共通接続して差動増幅回路を構成するトランジ
スタ、3は前記トランジスタ1,2のエミツタ接
続点に接続された電流値I1なる定電流源、7は前
記差動増幅回路入力端子に接続された信号電流
源、8,9は負荷抵抗、13,14はそれぞれの
エミツタ電極が前記差動増幅回路入力端子(トラ
ンジスタ1,2の各ベース)にそれぞれ接続さ
れ、両コレクタ電極を共通接続し、かつベース電
極を共通接続して入力端子間で可変インピーダン
ス回路を構成するトランジスタ、15はトランジ
スタ、13,14のベース電極に接続され、その
ベース電流を制御する電流値I2なる定電流源、1
6,17は前記差動入力端子間に接続されたイン
ピーダンス値がともにZ2なるインピーダンス回路
である。
FIG. 3 shows a basic configuration diagram of the present invention, and parts having the same functions as those in FIG. 1 showing the conventional example are given the same reference numerals. 1, 2 in Figure 3
3 is a transistor whose base electrode is a differential input terminal and whose emitter electrodes are commonly connected to form a differential amplifier circuit; 3 is a constant current source having a current value I 1 connected to the emitter connection point of the transistors 1 and 2; 7 is a signal current source connected to the differential amplifier circuit input terminal, 8 and 9 are load resistors, and 13 and 14 are respective emitter electrodes connected to the differential amplifier circuit input terminal (bases of transistors 1 and 2). A transistor 15 is connected to the base electrodes of 13 and 14, and a transistor 15 is connected to the base electrodes of 13 and 14, and the transistor 15 is connected to the base electrodes of 13 and 14, and has its collector electrodes commonly connected and its base electrodes commonly connected to form a variable impedance circuit between the input terminals. A constant current source with a current value to be controlled I 2 , 1
Reference numerals 6 and 17 are impedance circuits connected between the differential input terminals, both of which have an impedance value of Z2 .

この構成において利得の制御は定電流源15の
電流値を変化させ、これによつてトランジスタ1
3,14のコレクタ−エミツタ間インピーダンス
を変化せしめ、信号電流isと差動増幅回路入力
信号電流との分流比を変化させることで達成でき
る。インピーダンス回路16,17は利得制御装
置が最大利得時(I2=0で可変インピーダンス回
路のインピーダンスが無限大とみなせる程大きい
時)に差動増幅段トランジスタ13,14の電流
増幅率heのばらつきによる最大利得のばらつ
きを減少させるためのものである。これらのこと
を次に詳細に説明する。
In this configuration, the gain is controlled by changing the current value of the constant current source 15, thereby controlling the gain of the transistor 1.
This can be achieved by changing the impedance between the collectors 3 and 14 and by changing the shunt ratio between the signal current i s and the input signal current of the differential amplifier circuit. The impedance circuits 16 and 17 control the variation in the current amplification factor h e of the differential amplifier stage transistors 13 and 14 when the gain control device is at maximum gain (when I 2 = 0 and the impedance of the variable impedance circuit is large enough to be considered infinite). This is to reduce the variation in maximum gain due to These matters will be explained in detail next.

まず接合形トランジスタのコレクタ−エミツタ
間飽和電圧をVCE(sat)とすると、 で表わされ、したがつて飽和領域におけるインピ
ーダンスZ3となる。ここでk:ボルツマン定数、q:電子電
荷、T:絶対温度、αN:順方向ベース接地電流
増幅率、αi:逆方向ベース接地電流増幅率、r
e:エミツタバルク抵抗、rsc:コレクタバルク
抵抗、Ic:コレクタ電流、IB:ベース電流、I
E:エミツタ電流である。(4)式においては(3)式お
ける第2、第3項の微分値re,rscのバルク抵
抗成分は(4)式第1項成分に比べてはるかに小さい
ため省略している。またαN/(1−αN)はエミ
ツタ接地電流増幅率heであるので(4)式は となり、これは可変インピーダンス回路のトラン
ジスタ1個のC―E間インピーダンスである。
First, if the collector-emitter saturation voltage of a junction transistor is V CE(sat) , then Therefore, the impedance Z 3 in the saturation region is becomes. where k: Boltzmann constant, q: electronic charge, T: absolute temperature, α N : forward common base current amplification factor, α i : reverse common base current amplification factor, r
e : emitter bulk resistance, r sc : collector bulk resistance, I c : collector current, I B : base current, I
E : Emitter current. In equation (4), the bulk resistance components of the differential values r e and r sc of the second and third terms in equation (3) are omitted because they are much smaller than the first term component in equation (4). Also, α N /(1−α N ) is the emitter grounded current amplification factor h e , so equation (4) is This is the CE-to-E impedance of one transistor in the variable impedance circuit.

一方差動増幅回路のトランジスタ1の入力イン
ピーダンスZ1は Z1=rbb1+k/q h/IE1/q
/IE1……(6) となる。ここにrbb1:ベース拡がり抵抗、IE1
トランジスタ1のエミツタ電流である。ところで
第3図において入力端子には正負逆の差動入力信
号が供給されるためにトランジスタ1,2のエミ
ツタ接続点、トランジスタ13,14のコレクタ
接続点およびインピーダンス回路16,17の接
続点は仮想接地点と見なすことができ、仮想接地
点を軸として対象な回路であるから、一方のみで
説明を進める。
On the other hand, the input impedance Z 1 of transistor 1 of the differential amplifier circuit is Z 1 = r bb1 +k T /q h e /I E1 k T /q
h e /I E1 ...(6). Here r bb1 : Base spreading resistance, I E1 :
This is the emitter current of transistor 1. By the way, in FIG. 3, since differential input signals with opposite positive and negative polarities are supplied to the input terminals, the emitter connection point of transistors 1 and 2, the collector connection point of transistors 13 and 14, and the connection point of impedance circuits 16 and 17 are virtual. Since it can be regarded as a grounding point and the circuit is symmetrical with respect to the virtual grounding point, the explanation will proceed based on only one side.

本発明による利得制御装置の入力信号電流に対
する出力信号電流の比である信号電流伝送能率η
は入力信号電流をis、トランジスタ1の出力
信号電流をipとすれば、ipは(5),(6)式のZ3,Z1
および第3図中Z2により分流された入力信号のh
e倍であるから であり、(5),(6)式を代入すると、 となる。さらにトランジスタ13のコレクタは開
放、もしくは高抵抗で電源電圧Vccラインに接続
されるので(8)式におけるコレクタ電流Icは殆ど
零に近くなり、簡略化されて以下のようになる。
The signal current transmission efficiency η, which is the ratio of the output signal current to the input signal current of the gain control device according to the present invention
2 , if the input signal current is i s and the output signal current of transistor 1 is i p , then i p is Z 3 and Z 1 in equations (5) and (6).
and h of the input signal shunted by Z 2 in Figure 3.
Because it is e times , and substituting equations (5) and (6), we get becomes. Furthermore, since the collector of the transistor 13 is open or connected to the power supply voltage Vcc line with high resistance, the collector current Ic in equation (8) is almost zero, and can be simplified as follows.

さらにhe≫1/(1−αi)であり、IE1=I1/
2,IB=I2/2であるから最終的に η=1/{1/h+2V/I 1/Z+I
/I(1/1−α)}…… (10) となる。ここでVT=k/qである。
Furthermore, h e ≫1/(1−α i ), and I E1 = I 1 /
2, Since I B = I 2 /2, finally η 2 = 1/{1/h e +2V T /I 1 1/Z 2 +I
2 /I 1 (1/1-α i )}... (10). Here, V T =k T /q.

(10)式の第2項2V/I・1/Zは後述する最
大利得のば らつきを軽減するに有効な項であつて定数C1
して設定する。ここで1/h+C1≪I/I(1
/1−α)の 条件下では(10)式は以下のようになる。
The second term 2V T /I 1 ·1/Z 2 in equation (10) is an effective term for reducing variations in maximum gain, which will be described later, and is set as a constant C 1 . Here, 1/h e +C 1 ≪I 2 /I 1 (1
/1-α i ), equation (10) becomes as follows.

η1/I/I(1/1−α)=I/I
……(11) ここでk=(1/1−α)であり、kは1より大き く通常3程度の値を有している。したがつて(11)式
を、従来例における伝送能率ηを示した(2)式η
=I1/I5と比較してみるとI1を一定電流、I2,I5
を利得を制御するための制御電流とした時に同じ
伝送能率を得るのに本発明においては1/kの制御
電流で良いことが判る。これは第3図におけるト
ランジスタ1および2のベースバイアス変動が第
1図の従来例のそれに比べて1/kになることを意
味し、したがつて本発明においては回路ダイナミ
ツクレンジの増大および周波数特性の安定の面で
大きく改善される。
η 2 1/I 2 /I 1 (1/1-α i )=I 1 /I 2 k
...(11) Here, k=(1/1-α i ), and k is larger than 1 and usually has a value of about 3. Therefore, equation (11) is replaced by equation (2) η, which indicates the transmission efficiency η 1 in the conventional example.
Comparing 1 = I 1 /I 5 , I 1 is a constant current, I 2 , I 5
It can be seen that in the present invention, a control current of 1/k is sufficient to obtain the same transmission efficiency when is used as the control current for controlling the gain. This means that the base bias fluctuations of transistors 1 and 2 in FIG. 3 are 1/k compared to that in the conventional example shown in FIG. This greatly improves the stability of characteristics.

ところで利得制御装置は通常AGC(自動利得
制御)回路内に組込まれて使用されることが多
く、その場合には利得制御装置の最大利得に大き
なばらつきがあると、AGC回路の利得制御範囲
に同等のばらつきを生じさせる。つまりAGC回
路として同一出力レベルに制御し得る最小入力信
号レベルが大きくばらつく結果となる。(10)式にお
ける第2項はこのばらつきを軽減するたゆのもの
で、今(10)式においてI/I=0とした時の最大信
号伝 送能率η(max)は η2(nax)=1/{1/h+2V/I 1/Z
}……(12) となる。ここで1/h≪2V/I 1/Z
おけば η2(nax)は η2(nax)/2V・Z2=C1 ……(13) となる。通常he=50〜300であるのでC1は0.1
〜1程度の値をとる。今仮にC1=0.1と設定しh
eが50から300の範囲にばらついている時、
(13)式における最大利得η2(nax)のばらつきは
約1dB程度となり、C1の項がない場合(C1=0)
の最大利得η2(nax)のばらつきが約16dBであるの
に比べるとC1の項により最大利得のばらつきが
大幅に改善されるのが判る。
By the way, gain control devices are often used built into AGC (automatic gain control) circuits, and in that case, if there is a large variation in the maximum gain of the gain control device, the gain control range of the AGC circuit may vary. This causes variations in In other words, the minimum input signal level that can be controlled to the same output level as an AGC circuit will vary greatly. The second term in equation (10) is used to reduce this variation, and now in equation (10), when I 2 /I 1 = 0, the maximum signal transmission efficiency η 2 (max) is η 2( nax) =1/{1/h e +2V T /I 1 1/Z 2
}...(12) becomes. Here, if we set 1/h e <<2V T /I 1 1/Z 2 , η 2(nax) becomes η 2(nax) I 1 /2V T ·Z 2 =C 1 (13). Usually h e = 50 to 300, so C 1 is 0.1
It takes a value of ~1. Now let us temporarily set C 1 = 0.1 and h
When e varies between 50 and 300,
The variation in the maximum gain η 2 (nax) in equation (13) is about 1 dB, and when there is no C 1 term (C 1 = 0)
Compared to the variation in the maximum gain η 2 (nax) of about 16 dB, it can be seen that the variation in the maximum gain is significantly improved by the C 1 term.

第4図は第3図の基本回路におけるインピーダ
ンス回路16および17を抵抗値R2なる固定抵
抗16a,17aとした実施例であり他の構成要
素は第3図と同一である。第4図の実施例におい
て伝送能率ηは(10)式と同じく η=1/{1/h+2V/I+I/I
(1/1−α)}…… (14) となる。この時の利得の制御は定電流源3の電流
値I1を一定電流とし、定電流源15の電流値I2
制御することで行なわれる。この時の最大伝送能
率η2(nax)は η2(nax)=1/{1/h+2V/I}…
…(15) となる。上式においてVT=k/qであり常温(T= 300〓)で26mVの値であつて定数である。一方
I1R2は電流・抵抗の積であつて、通常の集積回路
技術においては電流と電圧のばらつき方向は互に
打消し合うので2〜5%程度の絶対精度を得るこ
とができる。したがつて(15)式における2V/I
= C1の値を比較的精度良く設定できるので第4図
の実施例の回路において最大伝送能率η2(nax)
ばらつきを小さいものにできる。
FIG. 4 shows an embodiment in which the impedance circuits 16 and 17 in the basic circuit of FIG. 3 are fixed resistors 16a and 17a having a resistance value R 2 , and the other components are the same as in FIG. 3. In the embodiment shown in FIG. 4, the transmission efficiency η 2 is the same as equation (10), η 2 =1/{1/h e +2V T /I 1 R 2 +I 2 /I
1 (1/1-α i )}... (14) The gain control at this time is performed by making the current value I 1 of the constant current source 3 a constant current and controlling the current value I 2 of the constant current source 15. The maximum transmission efficiency η 2(nax) at this time is η 2(nax) = 1/{1/h e +2V T /I 1 R 2 }...
…(15) becomes. In the above equation, V T =k T /q, which is a constant value of 26 mV at room temperature (T = 300〓). on the other hand
I 1 R 2 is the product of current and resistance, and in normal integrated circuit technology, the directions of variations in current and voltage cancel each other out, so an absolute accuracy of about 2 to 5% can be obtained. Therefore, 2V T /I 1 in equation (15)
Since the value of R 1 =C 1 can be set with relatively high precision, variations in the maximum transmission efficiency η 2 (nax) can be made small in the circuit of the embodiment shown in FIG.

第5図は第3図の基本回路のインピーダンス回
路16,17をダイオード16b,17bおよび
電流値I5なる定電流源18で構成した実施例であ
り、この時インピーダンスZ2はダイオード動作抵
抗となり Z2=2V/I ……(16) となる。これを(10)式に代入すれば η=1/{1/h+I/I+I/I
1/1−α)}…… (17) が得られる。ここで1/h≪I/I=C1(一定
)となる ようにI5とI1の比を選んでやれば最大伝送能率η2
(nax)のばらつきは押さえられる。しかもC1の項
には(15)式のように温度成分を含まないので第
4図実施例に比べて温度変動が少ない。この時の
利得制御は定電流源3の電流値I1と定電流源15
の電流値I2の比を変えることで行われるのでI1
I2いずれを、もしくは両方を変化させても良い。
但しI1を変化させる時には定電流源18の電流I5
も追従変化させI5/I1が一定になるように考慮する
必要がある。これについては定電流源3,18を
構成する際にエミツタ面積比がI5/I1であるような
共通ベースのトランジスタを用いることで解決で
きる。
FIG. 5 shows an embodiment in which the impedance circuits 16 and 17 of the basic circuit shown in FIG. 3 are constructed with diodes 16b and 17b and a constant current source 18 with a current value I5 , and in this case, the impedance Z2 becomes the diode operating resistance Z 2 = 2V T /I 5 ... (16). Substituting this into equation (10), we get η 2 =1/{1/h e +I 5 /I 1 +I 2 /I 1 (
1/1−α i )}... (17) is obtained. Here, if the ratio of I 5 and I 1 is selected so that 1/h e ≪I 5 /I 1 = C 1 (constant), the maximum transmission efficiency η 2
(nax) variations can be suppressed. Furthermore, since the term C1 does not include a temperature component as in equation (15), the temperature fluctuation is smaller than in the embodiment shown in FIG. Gain control at this time is based on the current value I 1 of constant current source 3 and constant current source 15.
This is done by changing the ratio of the current value I 2 of I 1 ,
Either or both of I2 may be changed.
However, when changing I1 , the current I5 of constant current source 18
It is also necessary to take into account that I 5 /I 1 is constant by changing the following. This can be solved by using common base transistors with an emitter area ratio of I 5 /I 1 when configuring the constant current sources 3 and 18.

第6図は第3図の基本構成のうちトランジスタ
13,14のベース電流を独立した電流源19,
20から供給する実施例で、電流源19,20の
電流値をI3,I4と1,I3=I4とすれば、この時伝送
能率ηは(10)式から η=1/{1/h+2V/I+2I
(1/1−α)}…… (18) で表わされる。
FIG. 6 shows the base current of the transistors 13 and 14 in the basic configuration of FIG.
In this example, if the current values of the current sources 19 and 20 are I 3 , I 4 and 1, and I 3 = I 4 , then the transmission efficiency η 2 is calculated as η 2 = 1 from equation (10). /{1/h e +2V T /I 1 Z 2 +2I 3 /
I 1 (1/1-α i )}... (18) It is expressed as follows.

以上のように本発明は可変インピーダンス回路
として少くとも2対のトランジスタのC―E間飽
和インピーダンスを用い、差動増幅段入力インピ
ーダンスとの比を制御することで利得を制御して
いる。可変インピーダンス回路を可変するための
制御電流は従来例に比べて数分の1となるために
差動増幅段ベースバイアス変動を少なくすること
ができ、すなわち回路ダイナミツクレンジの増
大、また周波数特性の安定化の面で大きく改善さ
れる。また最大利得のばらつきの少ないなど本発
明による効果は大なるものがある。
As described above, the present invention uses the CE-to-E saturation impedance of at least two pairs of transistors as a variable impedance circuit, and controls the gain by controlling the ratio to the input impedance of the differential amplifier stage. Since the control current for varying the variable impedance circuit is a fraction of that of the conventional example, it is possible to reduce the variation in the base bias of the differential amplifier stage, which increases the circuit dynamics range and improves the frequency characteristics. Great improvement in terms of stabilization. Further, the present invention has significant effects such as less variation in maximum gain.

なお実施例においてトランジスタ13,14は
NPNトランジスタとしているが、PNPトランジ
スタにても本発明の目的と効果を達成できること
はいうまでもない。
In addition, in the embodiment, the transistors 13 and 14 are
Although NPN transistors are used, it goes without saying that the objects and effects of the present invention can also be achieved with PNP transistors.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の利得制御装置の構成図、第2図
は電流源の等価回路図、第3図は本発明の基本構
成図、第4図、第5図、第6図はそれぞれ本発明
の実施例を示す構成図である。 1,2……トランジスタ、3……定電流源、7
……信号電流源、13,14……トランジスタ、
15……定電流源、16,17……インピーダン
ス回路、16a,17a……固定抵抗、16b,
17b……ダイオード、18……定電流源、1
9,20……電流源。
Fig. 1 is a block diagram of a conventional gain control device, Fig. 2 is an equivalent circuit diagram of a current source, Fig. 3 is a basic block diagram of the present invention, and Figs. 4, 5, and 6 are respectively in accordance with the present invention. FIG. 1, 2...transistor, 3...constant current source, 7
... Signal current source, 13, 14 ... Transistor,
15... constant current source, 16, 17... impedance circuit, 16a, 17a... fixed resistance, 16b,
17b...Diode, 18... Constant current source, 1
9, 20... Current source.

Claims (1)

【特許請求の範囲】 1 ベース電極を差動入力端子とし、エミツタ電
極を共通接続してなる少くとも第1,第2のトラ
ンジスタ対より構成される差動増幅回路と、前記
入力端子にエミツタ電極をそれぞれ接続するとと
もにコレクタ電極を共通接続した少くとも第3,
第4のトランジスタを含んでなる可変インピーダ
ンス回路と、前記入力端子間に接続された前記差
動増幅回路入力インピーダンス値と比例したイン
ピーダンス値を有する第2インピーダンス回路を
有し、前記入力端子間に差動信号電流源を接続
し、前記第1,第2トランジスタエミツタ共通接
続点を第1定電流源に接続するとともに、前記可
変インピーダンス回路を構成する第3,第4トラ
ンジスタのベース電極にこれらトランジスタのベ
ース電流を制御するための第2定電流源を接続
し、前記第1,第2定電流源の何れか一方、また
は両方が前記差動増幅器の利得を変化させるため
に制御されてなる利得制御装置。 2 前記可変インピーダンス回路を構成するトラ
ンジスタ対のベース電極を共通接続するととも
に、前記接続点を第2定電流源に接続してなる特
許請求の範囲第1項記載の利得制御装置。 3 前記第2定電流源が第3,第4定電流源で構
成されるとともに、前記可変インピーダンス回路
を構成する第3,第4トランジスタのベース電極
をそれぞれ前記第3,第4定電流源に接続し、前
記第3,第4定電流源と前記第1定電流源の電流
比によつて利得を制御してなる特許請求の範囲第
1項記載の利得制御装置。 4 前記第2インピーダンス回路としてそれぞれ
のアノード電極が前記入力端子のそれぞれに接続
され、カソード電極が共通接続された第1,第2
ダイオードを有し、該カソード電極接続点に前記
第1定電流源と一定比の電流値の第5定電流源が
接続されてなる特許請求の範囲第1項記載の利得
制御装置。 5 前記第1定電流源を固定電流源とし、前記第
2インピーダンス回路として前記差動増幅回路第
1,第2トランジスタエミツタ抵抗より少くとも
大なる抵抗値の固定抵抗器を有する特許請求の範
囲第1項記載の利得制御装置。
[Scope of Claims] 1. A differential amplifier circuit comprising at least a first and second transistor pair, each having a base electrode as a differential input terminal and an emitter electrode connected in common; At least a third,
a variable impedance circuit including a fourth transistor; and a second impedance circuit connected between the input terminals and having an impedance value proportional to the input impedance value of the differential amplifier circuit; A dynamic signal current source is connected, a common connection point of the emitters of the first and second transistors is connected to the first constant current source, and base electrodes of the third and fourth transistors constituting the variable impedance circuit are connected to these transistors. A second constant current source for controlling the base current of the differential amplifier is connected, and either one or both of the first and second constant current sources is controlled to change the gain of the differential amplifier. Control device. 2. The gain control device according to claim 1, wherein the base electrodes of the transistor pair constituting the variable impedance circuit are commonly connected, and the connection point is connected to a second constant current source. 3. The second constant current source is composed of third and fourth constant current sources, and the base electrodes of the third and fourth transistors forming the variable impedance circuit are connected to the third and fourth constant current sources, respectively. 2. The gain control device according to claim 1, wherein the gain is controlled by the current ratio of the third and fourth constant current sources and the first constant current source. 4 As the second impedance circuit, first and second impedance circuits each have an anode electrode connected to each of the input terminals and a cathode electrode connected in common.
2. The gain control device according to claim 1, comprising a diode, and a fifth constant current source having a current value at a fixed ratio with respect to the first constant current source is connected to the cathode electrode connection point. 5. The first constant current source is a fixed current source, and the second impedance circuit includes a fixed resistor having a resistance value at least larger than the emitter resistance of the first and second transistors of the differential amplifier circuit. The gain control device according to item 1.
JP9024480A 1980-07-02 1980-07-02 Gain controller Granted JPS5715512A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9024480A JPS5715512A (en) 1980-07-02 1980-07-02 Gain controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9024480A JPS5715512A (en) 1980-07-02 1980-07-02 Gain controller

Publications (2)

Publication Number Publication Date
JPS5715512A JPS5715512A (en) 1982-01-26
JPS625489B2 true JPS625489B2 (en) 1987-02-05

Family

ID=13993080

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9024480A Granted JPS5715512A (en) 1980-07-02 1980-07-02 Gain controller

Country Status (1)

Country Link
JP (1) JPS5715512A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58196706A (en) * 1982-05-11 1983-11-16 Matsushita Electric Ind Co Ltd Control circuit

Also Published As

Publication number Publication date
JPS5715512A (en) 1982-01-26

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