JPS6255352B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a drive circuit for a solid-state image sensor, such as a CCD (charge coupled device).

Solid-state imaging devices such as CCDs have been used in various fields in recent years, such as two-dimensional imaging devices used in place of image pickup tubes in television cameras, and one-dimensional CCD sensors used in facsimiles and image processing, etc. as photoelectric conversion devices. It has come to be used in many technical fields. In particular, CCDs use their photoelectric conversion, storage functions, and self-transfer functions to sequentially transfer the image charge accumulated in each picture element in one direction while extracting image signals. In recent years, the range of applications has been expanding more and more by taking advantage of characteristics such as low power consumption.

The present invention relates to a drive circuit for a solid-state image sensor as described above, and an object of the present invention is to provide a drive circuit for minimizing non-linearity in output characteristics of a CCD, especially at low illuminance.

The present invention will be explained in detail below with reference to the drawings.

Since the output voltage of a solid-state image sensor is linearly proportional to the illuminance, the dynamic range is narrow. A method is used to expand the dynamic range by switching the FIG. 1 is a characteristic curve diagram in which the horizontal axis is the logarithm of the light-receiving element surface illuminance I of the solid-state image sensor, and the vertical axis is the logarithm of the output voltage V of the image sensor. The illustrated illuminance-output characteristic curve is ideally a straight line with γ=1, based on the signal output level when the photoelectric conversion section of the solid-state image sensor is shielded from light. Unnecessary charges generated in the photoelectric conversion section of the solid-state image sensor are transferred to an analog shift register for charge transfer by a charge transfer pulse, and this analog shift register is reset by idle feeding, and only the necessary charges are accumulated. In a normal driving method in which an output signal is obtained by reading out a signal, an almost ideal characteristic of γ=1 is obtained regardless of the accumulation time, as shown by the broken line in FIG. However, with such a driving method, it is not possible to make the accumulation time shorter than the time required to read out all the charges generated in the photoelectric conversion section. In order to improve this and drive with a short accumulation time, a solid-state image sensor, such as Retikon's solid-state image sensor, has an integral clear gate that can instantly reset the unnecessary charge.
CCPD is manufactured. A solid-state image pickup device of this type has characteristics as shown by the solid line in FIG. 1, and the illuminance-output characteristic becomes non-linear, especially at low illuminance. This nonlinearity is a phenomenon that occurs due to the electrical induction of the driving pulse and the interface state, and this phenomenon tends to become larger in the case of low illuminance.

The present invention is a drive circuit for minimizing the non-linearity of the illuminance-output characteristic in a solid-state image sensor as described above. This is a drive circuit that sometimes controls the storage time using a charge transfer gate.

FIG. 2 is a circuit connection diagram showing an embodiment of a driving circuit for a solid-state image sensor according to the present invention, which uses a one-dimensional solid-state image sensor. In the figure, SP surrounded by a broken line is a solid-state image sensor, and photoelectric conversion units S ₁ to Sm,
Integral clear gate FA ₁ ~ FAm _-1 ; FB ₁ ~ FBm _-1 ,
Charge transfer gates FA ₂ ~FAm, FB ₂ ~FBm and charge transfer analog shift registers CA ₁ ~CAn,
Equipped with CB ₁ ~ CBn. The photoelectric conversion section receives incident light and performs photoelectric conversion on the received light. The integral clear gate instantaneously resets the charge accumulated in the photoelectric conversion section by a reset signal (ICG(F)). Further, the charge transfer gate transfers the charges stored in the photoelectric conversion section according to the subject brightness to the analog shift register for charge transfer.

The output from the analog shift register is resistor R ₁
~R ₃ , FET, FC1, and FC2, the voltage information is converted into voltage information V _F and read out.
The voltage divider circuit consisting of resistors R ₄ to _{R 6} has a reference voltage Vmax,
Generate Vmin. Comparator CP ₁ , CP ₂ , inverter IN ₁ , OR gate OR ₁ , AND gate
The logic circuit consisting of AN ₁ , exclusive OR gate EX ₁ , and up-down counter ADC is an accumulation time designation circuit, and a comparator is set so that the output VF of the solid-state image sensor SP falls within the appropriate voltage range Vmax>VF>Vmin. Specify the accumulation time by counting down or up the up/down counter ADC using the outputs of CP ₁ and CP ₂ .

FIG. 3 is a timing chart showing the waveforms of the input and output signals of the up-down counter, and specifies the accumulation times t ₁ to _{t 8} . The exclusive OR gate EX ₁ has an accumulation time set to t ₁ or t ₈ , and this prevents the ADC from resetting and fixes the accumulation time when shift information to the short or long time side comes. This is a logic circuit.

FIG. 4 is a timing chart of each control pulse generated by the pulse control circuit PGC. In the PGC shown in the second figure, CLR is a reset pulse for the up-down counter ADC, AC is an accumulation time control pulse, and one pulse is generated each time the output signal of the solid-state image sensor is read. AG is an image control pulse for storing an image signal VF necessary for each readout of the solid-state image sensor into the memory capacitor _C1 via the analog gate _AG1 . ICG is also an integral clear gate control pulse,
SH is a charge transfer gate control pulse, RS is a gate reset pulse for the charge/voltage conversion circuit, and φ1 and φ2 are charge transfer pulses for the analog shift register.

The outputs ICG and SH of the pulse control circuit PGC are
AND gate AN ₂ , AN ₃ , inverter IN ₂ , IN ₃ ,
The signal is input to the integral clear gate and charge transfer gate of the solid-state image sensor SP through an accumulation time control switching circuit consisting of an OR gate _OR2 and a one-shot multivibrator OH. As shown in Figure 3, the _Q1 terminal of the up-down counter ADC is low during the relatively short accumulation time from time _t1 to _t4 .
level, which turns on the AND gate AN ₂ via the inverter 2N ₂ , and its output ICG(F)
is applied to the integral clear gate of SP, which controls the accumulation time as shown in Figure 4.

Next, when the incident light of the SP is dark, the _Q1 terminal of the up-down counter ADC is at the H level from time _t5 to _t8 as shown in Figure 3, so the AND gate _AN2 of the switching circuit is is turned off and the IDG(F) signal is
It is not applied to the integral clear gate of SP. on the other hand
The one-shot multivibrator OH operates in synchronization with the falling phase of the ICG pulse, and the output pulse is applied to the charge transfer gate via the inverter IN ₃ , AND gate AN ₃ , and OR gate OR ₂ , and the output pulse is applied to the charge transfer gate SP. The unnecessary charges in the photoelectric conversion section are read out, and the following steps are carried out as shown in the fourth figure.
During the period until the falling edge of the SH(F) pulse, signal charges are newly accumulated in the photoelectric conversion section.

As described above, according to the drive circuit of the present invention, at low illuminance where non-linear characteristics are relatively likely to occur, the accumulation time is controlled by the charge transfer gate to improve linearity and prevent non-linear characteristics from occurring. By controlling the accumulation time with an integral clear gate that instantaneously resets unnecessary charges during high illuminance, it is possible to obtain a photoelectric output with good linearity over a wide dynamic range from low illumination to high illuminance. Therefore, the effect is great for various photoelectric conversion purposes, and the range of its use can be expanded.

In the above embodiment, low illuminance and high illuminance are discriminated by the output of the accumulation time designation circuit, but illuminance discrimination is performed by a separately provided light receiving element for detecting illuminance, and the output of this light receiving element is shown in Fig. 2. inverter
Another method is to apply it to IN ₂ . It goes without saying that even in this manner, the storage time control method can be switched in accordance with the illuminance in the same manner as in the above embodiment.

[Brief explanation of the drawing]

FIG. 1 is a characteristic curve diagram showing the relationship between light-receiving surface illuminance and output voltage of a solid-state image sensor according to the present invention, and FIG. 2 is a circuit connection diagram showing an embodiment of a driving circuit for a solid-state image sensor according to the present invention. Fig. 3 is a timing chart showing the waveforms of the input and output signals of the up-down counter in Fig. 2, and Fig. 4 shows the waveforms of each control pulse generated by the pulse control circuit and the output signal of the solid-state image sensor in Fig. 2. This is a timing chart. SP...Solid-state image sensor, E ₁ ...Power supply, ADC...
Up/down counter, PGC... Pulse control circuit, CP ₁ , CP ₂ ... Comparator, IN ₁ ,
IN ₂ , IN ₃ ... Inverter, AN ₁ , AN ₂ , AN ₃ ...
...AND gate, OR ₁ , OR ₂ ...OR gate, EX ₁
...Exclusive OR gate, AG ₁ ...Analog gate, C ₁ ...Memory capacitor, OH...
...One-shot multi-vibrator.

Claims (1)

[Claims] 1 A photoelectric conversion storage unit having a plurality of light receiving units accumulates each charge according to the light reception state of each light receiving unit, and after the accumulation is completed, each accumulated charge is transferred to a charge self-transfer unit via a charge transfer gate. , in a drive circuit for a solid-state image sensor that sequentially reads out each charge transferred to the transfer section as a time-series signal, an integral clear gate is provided for erasing the charge accumulated in the photoelectric conversion storage section, and the charge is transferred to the solid-state image sensor. When the amount of incident light is lower than a preset brightness, the charge accumulated in the photoelectric conversion section is transferred to the transfer section via the charge transfer gate, and each charge is read out as a time-series signal and erased. . A drive circuit for a solid-state image sensor, characterized in that, on the other hand, when the amount of incident light is higher in brightness than the brightness, the integral clear gate is activated to erase the charge accumulated in the photoelectric conversion section.