JPS6256686B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to automatic equalization for automatically removing intersymbol interference occurring in a transmission path in digital transmission.

In a conventional transversal automatic equalizer, the signal to be equalized is input to a delay line, and the equalization is applied to each input signal drawn from a plurality of taps attached to the delay line at equal intervals. A structure that applies a variable gain is used.

In this structure, it is necessary to find the product of a signal having an arbitrary value and a variable gain having an arbitrary value, and this part is the most complicated circuit when fabricating the device.

An object of the present invention is to solve the above problems and provide an automatic equalizer with a simple circuit configuration.

The principle of this invention will be explained below. For ease of explanation, binary pulse amplitude modulation will be explained.

If r _k is a sequence obtained by sampling the distorted signal to be equalized at the data transmission period, r _k can be expressed as follows.

Here, a _k is the kth transmission data and takes a value of +1 or -1, and _ho represents pulse waveform distortion that causes intersymbol interference. When estimating data a _l when k=l, the above formula is Therefore, the component of the second term in the above equation is correct a
This is an obstacle to estimating _l . The second term is called intersymbol interference. Now, in a hypothetical case, a _l-1 , a _l-2 , ... a _lN , a _l+1 , a _l+2 , ...
a _l+N and h _-1 , h _-2 , ... h _-N , h ₁ , h ₂ , ... h _N
If is known, the intersymbol interference can be calculated and the intersymbol interference component can be accurately removed from the received signal γ _k . In this invention, the data a _l-1 , a _l-2 , ..., a _lN , a _l
+1 , a _l+2 . . . , a _l+N , the results of the soft decision described below are used. For example, as a soft decision method for estimating a _li , it is possible to determine γ _li using the following rules.

(i) If γ _li is greater than +D (D<1) then a
Determine _li as +1.

(ii) If γ _li is smaller than -D, a _li is determined to be -1.

(iii) If -Dγ _li D, a _li is undetermined and provisionally determined to be 0.

When D=0 in the above rule, it is called a heart decision, and γ _li is always determined to be either +1 or −1.

The result of the above soft decision and the estimated distortion h
The principle of the automatic equalizer of the present invention is to obtain intersymbol interference using _o (n=±1, ±2, . . . , ±N) and subtract it from γ _l . Strain h _o (n=±1, ±2,
..., ±N) is estimated using the hard decision result for the automatic equalizer output and γ _lo (n=±1, ±
2, ..., ±N).

The figure is a block diagram showing one embodiment of the automatic equalizer of the present invention.

This will be explained below with reference to the figures.

An embodiment of the automatic equalizer will be explained in the case of three taps with reference to the drawings. Line 1 is an input line through which the signal to be equalized is input, and this input line is branched into two, one input to delay circuits 2-1 and 2-2, and the other input through soft decision circuit 3. It is stored in shift registers 4-1 and 4-2. 5-
1 and 5-2 are tap gain storage circuits that store tap gains, and multipliers 7-1 and 7-2 calculate the product of the soft decision results retrieved by taps 6-1 and 6-3 and the corresponding tap gains. be done. In this embodiment, it is considered that intersymbol interference for a certain transmission symbol occurs only from the symbol immediately before it and the symbol immediately after it, so that the outputs of multipliers 7-1 and 7-2 are It corresponds to the amount of intersymbol interference and the amount of intersymbol interference from the immediately following symbol. In order to obtain these quantities, especially the latter quantity, it is necessary to wait until the immediately following symbol is received. Therefore, the signal coming from line 1 passes through delay circuit 2-1 to tap 6-1. 2, and with subtractor 8,
The outputs of multipliers 7-1 and 7-2 are subtracted. Although the delay circuit 2-2 is not actually necessary, it is included here to clarify the time relationship with the delay circuits 4-1 and 4-2.

The output of the subtracter 8 is determined by a hard decision circuit 9. The difference between the above judgment result and the output signal of the subtracter 8 is obtained by the subtracter 10, and the product of this result and the signals of taps 6-1 and 6-3 is obtained by the multiplier 11.
-1 and 11-2 to obtain a tap gain correction value.

The automatic equalizer of the present invention is characterized in that the signal input to the delay line is replaced by the result of a soft decision of the input signal, whereby the delay line can be replaced with a shift register, Also, the product calculation circuit can be simplified,
The effect is great.

[Brief explanation of the drawing]

The figure is a block diagram showing one embodiment of the automatic equalizer of the present invention. In the figure, 3 is a soft decision circuit, 2-1 and 2-2 are delay circuits, 4-1 and 4-2 are shift registers, and 7-1, 7-
2, 11-1 and 11-2 are multiplication circuits, and 5
-1 and 5-2 are tap gain storage devices,
8 is a subtracter, 9 is a hard decision circuit, and 10 is a subtracter.

Claims (1)

[Claims] 1. In an automatic equalizer for data transmission, a first delay circuit that delays a received signal, a tentative decision circuit that tentatively decides the received signal, a second delay circuit that delays the tentative decision result, and a tap coefficient. a tap coefficient storage circuit that stores the sum of products of each of the outputs of the second delay circuit and each of the outputs of the tap coefficient storage circuit; and an output of the first delay circuit. An automatic equalizer comprising: a subtraction circuit that subtracts the output of the product-sum circuit from , and a determination circuit that determines the output of the subtraction circuit.