JPS625672B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate control circuit in, for example, an automatic mail sorting, sorting, stamping machine.

Generally, in automatic mail sorting, sorting, and stamping machines, a detection unit detects stamps, etc. on the mail, and the type of mail is determined based on the detection result.
The mail is transported to a collection section according to its type. At this time, the mail is transported by a detector and a gate provided on the transport path.

That is, FIG. 1 is a diagram schematically showing the arrangement mechanism section of the automatic mail sorting, arrangement, and stamping machine.
In the figure, 1 is a conveyance path, and detectors 2s, 2a, 2b, 2c, and 2d are provided in the middle of this conveyance path 1. These detectors 2s, 2a, 2b, 2
2d and 2d each output a signal by detecting the leading edge of the mail item being conveyed through the conveyance path 1, and each is constituted by a photoelectric switch or the like. For example, when the detector 2s detects the leading edge of the mail piece, it outputs a set signal, and the detector 2s outputs a set signal.
When the terminals a, 2b, 2c, and 2d detect the leading edge of the mail, they output a set signal as shown in FIG. 2, and after a predetermined period of time, they output a reset signal. Furthermore, gates 3a, 3b, and 3c are provided in the middle of the conveyance path 1. These gates 3a, 3b, and 3c allow the mail conveyed along the conveyance path 1 to pass through as is, or to accumulate them in the corresponding stacking sections 4a, 4b, and 4c, respectively. Note that mail that passes through the gate 3c without being driven is stacked in the stacking section 4d.

FIG. 3 schematically shows a gate control circuit for driving and controlling the gates 3a, 3b, and 3c. A signal corresponding to which of the stacking sections 4a, 4b, and 4c the mail is to be conveyed, that is, a logic "1" signal, is sent from a mail discrimination circuit (not shown) to a D-type flip-flop circuit (hereinafter simply referred to as FF circuit) 11. ₁ , 11 ₂ , and 11 ₃ are supplied to each data input terminal D. The above FF circuits 11 ₁ , 11 ₂ ,
Each clock pulse input terminal Cp of ₁₁₃ is supplied with a set signal 2sS from the detector 2s, and each reset input terminal R is supplied with a reset signal 2aR from the detector 2a. The above FF circuit 11 ₁ , 11
The set outputs of ₂ , 11 and ₃ are respectively sent to the FF circuit 12.
₁ , 12 ₂ , and 12 ₃ are supplied to each data input terminal D. These FF circuits 12 ₁ , 12 ₂ , 12 ₃
A leading detector 2 is installed at each clock pulse input terminal Cp.
A set signal 2aS is supplied from the detector 2a, and a reset signal 2bR is supplied from the detector 2b to each reset input terminal R of the FF circuits ₁₂₂ and ₁₂₃ .
The set output (gate drive signal) of the FF circuit ₁₂₁ is supplied to a drive circuit (not shown), and the drive circuit drives the gate 3a based on this signal. The above FF circuits 12 ₂ , 12 ₃
The set outputs of FF circuits 13 ₁ and 13 ₂ respectively
is supplied to each data input terminal D of. These FF
Each clock pulse input terminal of circuits ₁₃₁ and ₁₃₂
A set signal 2bS is supplied from the detector 2b to Cp, and a reset input terminal R of the FF circuit ₁₃₂ is supplied to Cp.
A reset signal 2cR is supplied from the detector 2c. The set output (gate drive signal) of the FF circuit ₁₃₁ is supplied to a drive circuit (not shown), and this signal causes the drive circuit to
b. Above FF circuit 1
The set output of ₃₂ is supplied to the data input terminal D of the FF circuit 14. The clock pulse input terminal Cp of this FF circuit 14 is supplied with the set signal 2cS of the detector 2c. The set output (gate drive signal) of the FF circuit 14 is supplied to a drive circuit (not shown), and the drive circuit drives the gate 3c based on this signal.

The operation in such a configuration will be explained. For example, if mail is to be transported to the stacking section 4a, a logic "1" signal is supplied to the input terminal D of the FF circuit ₁₁₁ . When the mail reaches the detector 2s, a set signal 2sS is sent from the detector 2s.
is output. As a result, the FF circuit ₁₁₁ is set, and its set output is output to the FF circuit ₁₂₁ . Thereafter, when the mail reaches the detector 2a, a set signal 2aS is output from the detector 2a. Then, the FF circuit ₁₂₁ is set, and the set output, that is, the gate drive signal, drives the gate 3a. This allows the mail to be stored in the stacking section 4.
transported to a. Further, the same operation is performed when mails are accumulated in the other accumulation sections 4b and 4c.

However, with the gate control circuit as described above, when mail is not conveyed in the correct direction due to malfunction of the gate, it is not possible to detect the malfunction.

This invention was made in view of the above circumstances,
The purpose of this invention is to provide a gate control circuit that can detect a malfunction of the gate when the paper sheets being conveyed are not conveyed in the correct direction due to the malfunction of the gate.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 shows a gate control circuit according to the present invention, and parts having the same functions as those in FIG. 2 are given the same reference numerals, and a detailed description thereof will be omitted.

The set output, ie, the gate drive signal, of the FF circuit ₁₂₁ is supplied to the data input terminal D of the FF circuit ₂₁₁ . The clock pulse input terminal Cp of this FF circuit ₁₂₁ receives a set signal 2 from the detector 2b.
bS is supplied. The set output of the FF circuit ₂₁₁ is supplied to a display (not shown), and this signal lights up the display.
Further, the set output, that is, the gate drive signal of the FF circuit ₁₃₁ is connected to the data input terminal D of the FF circuit ₁₂₂ .
is supplied to A set signal 2cS is supplied from the detector _2c to the clock pulse input terminal Cp of the FF circuit 212. The set output of the FF circuit ₂₁₂ is supplied to a display (not shown), and this signal lights up the display. Furthermore, the set output, ie, the gate drive signal, of the FF circuit 14 is supplied to the data input terminal D of the FF circuit ₂₁₃ . A set signal 2dS is supplied from the detector 2d to the clock pulse input terminal Cp of the FF circuit ₂₁₃ . The above FF circuit 21
The set output of ₃ is supplied to a display (not shown),
This signal drives the display.

The operation in such a configuration will be explained. For example, if mail is to be transported to the stacking section 4a, a logic "1" signal is supplied to the input terminal D of the FF circuit ₁₁₁ . When the mail reaches the detector 2s, a set signal 2sS is sent from the detector 2s.
is output. As a result, the FF circuit ₁₁₁ is set, and its set output is output to the FF circuit ₁₂₁ . Thereafter, when the mail reaches the detector 2a, a set signal 2aS is output from the detector 2a. Then, the FF circuit ₁₂₁ is set, and its set output, that is, the gate drive signal is sent to the FF circuit 1.
2 is supplied to a drive circuit (not shown) corresponding to ₁ . At this time, if the drive circuit does not work for some reason and does not drive the gate 3a, the mail will reach the detector 2b via the gate 3a without being conveyed to the stacking section 4a. As a result, a set signal 2bS is output from the detector 2b. At this time, since the gate drive signal is supplied from the FF circuit 12 ₁ to the FF circuit 21 ₁ , the FF circuit 21 ₁
is set, and the set output is output to a display (not shown) as a gate malfunction signal. This causes the display to light up, informing the operator that the gate 3a has malfunctioned. Further, even if the other gates 3b and 3c malfunction, they will operate in the same way.

In this manner, when the gates 3a, 3b, and 3c malfunction, the operator can be notified of the malfunction of those gates by lighting up the indicators corresponding to those gates, respectively.

In the above embodiments, the case where the detector is provided in the middle of the conveyance path has been described, but the same method can be applied to the case where the detector is provided in the accumulation section. Further, although the case where the present invention is applied to an automatic mail sorting, sorting, and stamping machine has been described, the present invention is not limited to this, and the same applies to other apparatuses.

As described in detail above, according to the present invention, the conveyance of paper sheets is detected by a detector provided in the middle of the conveyance path or in the stacking section, and a gate drive signal is output in accordance with this detection signal. Controlling the drive of a gate provided in the middle of the conveyance path,
In a gate control circuit that branches the paper sheets to a predetermined stacking section or another conveyance path, when the gate drive signal is output, a detection signal is output from a detector provided at a subsequent stage of the gate. Since a logic circuit is provided that outputs a gate malfunction signal when the gate malfunctions, it is possible to provide a gate control circuit that can detect malfunction when paper sheets are not conveyed in the correct direction due to gate malfunction. It is something.

[Brief explanation of the drawing]

Fig. 1 is a diagram schematically showing the arrangement mechanism section of an automatic mail sorting, arrangement and stamping machine, Fig. 2 is a waveform diagram showing the output signal of the detector, and Fig. 3 is a diagram schematically showing a conventional gate control circuit. , FIG. 4 is a schematic diagram showing an embodiment of the present invention. 1... Conveyance path, 2s, 2a, 2b, 2c, 2d
...Detector, 3a, 3b, 3c...Gate, 4
a, 4b, 4c, 4d...accumulation section, 21 ₁ , 21
₂ , 21 ₃ ...Flip-flop circuit.

Claims (1)

[Claims] 1. The conveyance of paper sheets is detected by a detector provided in the middle of the conveyance path or in the stacking section, and a gate drive signal is output in response to this detection signal, thereby controlling the gate provided in the middle of the conveyance path. In a gate control circuit that performs drive control and branches the paper sheets to a predetermined stacking section or another conveyance path, a detector provided at a stage subsequent to the gate when the gate drive signal is output. 1. A gate control circuit comprising a logic circuit that outputs a gate malfunction signal when a detection signal is output from the gate control circuit.