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JPS6256974B2 - - Google Patents
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JPS6256974B2 - - Google Patents

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Publication number
JPS6256974B2
JPS6256974B2 JP55021554A JP2155480A JPS6256974B2 JP S6256974 B2 JPS6256974 B2 JP S6256974B2 JP 55021554 A JP55021554 A JP 55021554A JP 2155480 A JP2155480 A JP 2155480A JP S6256974 B2 JPS6256974 B2 JP S6256974B2
Authority
JP
Japan
Prior art keywords
binary
signal
cutting
value
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55021554A
Other languages
Japanese (ja)
Other versions
JPS56118647A (en
Inventor
Mitsuyoshi Koizumi
Nobuyuki Akyama
Yoshimasa Ooshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2155480A priority Critical patent/JPS56118647A/en
Publication of JPS56118647A publication Critical patent/JPS56118647A/en
Publication of JPS6256974B2 publication Critical patent/JPS6256974B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01NINVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84Systems specially adapted for particular applications
    • G01N21/88Investigating the presence of flaws or contamination
    • G01N21/89Investigating the presence of flaws or contamination in moving material, e.g. running paper or textiles

Landscapes

  • Engineering & Computer Science (AREA)
  • Textile Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Biochemistry (AREA)
  • General Health & Medical Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Immunology (AREA)
  • Pathology (AREA)
  • Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
  • Closed-Circuit Television Systems (AREA)

Description

【発明の詳細な説明】 本発明は傷検査装置に係り、特に傷の形状種類
の自動判別可能な傷検査装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a flaw inspection device, and more particularly to a flaw inspection device capable of automatically determining the shape and type of flaws.

第1図は傷検査装置の全体構成を示す図であ
る。第1図において、レーザ管1より発振された
レーザ光は、回転多面鏡2の回転とレンズ3の作
用により、X方向に連続的に移動する試料4の表
面に集光され、試料4の表面全域を走査する。試
料4の表面の正常部は滑らかであるため、レーザ
光の反射光は逆にレンズ3に入射する。試料4の
表面に傷がある場合にはレーザ光の反射は散乱光
となり、光電管7の電流を励起する。光電管7は
乱反射光の有無を検出して映像信号を得る光電変
換手段である。信号処理装置8は光電管7の出力
信号を検出して傷の有無を判定する。
FIG. 1 is a diagram showing the overall configuration of a flaw inspection device. In FIG. 1, a laser beam oscillated from a laser tube 1 is focused on the surface of a sample 4 that is continuously moving in the X direction by the rotation of a rotating polygon mirror 2 and the action of a lens 3. Scan the entire area. Since the normal portion of the surface of the sample 4 is smooth, the reflected light of the laser beam is incident on the lens 3 instead. If there is a scratch on the surface of the sample 4, the reflection of the laser beam becomes scattered light, which excites the current in the phototube 7. The phototube 7 is a photoelectric conversion means that detects the presence or absence of diffusely reflected light and obtains a video signal. The signal processing device 8 detects the output signal of the phototube 7 and determines the presence or absence of a scratch.

試料面が金属加工面の場合には、孤立状の傷は
異物等の混入、ボイド等が原因であり、線状の傷
は荒加工時のカツタマークの残存(仕上げ加工の
不足),搬送時のこすれ等が原因である。前者は
修正不可であるが、後者は更なる仕上げ加工によ
り修正が可能である。
If the sample surface is a metal-processed surface, isolated scratches are caused by foreign matter, voids, etc., and linear scratches are caused by cutter marks remaining during rough machining (lack of finishing machining) or during transportation. This is caused by rubbing etc. The former cannot be modified, but the latter can be modified by further finishing.

しかし、従来の傷検査装置では、光電管7の出
力をデイジタル化して膨大なメモリに記憶し、こ
れを全体として処理することによつて傷の検出を
行なつているため、その傷の種類の判定の実時間
処理は不可能で、検査員による目視に依らざるを
得ず、自動判定は不可能であつた。
However, in conventional flaw inspection devices, flaws are detected by digitizing the output of the phototube 7, storing it in a huge memory, and processing it as a whole, so the type of flaw can be determined. It is impossible to process this in real time, and we have to rely on visual inspection by inspectors, making automatic judgment impossible.

本発明の目的は、上記した従来技術の欠点をな
くし、傷の種類まで自動的に実時間で判別可能な
傷検査装置を提供するにある。
SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to provide a flaw inspection device that can automatically determine the type of flaw in real time.

上記の目的を達成するために、本発明において
は、光電管により捉えた検査面に対応する二次元
パターンを、適当な大きさの小枠によつて順次切
り出し、この小枠内の傷パターンの連続性および
大小を実時間でしらべることによつて傷の有無お
よびその種類を自動判別するようにしたことを特
徴としている。
In order to achieve the above object, in the present invention, a two-dimensional pattern corresponding to the inspection surface captured by a phototube is sequentially cut out using small frames of an appropriate size, and a continuous flaw pattern within the small frames is cut out. The feature is that the presence or absence of scratches and their type can be automatically determined by checking the nature and size in real time.

以下、本発明を詳細に説明する。第2図は線状
傷9および孤立傷10とレーザ走査線i〜lの関
係を示す図であり、第3図は第1図の光電管出力
をデイジタル化して記憶するまでの処理波形を示
す図である。第3図にて、レーザ光の走査のタイ
ミング検出用としてのセンサ6の出力aは、一組
のしや光板5の間隔中(S→E)をレーザが走査
する前に発生する。センサ出力aの発生後、Δt
秒経過した時点で走査ゲートbを開き、この間の
光電管出力cを閾値により二値化して、二値化出
力ゲートdを得る。走査ゲートbが開いている間
はクロツクeがN個発生するので、このクロツク
eを二値化力dでゲートすると、二値化クロツク
fが得られる。
The present invention will be explained in detail below. FIG. 2 is a diagram showing the relationship between linear scratches 9 and isolated scratches 10 and laser scanning lines i to l, and FIG. 3 is a diagram showing processing waveforms until the phototube output in FIG. 1 is digitized and stored. It is. In FIG. 3, the output a of the sensor 6 for detecting the scanning timing of the laser beam is generated before the laser scans the interval (S→E) between the pair of optical plates 5. After generation of sensor output a, Δt
After a second has elapsed, scanning gate b is opened, and the phototube output c during this period is binarized using a threshold value to obtain a binarized output gate d. Since N clocks e are generated while the scanning gate b is open, when this clock e is gated with the binarization power d, a binarization clock f is obtained.

ここで、2値化クロツクとは、2値絵素化信号
である。この2値化クロツクを得るには、光電管
の出力である映像信号を所定の閾値によつて2値
化回路によつて2値化し、次いでサンプリングし
て得るようにする。これらは公知である。
Here, the binary clock is a binary pixel signal. In order to obtain this binarized clock, the video signal which is the output of the phototube is binarized by a binarization circuit using a predetermined threshold value, and then it is obtained by sampling. These are known.

このようにして得られた第2図に対応する二値
化クロツクの2次元パターンを第4図に示す。
FIG. 4 shows the two-dimensional pattern of the binarized clock corresponding to FIG. 2 obtained in this way.

本発明ではこのパターン中を適当な大きさ(m
×n絵素)の枠で走査し、各走査位置における枠
内の“1”の分布を計測することにより、孤立
傷,線状傷の判定を行なうものである。ただし枠
は第4図でSからEの方向へ、そしてi→lの方
向へと商用テレビの走査と同様な形で移動する。
In the present invention, an appropriate size (m
By scanning a frame of xn picture elements) and measuring the distribution of "1" within the frame at each scanning position, isolated flaws and linear flaws are determined. However, the frame moves from S to E in FIG. 4 and from i to l in a manner similar to commercial television scanning.

第5図は二次元パターンをこの小枠で切り出し
ながら走査するための切り出し回路の構成を示す
図である。ただし第4図では簡単のため、枠の大
きさm×nを4×4としている。この切り出し回
路はNビツトの直列入力型シフトレジスタ50の
n−1個と、mビツトの直列入力並列出力型シフ
トレジスタ51のn個より構成され、二値化クロ
ツクfを入力として動作する。そしてn個のシフ
トレジスタ51が切り出し枠20を構成する。
FIG. 5 is a diagram showing the configuration of a cutout circuit for scanning a two-dimensional pattern while cutting it out using this small frame. However, in FIG. 4, the size of the frame m×n is set to 4×4 for simplicity. This extraction circuit is composed of n-1 N-bit serial input type shift registers 50 and n m-bit serial input parallel output type shift registers 51, and operates with a binary clock f as input. The n shift registers 51 constitute the cutting frame 20.

第6図〜第11図はこの回路の動作説明図で、
第6図はクロツクが走査線lの4つ目(右から)
の“1”に対応した時間での切り出し回路のビツ
トパターンを示す。クロツクが順次進み走査線l
の12個目の“0”に対応した時間でのビツトパタ
ーンが第7図である。次の走査線の1つ目の
“0”でのビツトパターンが第8図、2つ目の
“0”でのビツトパターンが第9図、3つ目の
“0”でのビツトパターンが第10図、4つ目の
“0”でのビツトパターンが第11図に示されて
いる。このように各走査開始点よりm−1個目迄
は、切り出し回路のm×n(=4×4)絵素と2
次元パターンとは一致しないため、この間は後述
する傷の判定を行わない。
Figures 6 to 11 are diagrams explaining the operation of this circuit.
In Figure 6, the clock is the fourth scanning line l (from the right)
The bit pattern of the extraction circuit at the time corresponding to "1" is shown. The clock advances sequentially and the scanning line l
Figure 7 shows the bit pattern at the time corresponding to the 12th "0". The bit pattern for the first "0" of the next scanning line is shown in Figure 8, the bit pattern for the second "0" is shown in Figure 9, and the bit pattern for the third "0" is shown in Figure 9. The bit pattern at the fourth "0" in FIG. 10 is shown in FIG. In this way, from the start point of each scan to the m-1th pixel, there are m×n (=4×4) picture elements and 2 pixels of the extraction circuit.
Since it does not match the dimensional pattern, the flaw determination described later is not performed during this time.

第12図は、以上の様にして切り出された切り
出し枠20の傷の有無およびその形状をしらべる
判定方法を示す。すなわち、次の如くなる。
FIG. 12 shows a determination method for examining the presence or absence of scratches on the cutout frame 20 cut out in the above manner and the shape thereof. That is, it becomes as follows.

イ 枠の周囲に“1”が無い場合(接触が無
い)。
B. When there is no “1” around the frame (no contact).

枠の内部の“1”の合計値をSとして、設定値
S0との比較をして、SがS0より小の場合は良品、
SがS0より大きい場合には孤立傷とする。ここ
で、S0の値を適当に設定すれば、微小な傷を許容
し、大きな傷のみを不良としたり、また微小傷も
不良とすることができる。
The total value of “1” inside the frame is set as S, and the set value
Compare with S 0 , if S is smaller than S 0 , it is a good product.
If S is greater than S 0 , it is considered an isolated flaw. Here, by appropriately setting the value of S 0 , it is possible to allow minute scratches and to treat only large scratches as defective, or to treat even minute scratches as defective.

ロ 枠の周囲に“1”が有る場合(接触が有
る)。
(b) When there are “1”s around the frame (there is contact).

枠の上端と下端に“1”が有る時(U〓D)と
枠の左端と右端に“1”が有る時(L〓R)に限
り(対辺接触)、枠内の“1”の合計値Sを計数
する。設定値S1とSの比較を行い、SがS1より小
の場合は良品、SがS1より大の場合には線状傷と
判定する。ここでS1を適当な値に設定することに
より、断続的な線状傷の検出も行える。枠の周囲
に“1”が有る場合でも、左端と上端に“1”が
有る時のような隣辺接触や、一端のみの接触の時
には無条件に良品とする。この理由を第13図に
より説明する。
Only when there is a “1” at the top and bottom of the frame (U〓D) and when there is a “1” at the left and right ends of the frame (L〓R) (opposite side contact), the sum of “1” in the frame Count the value S. The set value S1 is compared with S, and if S is smaller than S1 , it is judged to be a good product, and if S is larger than S1 , it is judged to be a linear flaw. By setting S 1 to an appropriate value, intermittent linear flaws can also be detected. Even if there are "1"s around the frame, if there is contact on the adjacent side, such as when there are "1"s at the left end and top end, or if only one end is in contact, it is unconditionally considered to be a good product. The reason for this will be explained with reference to FIG.

枠がaの位置では“1”の群がbに示す実線部
分の大きさか点線部分の大きさかの判断が出来な
いので、判定は行なわない。(とりあえず良品と
する)これは枠がbの1点鎖線位置に来て判定が
行なわれる。cの一辺接触の時も同様である。枠
がdの実線の位置では隣辺接触のため判定は行な
わないが、一点鎖線位置で対辺接触となり判定を
行う。eのような過大傷の場合にはU〓Dの対辺
接触となり、S≧S0ならば線状傷と判定する。
When the frame is at position a, it cannot be determined whether the group of "1"s is the size of the solid line portion or the dotted line portion shown at b, so no determination is made. (It is assumed to be a good product for the time being.) This determination is made when the frame comes to the position indicated by the dashed-dotted line b. The same thing applies when one side of c is in contact. At the position of the solid line with frame d, no determination is made because the adjacent side is in contact, but at the position of the dashed dotted line, the opposite side is in contact and a determination is made. In the case of an excessive scratch like e, the opposite side contacts U〓D, and if S≧S 0 , it is determined to be a linear scratch.

第14図は、第13図の判定方法を実行するた
めの判定回路例を示す図である。第14図におい
て、切り出し枠20の周辺の各絵素は、各々オア
ゲート11〜14に結線され、信号U,D,R,
Lは各端に接触がある場合には、“1”となる。
従つてアンドゲート15の出力が“1”の場合に
は、対辺接触U〓Dが、アンドゲート16の出力
が“1”の場合には、対辺接触L〓Rがあること
を示し、オアゲート17の出力が“1”の場合に
は対辺接触があることを示す。また、オアゲート
18、インバータ19の動作により、インバータ
19の出力が“1”の時は、切り出し枠20の周
辺に“1”がないことを示す。一方、枠内の
“1”の計数回路24で計数された値Sと、設定
回路26で予め設定された値S1、および設定回路
28で予め設定された値S0とが比較回路25およ
び27で比較され、Sが各々設定値S1,S0より大
なる時に比較回路出力が“1”となる。従つてア
ンドゲート29の出力は線状傷のあるとき
“1”、アンドゲート31の出力は孤立傷のあると
き“1”となる。これらの信号はさらにアンドゲ
ート41,42に入力される。これは、カウント
回路41Aが、切り出し枠20の各水平方向の走
査開始からm−1個目のクロツクまで“0”とな
り、判定を行なわないようにするために設けられ
ている。
FIG. 14 is a diagram showing an example of a determination circuit for carrying out the determination method of FIG. 13. In FIG. 14, each picture element around the cutting frame 20 is connected to the OR gates 11 to 14, and the signals U, D, R,
L becomes "1" when there is contact at each end.
Therefore, when the output of the AND gate 15 is "1", it indicates that there is a contact on the opposite side U〓D, and when the output of the AND gate 16 is "1", it indicates that there is a contact on the opposite side L〓R, and the OR gate 17 When the output is "1", it indicates that there is contact between opposite sides. Furthermore, when the output of the inverter 19 is "1" due to the operation of the OR gate 18 and the inverter 19, it indicates that there is no "1" around the cutting frame 20. On the other hand, the value S counted by the counting circuit 24 of "1" in the frame, the value S 1 preset by the setting circuit 26, and the value S 0 preset by the setting circuit 28 are compared to the comparison circuit 25 and 27, and when S is larger than the respective set values S 1 and S 0 , the comparison circuit output becomes "1". Therefore, the output of the AND gate 29 becomes "1" when there is a linear flaw, and the output of the AND gate 31 becomes "1" when there is an isolated flaw. These signals are further input to AND gates 41 and 42. This is provided so that the count circuit 41A becomes "0" from the start of scanning of the cutting frame 20 in each horizontal direction until the m-1th clock and does not perform any determination.

第15図は第14図のsの計数回路24の回路
例を示す図であり、切り出し枠20中の全ての絵
素より出力された線は重みなし係数カウンタ21
の入力となる。係数カウンタ21は入力の“1”
の個数をビツト2,2,2で出力する。係
数カウンタの2ケの出力を4ビツト全加算器22
に入力する。全加算器22の2ケの出力を更に4
ビツト全加算器22に入力する。このようにして
切り出し回路中m×n絵素内の“1”の合計Sは
ラツチ23にラツチされる。
FIG. 15 is a diagram showing a circuit example of the counting circuit 24 of s in FIG.
becomes the input. Coefficient counter 21 inputs “1”
Outputs the number of bits 2 0 , 2 1 , 2 2 . The two outputs of the coefficient counter are transferred to a 4-bit full adder 22.
Enter. The two outputs of the full adder 22 are further
It is input to the bit full adder 22. In this way, the sum S of "1"s in the m.times.n picture elements in the extraction circuit is latched in the latch 23.

第16図は本発明の一実施例を示す図で、この
実施例では、切り出し枠3のmビツトシストレジ
スタをm+1ビツトに拡張し、この第m+1ビツ
ト目を出力端としてここの“1”の個数をカウン
タ32で計数することにより、切り出し枠移動時
に失なわれる“1”の個数Bを計数している。一
方、切り出し枠3の入力端の“1”の個数Aはカ
ウンタ31で計数され、これは切り出し枠3の移
動時に新しくふえる“1”の個数である。このよ
うにすると切り出し枠3からの結線は2n本でよ
く、かつカウンタ31,32も極めて小さいもの
でよい。
FIG. 16 is a diagram showing an embodiment of the present invention. In this embodiment, the m-bit register in the extraction frame 3 is expanded to m+1 bits, and the "1" here is set as the m+1-th bit as the output terminal. By counting the number with a counter 32, the number B of "1"s lost during the movement of the cutting frame is counted. On the other hand, the number A of "1"s at the input end of the cutout frame 3 is counted by the counter 31, and this is the number of "1"s newly increased when the cutout frame 3 is moved. In this way, the number of connections from the cutting frame 3 may be 2n, and the counters 31 and 32 may also be extremely small.

カウンタ31,32の出力A,Bは減算器33
に入力されて差A−Bが出力され、移動直前の
“1”の個数Sと加算器34で加えられ、新しい
計数値Sとしてラツチ35にラツチされる。
The outputs A and B of the counters 31 and 32 are the subtracter 33
The difference A-B is output, added to the number S of "1"s immediately before the movement in an adder 34, and latched in a latch 35 as a new count value S.

走査ゲートbは第4図の横方向走査の間オンす
る信号で、クロツクeはその走査の各サンプリン
グ時刻を指定する。従つてアンドゲート36の出
力をカウンタ37で計数し、設定回路39の設定
値mと比較回路38で比較する。カウンタ37の
計数値がmより小さい間は切り出し枠3の右方は
第4図の二次元パターンからはみ出し、枠3の移
動によつて失なわれる“1”はないので、この間
は比較回路38の出力によつてアンドゲート40
をオフにし、B=0としておく。また、センサ出
力aはレーザ光による加工面走査が折り返す時
点、すなわち二次元パターンの横方向の一走査が
終了して次の走査が始まるときに出力を出すの
で、この信号aによりカウンタ37とラツチ35
の内容をクリアして新しい走査に備える。
Scan gate b is a signal that is turned on during the horizontal scan of FIG. 4, and clock e specifies each sampling time of that scan. Therefore, the output of the AND gate 36 is counted by the counter 37 and compared with the set value m of the setting circuit 39 by the comparison circuit 38. While the count value of the counter 37 is smaller than m, the right side of the cutting frame 3 protrudes from the two-dimensional pattern of FIG. AND gate 40 by the output of
Turn off and set B=0. Furthermore, since the sensor output a is output when the scanning of the machined surface by the laser beam turns around, that is, when one horizontal scan of the two-dimensional pattern ends and the next scan begins, this signal a causes the counter 37 and the latch to be output. 35
Clear the contents of and prepare for a new scan.

カウンタ31,32は、第16図のように構成
しても比較的小さくできるが、これらのカウンタ
機能にROMを用いればより簡単な回路にでき
る。すなわち、切り出し枠3のたて方向をnビツ
トとしたとき、2n−1個以上のアドレスを持つ
ROMを用意し、例えば切り出し枠3の入力端n
ビツトをROMのアドレスに対応して結線する。
つまり、入力端nビツトを2進級とみてこれによ
りROMのアドレスを指定するようにする。そし
て、ROMの各番地の内容には、そのアドレス2
進表現に含まれる“1”の個数を記憶させてお
く。例えばn=11の例を第17図に示す。このよ
うにするとROMのアドレス指定により直ちに
“1”の個数が出力される。
The counters 31 and 32 can be made relatively small even if configured as shown in FIG. 16, but if a ROM is used for these counter functions, the circuit can be made simpler. In other words, when the vertical direction of the cutting frame 3 is n bits, there are 2 n -1 or more addresses.
Prepare a ROM, for example, input end n of cutting frame 3.
Connect the bits according to the ROM address.
In other words, the n bits at the input terminal are regarded as binary, and the ROM address is specified using this. The contents of each address in the ROM include the address 2
The number of "1"s included in the decimal representation is stored. For example, an example where n=11 is shown in FIG. In this way, the number of "1"s is immediately output by specifying the address of the ROM.

以上の説明から明らかなように、本発明によれ
ば、比較的小さい切り出し枠を次々と実時間で処
理できるから、傷の有無およびその種類の自動判
定が可能となり、また試料面に対応する二次元パ
ターンも切り出し回路で説明したように小さい記
憶容量のレジスタに格納できるので、大容量の記
憶装置を必要としないという効果がある。
As is clear from the above explanation, according to the present invention, relatively small cutting frames can be processed one after another in real time, so it is possible to automatically determine the presence or absence of scratches and their type, and also to automatically determine the presence or absence of scratches and the type of scratches. Since the dimensional pattern can also be stored in a register with a small storage capacity as explained in connection with the extraction circuit, there is an advantage that a large-capacity storage device is not required.

なお、本発明の傷の形状判定方法は、血液中の
赤血球濃度の自動測定や、溶液中の混入異物の大
きさの自動測定等にも応用可能である。
The wound shape determination method of the present invention can also be applied to automatic measurement of the concentration of red blood cells in blood, automatic measurement of the size of foreign substances mixed in a solution, etc.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は傷検査装置の全体構成を示す図、第2
図は試料面の走査の様子を示す図、第3図は試料
面走査により二次元デイジタル信号パターンを得
るための回路動作説明図、第4図は得られた二次
元パターンの例を示す図、第5図は切り出し回路
の構成図、第6図〜第11図は切り出し回路の動
作説明図、第12図および第13図は傷の有無お
よび形状の判定方法を示す図、第14図は第13
図の方法を実行する判定回路の構成例を示す図、
第15図は切り出し枠内の“1”の計数回路例を
示す図、第16図は他の計数回路の実施例図、第
17図はROM内容を示す図である。 1……レーザ管、4……試料、7……光電管、
8……信号処理回路、9……線状傷、10……孤
立傷、20……切り出し枠、24……計数回路、
25,27……比較回路、26,28……設定回
路、f……二値化クロツク。
Figure 1 shows the overall configuration of the flaw inspection device, Figure 2 shows the overall configuration of the flaw inspection device.
The figure shows how the sample surface is scanned, FIG. 3 is an explanatory diagram of the circuit operation for obtaining a two-dimensional digital signal pattern by scanning the sample surface, and FIG. 4 is a diagram showing an example of the obtained two-dimensional pattern. FIG. 5 is a block diagram of the extraction circuit, FIGS. 6 to 11 are explanatory diagrams of the operation of the extraction circuit, FIGS. 12 and 13 are diagrams showing a method for determining the presence or absence of scratches and their shape, and FIG. 13
A diagram showing an example of the configuration of a determination circuit that executes the method shown in the figure.
FIG. 15 is a diagram showing an example of a counting circuit for "1" within the cutout frame, FIG. 16 is a diagram of another embodiment of the counting circuit, and FIG. 17 is a diagram showing ROM contents. 1... Laser tube, 4... Sample, 7... Phototube,
8... Signal processing circuit, 9... Linear flaw, 10... Isolated flaw, 20... Cutting frame, 24... Counting circuit,
25, 27... Comparison circuit, 26, 28... Setting circuit, f... Binarization clock.

Claims (1)

【特許請求の範囲】[Claims] 1 試料面上をレーザ光により走査し、該試料面
からの乱反射光の有無を検出して映像信号に変換
する光電変換装置と、該光電変換装置から得られ
る映像信号を所定の閾値によつて2値化すると共
にサンプリングして2値絵素化信号に変換する2
値化回路と、該2値化回路によつて得られた2値
絵素化信号をシフトレジスタ群によつてm×nの
メモリ手段にm×nの絵素からなる2値化画像枠
として切り出す切り出し手段と、該切り出し手段
によつて切り出される2値化画像枠の範囲内の傷
有の2値絵素化信号を計数する計数回路と、上記
切り出し手段によつて切り出された2値化画像枠
の内、周囲の4辺に切り出された傷有の2値絵素
化信号の論理和をとつて周囲の4辺に亘つて傷無
の2値絵素化信号を検出する第1のゲート手段
と、計数回路によつて計数された切り出し枠内で
の計数値Sと所定の設定値S0とを比較して値Sが
該設定値S0を越えたとき孤立傷が存在すると判定
する第1の判定手段と、上記切り出し手段によつ
て切り出された2値化画像枠の内、周囲の各4辺
毎に切り出された傷有の2値絵素化信号を各4辺
別々に論理和をとり、これら論理和の内、対向す
る辺の論理和信号の論理積をとり、更にこれら論
理積信号の論理和をとり、対向する辺上に傷有の
2値絵素化信号を検出する第2のゲート手段と、
且つ比較手段で上記計数回路によつて計数された
切り出し枠内での計数値Sと所定の設定値S1とを
比較して値Sが該設定値S1を越えたとき線状傷が
存在すると判定する第2の判定手段とを備え付け
たことを特徴とする傷検査装置。
1. A photoelectric conversion device that scans a sample surface with a laser beam, detects the presence or absence of diffusely reflected light from the sample surface, and converts it into a video signal; Binarize and sample to convert into a binary pixel signal 2
A digitizing circuit and a binary picture element signal obtained by the binarizing circuit are stored in an m×n memory means as a binarized image frame consisting of m×n picture elements by a group of shift registers. A cutting means for cutting out, a counting circuit for counting the damaged binary pixelized signal within the range of the binarized image frame cut out by the cutting means, and a binarized signal cut out by the cutting means. The first step is to calculate the logical sum of the binary pixelated signals with scratches cut out on the four surrounding sides of the image frame to detect the unblemished binary pixelated signals on the four surrounding sides. Comparing the count value S within the cutting frame counted by the gate means and the counting circuit with a predetermined set value S0 , and when the value S exceeds the set value S0 , it is determined that an isolated flaw exists. and a first determining means for determining the flawed binary pixelated signal cut out for each of the four surrounding sides of the binarized image frame cut out by the cutout means, separately for each of the four sides. Take the logical sum, take the logical product of the logical sum signals of the opposite sides of these logical sums, and then take the logical sum of these logical product signals, and create a damaged binary pixelated signal on the opposite side. second gating means for detecting;
In addition, when the comparison means compares the counted value S within the cutting frame counted by the counting circuit with a predetermined set value S1 , and the value S exceeds the set value S1 , a linear flaw exists. A flaw inspection device characterized in that it is equipped with a second determining means that determines whether
JP2155480A 1980-02-25 1980-02-25 Flaw inspecting apparatus Granted JPS56118647A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2155480A JPS56118647A (en) 1980-02-25 1980-02-25 Flaw inspecting apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2155480A JPS56118647A (en) 1980-02-25 1980-02-25 Flaw inspecting apparatus

Publications (2)

Publication Number Publication Date
JPS56118647A JPS56118647A (en) 1981-09-17
JPS6256974B2 true JPS6256974B2 (en) 1987-11-28

Family

ID=12058216

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2155480A Granted JPS56118647A (en) 1980-02-25 1980-02-25 Flaw inspecting apparatus

Country Status (1)

Country Link
JP (1) JPS56118647A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59196446A (en) * 1983-04-22 1984-11-07 Toshiba Corp Defect recognizing device
DE4304678C1 (en) * 1993-02-16 1994-07-21 Kurandt System Gmbh Method for continuously scanning and checking track applications on a moving surface and device for carrying out the method
CN104406517A (en) * 2014-11-12 2015-03-11 昆山万像光电有限公司 Multi-station laser scanning measuring method for flatness
CN110763690B (en) * 2019-11-14 2022-04-12 上海精测半导体技术有限公司 Surface detection device and method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54133022A (en) * 1978-04-07 1979-10-16 Hitachi Ltd Comparison and inspection system for two dimensional picture
JPS5594147A (en) * 1979-01-12 1980-07-17 Kobe Steel Ltd Method of discriminating surface flaw of high temperature material to be detected

Also Published As

Publication number Publication date
JPS56118647A (en) 1981-09-17

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